CN100371816C - TFT array substrate of liquid crystal display, liquid crystal display panel and manufacturing method thereof - Google Patents

Abstract

A thin film transistor (TFT) array substrate for a liquid crystal display comprises a substrate; a gate electrode located on the substrate; a gate dielectric layer covering the substrate and the gate electrode; a semiconductor layer located on the gate dielectric layer, and the semiconductor layer comprises a channel; a light shielding layer located in the semiconductor layer; a source electrode electrically connected to a portion of the semiconductor layer on one side of the channel; a drain electrode electrically connected to a portion of the semiconductor layer on the other side of the channel, and the drain electrode does not overlap with the gate electrode in the orthographic projection plane. The TFT structure provided by the present invention has a smaller coupling capacitance (Cgd), which can improve the feed-through effect problem of the known technology; in addition, the light shielding layer can reduce the leakage problem of this structure caused by light.

Description

TFT array substrate of liquid crystal display, liquid crystal display panel and manufacturing method thereof

technical field

The present invention relates to a liquid crystal display and a manufacturing method thereof, in particular to a thin film transistor (TFT: Thin Film Transistor) of a liquid crystal display and a manufacturing method thereof.

Background technique

Liquid crystal display (LCD: liquid crystal display) is the mainstream of flat-panel display development at present. Its display principle is to use the dielectric anisotropy and conductive anisotropy of liquid crystal molecules to change the alignment state of liquid crystal molecules when an electric field is applied. Cause the liquid crystal film to produce various photoelectric effects. The panel structure of a liquid crystal display is generally formed by laminating two substrates, leaving a certain distance in the middle for filling liquid crystals, and corresponding electrodes are formed on the upper and lower substrates to control the direction and arrangement of liquid crystal molecules. FIG. 1 is a plan view of a thin film transistor structure in the prior art. The liquid crystal display uses thin film transistors as control switches, wherein the gate 102 overlaps the source 106 and the drain 104 on the front projection plane. However, because there is a coupling capacitor (hereinafter referred to as Cgd) at the gate 102 and drain 104 of the thin film transistor, when the gate 102 is turned off, the pixel potential will be pulled down through the coupling capacitor, which is called the feed through effect. .

Generally speaking, the larger the coupling capacitance, the more serious the feed through effect. In the past, increasing the storage capacitor Cst is used to improve the feedthrough effect, but the increase of the storage capacitor Cst will lead to a decrease in aperture ratio. In addition, when exposure shift or etching unevenness occurs, the uniformity of the coupling capacitor Cgd will be poor, resulting in uneven phenomenon shot mura or flicker phenomenon at the mask junction. Reducing the coupling capacitance Cgd can improve the above disadvantages. In addition, the smaller the coupling capacitance Cgd, the mura caused by the uneven coupling capacitance Cgd is also less severe.

Contents of the invention

Therefore, according to the above problems, the purpose of the present invention is to provide a TFT structure that can reduce the coupling capacitance Cgd, so as to improve the feed through effect or various problems caused by excessive Cgd.

The invention provides a TFT array substrate of a liquid crystal display. It includes: a substrate; a gate is located on the substrate; a gate dielectric layer covers the substrate and the gate (gate); a semiconductor layer is located on the gate dielectric layer, and the semiconductor layer includes a channel; a light-shielding layer, located in the semiconductor layer; a source is electrically connected to a part of the semiconductor layer on one side of the channel; a drain is electrically connected to a part of the semiconductor layer on the other side of the channel, and the drain does not overlap the gate on the orthographic projection plane .

The invention provides a method for manufacturing a TFT array substrate of a liquid crystal display. First, a substrate is provided, and a gate is formed on the substrate; a gate dielectric layer is formed to cover the substrate and the gate (gate); a conductive layer (light-shielding material layer) is formed on or above the gate dielectric layer; removing the conductive layer above the gate to form an opening to expose the gate dielectric layer; forming a semiconductor layer on the conductive layer and filling the opening, wherein the semiconductor layer includes a channel; forming a doped semiconductor layer on the semiconductor on the layer; pattern the doped semiconductor layer and the semiconductor layer, so that the doped semiconductor layer and the semiconductor layer protrude from the gate on at least one side of the front projection plane; use the doped semiconductor layer as a mask, etch the conductive layer to form A light-shielding layer is formed in the semiconductor layer to shield part of the semiconductor layer; a source electrode is formed to electrically connect part of the semiconductor layer on one side of the channel; a drain electrode is formed to electrically connect part of the semiconductor layer on the other side of the channel, wherein the drain electrode is in The orthographic projection plane does not overlap the grid.

The invention provides a liquid crystal display panel, which comprises:

a first substrate;

a second substrate relative to the first substrate;

A thin film transistor is disposed on the first substrate, and the thin film transistor includes:

a gate located on the first substrate;

a gate dielectric layer covering the substrate and the gate;

a semiconductor layer on the gate dielectric layer, the semiconductor layer including a channel;

a light-shielding layer located in the semiconductor layer;

A source electrically connected to a part of the semiconductor layer on one side of the channel;

a drain electrically connected to part of the semiconductor layer on the other side of the channel, and the drain does not overlap the gate in the orthographic plane; and

A liquid crystal layer is sandwiched between the first substrate and the second substrate.

The beneficial effect of the present invention is that, the TFT array substrate provided by the present invention, its gate and drain do not overlap each other, has smaller coupling capacitance (Cgd), can improve the problem of feedthrough effect (feed through effect) in the prior art . In addition, the present invention further provides a light-shielding layer to reduce the problem of electric leakage caused by light in this structure.

Description of drawings

1 is a plan view of a thin film transistor structure in the prior art;

2A is a partial top view of a thin film transistor TFT array substrate according to an embodiment of the present invention;

2B is a partial bottom view of a thin film transistor TFT array substrate according to an embodiment of the present invention;

2C is a partial rear view of a thin film transistor TFT array substrate according to an embodiment of the present invention;

3A to 3L are schematic flow diagrams of a thin film transistor TFT array substrate according to an embodiment of the present invention;

Fig. 4 is the relationship diagram of bias voltage and coupling capacitance Cgd of the TFT structure in the prior art and the TFT structure of an embodiment of the present invention;

5 is a graph showing the relationship between the bias voltage and the off-state current of a TFT structure with a light-shielding layer and a TFT structure without a light-shielding layer according to an embodiment of the present invention;

6A is a partial top view of a thin film transistor TFT array substrate according to another embodiment of the present invention;

Fig. 6B is a sectional view along 6B-6B' among Fig. 6A;

7A is a partial top view of a thin film transistor TFT array substrate according to another embodiment of the present invention;

Figure 7B is a sectional view along 7B-7B' in Figure 7A;

8A is a partial top view of a thin film transistor TFT array substrate according to another embodiment of the present invention;

Fig. 8B is a cross-sectional view along 8B-8B' in Fig. 8A.

【Symbol Description】

Gate 102; Drain 104;

source 106; substrate 300;

grid 302; storage capacitor lower electrode 304;

contact metal pad 306; gate dielectric layer 308;

photoresist layer 310; light-shielding material layer 312;

semiconductor layer 314; doped semiconductor layer 316;

light-shielding layer 318; third conductive layer 320;

source 322; drain 324;

storage capacitor 326; storage capacitor upper electrode 328;

protective layer 330; transparent conductive layer 332;

pixel electrode 332a; contact electrode 332b;

Drain 602; Gate 604;

light-shielding layer 606; semiconductor layer 608;

source 610; drain 702;

grid 704; shading layer 706

semiconductor layer 708; source 710;

Channel 712; Gate insulating layer 714;

Drain 802; Gate 804;

light-shielding layer 806; semiconductor layer 808;

source 810; channel 812;

gate insulating layer 814 .

Detailed ways

The present invention will be described in detail below with examples. In icons or descriptions, the same figure numbers are used for similar or identical parts. In the diagrams, the shape or thickness of the embodiments may be exaggerated to simplify or facilitate labeling. Parts of the components in the diagrams will be explained by description, and the components that are not shown or described are in the form known to those skilled in the art. Furthermore, when it is stated that a layer is on a substrate or another layer, the layer may be directly on the substrate or another layer, or there may be an intervening layer therebetween.

FIG. 2A is a partial top view of a thin film transistor TFT array substrate according to an embodiment of the present invention. FIG. 2B is a partial bottom view of a thin film transistor TFT array substrate according to an embodiment of the present invention. 3I is a cross-sectional view of a thin film transistor TFT array substrate according to an embodiment of the present invention. Referring to FIGS. 2A , 2B and 3I , a gate 302 is located on a substrate 300 , and the gate 302 can be connected to a gate line 202 . A gate dielectric layer 308 covers the gate 302 and the substrate 300 . A light-shielding layer 318 is located on or above the gate dielectric layer 308 , and a photoresist layer may be sandwiched between the light-shielding layer 318 and the gate dielectric layer 308 . In one embodiment, on the orthographic projection surface of the substrate 300 , the light-shielding layer 318 contacts the gate 302 to completely cover the semiconductor layer 314 to prevent leakage current. In another embodiment, on the orthographic projection surface of the substrate 300 , the light shielding layer 318 is adjacent to the gate 302 with a gap d therebetween, as shown in FIG. 2C . In one embodiment, the semiconductor layer 314 covers a portion of the gate dielectric layer 308 and the light shielding layer 318 . Considering the channel, the semiconductor layer 314 needs to protrude from at least one end of the gate 302 in the direction of the orthographic projection plane.

Since the semiconductor layer 314 is a photosensitive material, it is easy to generate a photocurrent (photo current) after being irradiated with light, resulting in excessive leakage current of the TFT. Therefore, an embodiment of the present invention proposes a TFT structure, and the light shielding layer 318 is located in the protruding semiconductor layer 314. And adjacent to the gate dielectric layer 308 to avoid TFT leakage. A source 322 is located above the semiconductor layer 314 and overlaps part of the gate 302 on the orthographic plane of the substrate 300 . A drain 324 is located above the semiconductor layer 314 and does not overlap the gate 302 on the orthographic plane of the substrate 300 . In one embodiment, on the orthographic projection plane, the semiconductor layer 314 only protrudes from the gate 302 at one end, and the drain 324 overlaps the part of the semiconductor layer 314 protruding from the gate 302, so as to reduce the overlapping area of the gate and the drain. And reduce the coupling capacitance Cgd. In one embodiment, on the rear projection plane, the gate 302 and the light-shielding layer 318 completely cover the semiconductor layer 314 to prevent the semiconductor layer 314 from leaking due to light, as shown in FIG. 2B . In addition, a doped semiconductor layer 316 may be interposed between the source electrode 322 or the drain electrode 324 and the semiconductor layer 314 to provide lower contact resistance.

3A to 3L are schematic flow diagrams of a thin film transistor TFT array substrate according to an embodiment of the present invention. First, please refer to FIG. 3A , a substrate 300 such as a glass substrate is provided. Preferably, the substrate 300 can be an alkali-free glass substrate or a low-alkali glass substrate. Then, a first metal layer (not shown) is formed on the substrate 300 by a deposition method. The conductive layer (first metal layer) can be Ta, Mo, W, Ti, Cr, Al or a combination thereof or a stacked layer thereof. The above method for depositing a conductive layer may be a sputtering method (Physical Vapor Deposition) (PVD: Physica1 Vapor Deposition) or ion growth chemical vapor deposition (PECVD: Plasma Enhancement Chemical Vapor Deposition). The first metal layer on the substrate is patterned by known exposure and development methods to form the gate 302 , the bottom electrode 304 of the storage capacitor and the contact metal pad 306 .

Referring to FIG. 3B , a gate dielectric layer 308 is deposited on the gate 302 , the bottom electrode 304 of the storage capacitor, the contact metal pad 306 and the substrate 300 . The gate dielectric layer 308 can be silicon oxide, silicon nitride, silicon oxynitride or a combination thereof. Next, as shown in FIG. 3C , a photoresist layer 310 is formed on the gate dielectric layer 308 by a patterning method. Preferably, the photoresist layer 310 is a negative photoresist, so that subsequent processes can expose and define components from the back of the substrate. Then a light-shielding material layer 312 is deposited on the photoresist layer 310 . The light-shielding material layer 312 can be Ta, Mo, W, Ti, Cr, Al or a combination thereof or a stacked layer thereof, and a preferred method of depositing the light-shielding material layer 312 is a low-temperature process, for example: the above-mentioned deposition of a light-shielding material layer 312 The method can be a sputtering method (Physical Vapor Deposition) (PVD: Physical Vapor Deposition) or ion growth chemical vapor deposition (PECVD: Plasma Enhancement Chemical Vapor Deposition).

As shown in FIG. 3D, using the patterned conductive layer (gate 302, storage capacitor bottom electrode 304, contact metal pad 306) as a mask, exposure 311 is performed from the back of the substrate 300 to achieve self-alignment. The photoresist layer 310 is patterned in a manner. Thereafter, a lift-off step is performed. In this embodiment, since the photoresist layer 310 is a negative photoresist, a developing method can be used to remove the unexposed layer above the patterned conductive layer (gate 302, storage capacitor bottom electrode 304, contact metal pad 306). The photoresist layer 310, and because the unexposed photoresist layer 310 is removed, the light-shielding material layer 312 on the photoresist layer 310 is peeled off together, and the photoresist layer 310 and the light-shielding material layer 312 are patterned to Corresponding openings are formed above the corresponding gate 302 , storage capacitor bottom electrode 304 , and contact metal pad 306 . In this way, one mask can be reduced, but the present invention is not limited thereto. In the present invention, the light-shielding material layer 312 may be patterned by general photolithography and etching instead of the lift-off method.

As shown in FIG. 3E, a semiconductor layer 314 is deposited on the second metal layer (light-shielding material layer) 312, and filled in the above-mentioned openings, which respectively correspond to the gate 302, the lower electrode 304 of the storage capacitor and the contact metal pad. 306. A doped semiconductor layer 316 is deposited on the semiconductor layer 314 . In one embodiment, the semiconductor layer 314 may be composed of silicon, germanium, polycrystalline silicon or polycrystalline silicon. In addition, the doped semiconductor layer 316 can be silicon or germanium doped with phosphorus or arsenic to make it an n+ semiconductor layer, so as to provide a good contact with subsequent metal layers.

As shown in FIG. 3F , doped semiconductor 316 and semiconductor layer 314 are patterned by well-known photolithography and etching methods. In this step, the doped semiconductor 316 and the semiconductor layer 314 above the gate 302 and its adjacent regions and above the bottom electrode 304 of the storage capacitor are removed. In particular, at least one side of the doped semiconductor 316 and the semiconductor layer 314 protrudes beyond the gate 302 on the front projection plane. In this embodiment, one side of the doped semiconductor layer 316 and the semiconductor layer 314 protrudes from the gate 302 , but the invention is not limited thereto. As shown in FIG. 3G , using the patterned doped semiconductor layer 316 as a mask, an anisotropic etching is performed to etch the second metal layer (light-shielding material layer) 312 and the photoresist layer 310 thereunder. In this embodiment, the second metal layer (light-shielding material layer) in the semiconductor layer 314 is used as the light-shielding layer 318 to prevent backlight from irradiating the semiconductor layer 314 to generate photocurrent and cause leakage.

Next, as shown in FIG. 3H , a third conductive layer 320 is blanket deposited on the doped semiconductor 316 and the gate dielectric layer 308 . The third conductive layer 320 may be Ta, Mo, W, Ti, Cr, Al or a combination thereof or a stacked layer thereof. Then, as shown in FIG. 3I, the third conductive layer 320 and the doped semiconductor layer 316 are patterned by known photolithography and etching methods to form a source electrode 322 and a drain electrode 324 above the semiconductor layer 314, and to form a source electrode 322 and a drain electrode 324 on the storage capacitor 326 forms a storage capacitor upper electrode 328 . In particular, the drain 324 does not overlap the gate 302 on the orthographic projection, so as to reduce the coupling capacitance Cgd. In one embodiment, the drain 324 is located above the portion of the semiconductor layer 314 protruding from the gate 302.

Next, as shown in FIG. 3J , a protective layer 330 is blanket deposited on the source electrode 322 , the drain electrode 324 , the storage capacitor upper electrode 328 and the gate dielectric layer 308 . The passivation layer 330 may be composed of silicon nitride or silicon oxynitride. After that, the protective layer 330 and the upper electrode 328 of the storage capacitor are patterned. In particular, corresponding openings are formed above the storage capacitor 326 and the contact pad 306 . As shown in FIG. 3K , a transparent conductive layer 332 is blanket-deposited on the protection layer 320 and filled into the above-mentioned opening, so as to be electrically connected to the upper electrode 328 of the storage capacitor and the contact pad 306 . The transparent conductive layer 332 may be composed of ITO (Indium Tin Oxide). As shown in FIG. 3L , the transparent conductive layer 332 is patterned to form a pixel electrode 332 a connected to the storage capacitor 326 , and a contact electrode 332 b connected to the contact pad 306 .

FIG. 4 is a graph showing the relationship between the bias voltage and the coupling capacitance Cgd of the TFT structure in the prior art and the TFT structure of an embodiment of the present invention (the TFT structure in FIG. 2A ). As shown in FIG. 4 , the coupling capacitance Cgd of the structure 402 of an embodiment of the present invention is about 80% lower than that of the prior art. FIG. 5 is a graph showing the relationship between bias voltage and off-state current of a TFT structure 406 with a light-shielding layer and a TFT structure without a light-shielding layer 408 according to an embodiment of the present invention. As shown in FIG. 5 , when the Vds is 10V, the TFT structure 406 with a light-shielding layer can indeed effectively reduce the leakage current of the TFT of the embodiment of the present invention.

FIG. 6A is a partial top view of a thin film transistor TFT array substrate according to another embodiment of the present invention. Fig. 6B is a cross-sectional view along 6B-6B' in Fig. 6A. This embodiment of the present invention is similar to the embodiment of FIG. 2A , that is, the drain 602 does not overlap with the gate 604 on the orthographic projection plane. And a light shielding layer 606 is located in a semiconductor layer 608 to reduce leakage current. The difference is that the source 610 surrounds the drain 602 in a semi-arc shape, and there is a fixed distance between them. The semiconductor layer 608 is located under the source electrode 610 and the drain electrode 602 , and a part of its region may overlap with the source electrode 610 and the drain electrode 602 on the orthographic projection plane. The semiconductor layer 608 between the source and the drain is the channel 612 of the TFT. The gate 604 is located in the gate insulating layer 614 under the source 610 , the drain 602 and the semiconductor layer 608 , and is adjacent to a substrate 600 . It is particularly noted that the gate 604 and the drain 602 do not overlap each other in the orthographic projection.

FIG. 7A is a partial top view of a thin film transistor TFT array substrate according to another embodiment of the present invention. Fig. 7B is a cross-sectional view along 7B-7B' in Fig. 7A. This embodiment of the present invention is similar to the embodiment of FIG. 2A , that is, the drain 702 does not overlap with the gate 704 on the orthographic projection plane. And a light shielding layer 706 is located in a semiconductor layer 708 to reduce leakage current. The difference is that in this embodiment, the drain 702 is L-shaped, and the source 710 is an inverted L-shaped, and there is a fixed distance between them. The semiconductor layer 708 is located under the source electrode 710 and the drain electrode 702 , and a part of its region may overlap with the source electrode 710 and the drain electrode 702 on the orthographic projection plane. The gap of the semiconductor layer 708 between the source 710 and the drain 702 is the channel 712 of the TFT. The gate 704 is located in the gate insulating layer 714 under the source 710 , the drain 702 and the semiconductor layer 708 , and is adjacent to a substrate 700 . It is particularly noted that the gate 704 and the drain 702 do not overlap each other in the orthographic projection.

8A is a partial top view of a thin film transistor TFT array substrate according to another embodiment of the present invention. Fig. 8B is a cross-sectional view along 8B-8B' in Fig. 8A. This embodiment of the present invention is similar to the embodiment of FIG. 2A , that is, the drain 802 does not overlap with the gate 804 on the orthographic projection plane. And a light-shielding layer 806 is located in a semiconductor layer to reduce leakage current. The difference is that in this embodiment, the drain 802 is a rectangle, and the source 810 is a hook, and there is a fixed distance between them. The semiconductor layer 808 is located under the source electrode 810 and the drain electrode 802 , and a part of its area may overlap with the source electrode 810 and the drain electrode 802 on the orthographic projection plane. Part of the semiconductor layer located in the gap between the source 802 and the drain 810 is the channel 812 of the TFT. The gate 804 is located in the gate insulating layer 814 under the source 810 , the drain 802 and the semiconductor layer 808 , and is adjacent to a substrate 800 . It is particularly noted that the gate 804 and the drain 802 do not overlap each other in the orthographic projection.

In addition, the TFT array substrate formed in the above embodiment is a part of a liquid crystal display panel. The liquid crystal display also includes an upper substrate opposite to the TFT array substrate. In an embodiment, the upper substrate may be a color filter substrate. A liquid crystal layer may be sandwiched between the TFT array substrate (which may be referred to as the lower substrate herein) and the upper substrate. This part is well known to those skilled in the art, and it is not shown in the figure for simplicity.

In the TFT structure provided by the embodiment of the present invention, its gate and drain do not overlap each other, so the TFT structure provided by the present invention has a smaller coupling capacitance (Cgd), which can improve the feedthrough effect (feedthrough effect) problem of the known technology . In addition, the present invention further provides a light-shielding layer to reduce the problem of electric leakage caused by light in this structure.

The foregoing embodiments are only used to illustrate the present invention, but not to limit the present invention.

Claims (19)

1. A TFT array substrate of a liquid crystal display, characterized in that comprising: a substrate; a gate located on the substrate; a gate dielectric layer covering the substrate and the gate; a semiconductor layer on the gate dielectric layer, the semiconductor layer including a channel; a light-shielding layer located in the semiconductor layer; a source electrically connected to a portion of the semiconductor layer on one side of the channel; and A drain is electrically connected to a part of the semiconductor layer on the other side of the channel, and the drain does not overlap with the gate in an orthographic projection plane. 2. The TFT array substrate of a liquid crystal display according to claim 1, wherein the light-shielding layer is adjacent to the gate dielectric layer, and the light-shielding layer blocks the connection between the semiconductor layer and the grid on the front projection plane. The area outside the pole overlap. 3. The TFT array substrate of a liquid crystal display according to claim 1, wherein the light-shielding layer is made of opaque metal. 4 . The TFT array substrate of a liquid crystal display according to claim 2 , wherein a photoresist layer is interposed between the light-shielding layer and the gate dielectric layer. 5. The TFT array substrate of a liquid crystal display according to claim 4, wherein the photoresist layer is composed of a negative photoresist material. 6. The TFT array substrate of a liquid crystal display according to claim 1, wherein the semiconductor layer protrudes from the grid on one side of the front projection plane, and the drain overlaps the semiconductor layer protruding from the grid part. 7. the TFT array substrate of liquid crystal display as claimed in claim 1, is characterized in that, The source is in a semi-arc shape, surrounding the drain, and the two are separated by a fixed distance; The semiconductor layer is located under the source and the drain, and a part of its region overlaps with the source and the drain on the orthographic plane; and The semiconductor layer between the source and the drain is the channel of the thin film transistor. 8. the TFT array substrate of liquid crystal display as claimed in claim 1, is characterized in that, The drain is L-shaped; The source is in an inverted L shape with a fixed gap between them; The semiconductor layer is located under the source and the drain, and a part of its region overlaps with the source and the drain on the orthographic plane; and The semiconductor layer between the source and the drain is the channel of the thin film transistor. 9. the TFT array substrate of liquid crystal display as claimed in claim 1, is characterized in that, The drain is rectangular; The source is hook-shaped, and a part of the source is separated from the drain by a fixed gap; The semiconductor layer is located under the source and the drain, and part of its region overlaps part of the source and the drain on the orthographic plane; and The semiconductor layer between the source and the drain is the channel of the thin film transistor. 10. A method for manufacturing a TFT array substrate of a liquid crystal display, characterized in that it comprises: providing a substrate; forming a gate on the substrate; forming a gate dielectric layer covering the substrate and the gate; forming a light-shielding material layer on or above the gate dielectric layer; removing the light-shielding material layer above the gate to form an opening to expose the gate dielectric layer; forming a semiconductor layer on the light-shielding material layer and filling the opening, the semiconductor layer including a channel; forming a doped semiconductor layer on the semiconductor layer; patterning the doped semiconductor layer and the semiconductor layer, so that the doped semiconductor layer and the semiconductor layer protrude from the gate on at least one side of the front projection plane; Using the doped semiconductor layer as a mask, etching the light-shielding material layer to shield part of the semiconductor layer; forming a source electrically connected to a portion of the semiconductor layer on one side of the channel; and A drain is formed to be electrically connected to part of the semiconductor layer on the other side of the channel, wherein the drain does not overlap with the gate in an orthographic projection plane. 11 . The method for manufacturing a TFT array substrate of a liquid crystal display according to claim 10 , further comprising forming a photoresist layer on the gate dielectric layer before forming the light-shielding material layer. 12. The method for manufacturing a TFT array substrate of a liquid crystal display according to claim 11, wherein removing the light-shielding material layer above the gate comprises the following steps: using the gate as a mask to expose the photoresist layer from the back side of the substrate; and removing the unexposed photoresist layer, and peeling off the light-shielding material layer on the unexposed photoresist layer. 13. The manufacturing method of the TFT array substrate of liquid crystal display as claimed in claim 12, is characterized in that, described photoresist layer is negative photoresist, and removing described photoresist layer that is not exposed is a development step. 14. A liquid crystal display panel, characterized in that it comprises: a first substrate; a second substrate relative to the first substrate; A thin film transistor is disposed on the first substrate, and the thin film transistor includes: a gate located on the first substrate; a gate dielectric layer covering the substrate and the gate; a semiconductor layer on the gate dielectric layer, the semiconductor layer including a channel; a light shielding layer located in the semiconductor layer; A source electrically connected to a part of the semiconductor layer on one side of the channel; a drain electrically connected to part of the semiconductor layer on the other side of the channel, and the drain does not overlap the gate in the orthographic plane; and A liquid crystal layer is sandwiched between the first substrate and the second substrate. 15. The liquid crystal display panel according to claim 14, wherein the light-shielding layer is adjacent to the gate dielectric layer, and the light-shielding layer covers the semiconductor layer except that the front projection plane overlaps the gate Area. 16 . The liquid crystal display panel according to claim 14 , wherein the semiconductor layer protrudes from the gate on one side of the front projection plane, and the drain is electrically connected to a portion of the semiconductor layer protruding from the gate. 17. The liquid crystal display panel as claimed in claim 14, wherein, The source is in a semi-arc shape, surrounding the drain, and the two are separated by a fixed distance; The semiconductor layer is located under the source and drain, and a part of its region overlaps with the source and drain in the orthographic plane; and The semiconductor layer between the source and the drain is the channel of the thin film transistor. 18. The liquid crystal display panel as claimed in claim 14, wherein, The drain is L-shaped; The source is inverted L-shaped, and the source and drain are separated by a fixed gap; The semiconductor layer is located under the source and drain, and a part of its region overlaps with the source and drain in the orthographic plane; and The semiconductor layer between the source and the drain is the channel of the thin film transistor. 19. The liquid crystal display panel as claimed in claim 14, wherein, The drain is rectangular; The source is hook-shaped, and a part of the source is separated from the drain by a fixed gap; The semiconductor layer is located under the source and drain, and part of its region overlaps part of the source and drain on the orthographic plane; and The semiconductor layer between the source and the drain is the channel of the thin film transistor.

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