CN109671723A - A kind of tft array substrate - Google Patents
A kind of tft array substrate Download PDFInfo
- Publication number
- CN109671723A CN109671723A CN201811564889.0A CN201811564889A CN109671723A CN 109671723 A CN109671723 A CN 109671723A CN 201811564889 A CN201811564889 A CN 201811564889A CN 109671723 A CN109671723 A CN 109671723A
- Authority
- CN
- China
- Prior art keywords
- layer
- drain electrode
- tft array
- metal layer
- array substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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- 239000000758 substrate Substances 0.000 title claims abstract description 47
- 239000002184 metal Substances 0.000 claims abstract description 61
- 229910052751 metal Inorganic materials 0.000 claims abstract description 61
- 238000002161 passivation Methods 0.000 claims abstract description 39
- 239000004065 semiconductor Substances 0.000 claims abstract description 27
- 239000000463 material Substances 0.000 claims description 3
- 239000003990 capacitor Substances 0.000 abstract description 16
- 230000000694 effects Effects 0.000 abstract description 9
- 230000007423 decrease Effects 0.000 abstract description 7
- 239000010409 thin film Substances 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 230000005611 electricity Effects 0.000 description 2
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 2
- 239000010931 gold Substances 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000005034 decoration Methods 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
- H10D86/40—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs
- H10D86/60—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates characterised by multiple TFTs wherein the TFTs are in active matrices
Landscapes
- Thin Film Transistor (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
Abstract
The present invention provides a kind of tft array substrate, including underlay substrate, the gate metal layer being arranged on underlay substrate, the gate insulating layer for covering gate metal layer, the semiconductor layer being arranged on gate insulating layer, and the source electrode and drain electrode being electrically connected with semiconductor layer；Wherein, the drain electrode is mutually indepedent along the projection for projecting the thickness direction with the gate metal layer along the passivation layer of the thickness direction of the passivation layer.The utility model has the advantages that being arranged to there is no corresponding region in the thickness direction and gate metal layer of passivation layer by that will drain, increase the spacing between drain electrode and gate metal layer, to reduce the capacitor for the capacitor that drain electrode is formed with gate metal layer, prevent that feedthrough effect causes panel luminance to decline.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of tft array substrates.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, TFT) is the primary drive part of current panel display board,
It is directly related to the developing direction of high performance flat display device.
Grid, source electrode and drain electrode made of metal layer, source electrode and grid have been generally comprised in thin-film transistor array base-plate
And the dielectric layer that a layer insulating is used as can be set between drain electrode and grid, to make source electrode and grid and drain electrode and grid
Capacitor is formed between pole.
However, the capacitor between drain electrode and grid is also easy to produce Feed through (feedthrough effect) when larger, so as to cause
Panel luminance decline, influences panel image quality.
Summary of the invention
The present invention provides a kind of tft array substrate, to solve to be also easy to produce feedthrough when the capacitor between drain electrode and grid is larger
The technical issues of effect.
To solve the above problems, technical solution provided by the invention is as follows:
A kind of tft array substrate, comprising:
Underlay substrate；
Gate metal layer on the underlay substrate is set；
Cover the gate insulating layer of the gate metal layer；
Semiconductor layer on the gate insulating layer and the source electrode being electrically connected with the semiconductor layer and leakage are set
Pole；
Cover the passivation layer of the semiconductor layer, the source electrode and the drain electrode；And
The anode metal layer for being arranged on the passivation layer and being electrically connected with the drain electrode；
Wherein, the projection of thickness direction of the drain electrode along the passivation layer and the gate metal layer are along the passivation layer
Thickness direction projection it is mutually indepedent.
Further, the source electrode and the drain electrode are arranged on the semiconductor layer and touch with the semiconductor layer
It connects.
Further, the source electrode and the drain electrode are made with material.
Further, the first conductive layer, first conductive layer and grid gold are additionally provided on the underlay substrate
Belong to layer to be electrically connected, also, the projection of thickness direction of first conductive layer along the passivation layer drains with described along described
The projection section of the thickness direction of passivation layer is overlapped.
Further, the gate insulating layer is arranged on first conductive layer.
Further, first conductive layer is made of transparent conductive metal.
Further, the drain electrode is the part that the semiconductor layer extends to the direction far from the source electrode；Or it is described
Drain electrode is the part that the anode metal layer extends along the thickness direction of the passivation layer and is in contact with the semiconductor layer.
Further, the second conductive layer, second conductive layer and grid gold are additionally provided on the underlay substrate
Belong to layer to be electrically connected, also, the projection of thickness direction of second conductive layer along the passivation layer drains with described along described
The projection section of the thickness direction of passivation layer is overlapped.
Further, the gate insulating layer is arranged on the second conductive layer.
Further, second conductive layer is made of transparent conductive metal.
The invention has the benefit that being arranged to not have in the thickness direction of passivation layer with gate metal layer by that will drain
Corresponding region increases the spacing between drain electrode and gate metal layer, to reduce the capacitor of drain electrode and gate metal layer formation
Capacitor, prevent that feedthrough effect causes panel luminance to decline, at the same by setting led with what gate metal layer was electrically connected
Electric layer reduces the conducting resistance between drain electrode and gate metal layer, and thin film transistor (TFT) is made to keep working normally.
Detailed description of the invention
It, below will be to embodiment or the prior art in order to illustrate more clearly of embodiment or technical solution in the prior art
Attached drawing needed in description is briefly described, it should be apparent that, the accompanying drawings in the following description is only some of invention
Embodiment for those of ordinary skill in the art without creative efforts, can also be attached according to these
Figure obtains other attached drawings.
Fig. 1 is the structural schematic diagram of tft array substrate in the embodiment of the present invention one；
Fig. 2 is the structural schematic diagram of tft array substrate in the embodiment of the present invention two；
Fig. 3 is the structural schematic diagram of tft array substrate in the embodiment of the present invention three；
Fig. 4 is the structural schematic diagram of tft array substrate in the embodiment of the present invention four.
Appended drawing reference:
10, underlay substrate；20, gate metal layer；30, gate insulating layer；40, semiconductor layer；51, source electrode；52, it drains；
61, the first conductive layer；62, the second conductive layer；70, passivation layer；80, anode metal layer.
Specific embodiment
The explanation of following embodiment is referred to the additional illustration, the particular implementation that can be used to implement to illustrate the present invention
Example.The direction term that the present invention is previously mentioned, such as [on], [under], [preceding], [rear], [left side], [right side], [interior], [outer], [side]
Deng being only the direction with reference to annexed drawings.Therefore, the direction term used be to illustrate and understand the present invention, rather than to
The limitation present invention.The similar unit of structure is with being given the same reference numerals in the figure.
The present invention is directed in existing thin-film transistor array base-plate, since the capacitor between drain electrode and grid is larger, easily
It generates Feed through (feedthrough effect), so as to cause panel luminance decline, influences panel image quality.The present invention can solve
State problem.
Embodiment one:
A kind of tft array substrate, as shown in Figure 1, the tft array substrate includes underlay substrate 10, is arranged in the lining
Gate metal layer 20, the gate insulating layer 30 of the covering gate metal layer 20 on substrate 10, setting are exhausted in the grid
Semiconductor layer 40 in edge layer 30, and, the source electrode 51 being electrically connected with the semiconductor layer 40 and drain electrode 52.
Wherein, the tft array substrate further includes covering the semiconductor layer 40, the source electrode 51 and the drain electrode 52
Passivation layer 70, and, the anode metal layer 80 for being arranged on the passivation layer 70 and being electrically connected with the drain electrode 52.
Wherein, the projection of 52 thickness direction along the passivation layer 70 of drain electrode is with the gate metal layer 20 along described
The projection of the thickness direction of passivation layer 70 is mutually indepedent.
For those skilled in the art, it is to be understood that when forming capacitor between drain electrode 52 and gate metal layer 20,
Drain electrode 52 and two pole plates of the gate metal layer 20 as capacitor, the area of drain electrode 52 and the corresponding position of gate metal layer 20
Spacing between bigger, drain electrode 52 and gate metal layer 20 is smaller, the electricity for the capacitor that drain electrode 52 is formed with gate metal layer 20
Rong Yue great.52 it is arranged to thickness direction and gate metal layer 20 in passivation layer 70 without corresponding region by that will drain, increases
Spacing between drain electrode 52 and gate metal layer 20, to reduce the electricity for the capacitor that drain electrode 52 is formed with gate metal layer 20
Hold, prevents that Feed through (feedthrough effect) causes panel luminance to decline.
Specifically, the source electrode 51 and it is described drain electrode 52 be arranged on the semiconductor layer 40 and with the semiconductor layer
40 touch.
Further, the source electrode 51 and the drain electrode 52 are made with material with technique.
Embodiment two:
A kind of tft array substrate, as shown in Fig. 2, it the difference is that only the underlay substrate 10 with embodiment one
On be additionally provided with the first conductive layer 61.
Specifically, first conductive layer 61 is electrically connected with the gate metal layer 20, also, first conductive layer
61 projection and the Projection Division of 52 thickness direction along the passivation layer 70 that drains along the thickness direction of the passivation layer 70
Divide and is overlapped.
It is electrically connected using the second conductive layer 62 with gate metal layer 20, while preventing feedthrough effect, reduces leakage
Conducting resistance between pole 52 and gate metal layer 20.
Further, the gate insulating layer 30 be arranged on first conductive layer 61 and with first conductive layer 61
It touches.
Further, first conductive layer 61 is made of transparent conductive metal.
Embodiment three:
A kind of tft array substrate, as shown in figure 3, the tft array substrate includes underlay substrate 10, is arranged in the lining
Gate metal layer 20, the gate insulating layer 30 of the covering gate metal layer 20 on substrate 10, setting are exhausted in the grid
Semiconductor layer 40 in edge layer 30, and, the source electrode 51 being electrically connected with the semiconductor layer 40 and drain electrode 52.
Wherein, the tft array substrate further includes covering the semiconductor layer 40, the source electrode 51 and the drain electrode 52
Passivation layer 70 and the anode metal layer 80 for being arranged on the passivation layer 70 and being electrically connected with the drain electrode 52, the drain electrode
52 parts extended for the semiconductor layer 40 to the direction far from the source electrode 51.
Specifically, the projection of 52 thickness direction along the passivation layer 70 that drains and the gate metal layer 20 are along institute
The projection for stating the thickness direction of passivation layer 70 is mutually indepedent.
Drain electrode 52 is formed by extending semiconductor layer 40, to increase the aperture opening ratio of penetrating region, while by that will drain 52
It is arranged to thickness direction and gate metal layer 20 in passivation layer 70 without corresponding region, increases drain electrode 52 and gate metal layer 20
Between spacing, thus reduce drain electrode 52 with gate metal layer 20 formed capacitor capacitor, prevent that feedthrough effect is led
Cause panel luminance decline.
Further, be additionally provided with the second conductive layer 62 on the underlay substrate 10, second conductive layer 62 with it is described
Gate metal layer 20 is electrically connected, also, projection and institute of second conductive layer 62 along the thickness direction of the passivation layer 70
The projection section that drain electrode 52 is stated along the thickness direction of the passivation layer 70 is overlapped.
Further, the gate insulating layer 30 be arranged on second conductive layer 62 and with second conductive layer 62
It touches.
Further, second conductive layer 62 is made of transparent conductive metal.
Example IV:
A kind of tft array substrate, as shown in figure 4, the shape that the difference is that only the drain electrode 52 of itself and embodiment three
At mode difference.
Specifically, it is described drain electrode 52 for the anode metal layer 80 extend along the thickness direction of the passivation layer 70 and with
The part that the semiconductor layer 40 is in contact.
The invention has the benefit that 52 being arranged to thickness direction and gate metal layer in passivation layer 70 by that will drain
20 do not have corresponding region, increase the spacing between drain electrode 52 and gate metal layer 20, to reduce drain electrode 52 and gate metal layer
The capacitor of 20 capacitors formed, prevents that feedthrough effect causes panel luminance to decline, while passing through setting and gate metal
The conductive layer that layer 20 is electrically connected reduces the conducting resistance between drain electrode 52 and gate metal layer 20, keeps thin film transistor (TFT) just
Often work.
In conclusion although the present invention has been disclosed above in the preferred embodiment, but above preferred embodiment is not to limit
The system present invention, those skilled in the art can make various changes and profit without departing from the spirit and scope of the present invention
Decorations, therefore protection scope of the present invention subjects to the scope of the claims.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811564889.0A CN109671723A (en) | 2018-12-20 | 2018-12-20 | A kind of tft array substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811564889.0A CN109671723A (en) | 2018-12-20 | 2018-12-20 | A kind of tft array substrate |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109671723A true CN109671723A (en) | 2019-04-23 |
Family
ID=66144051
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201811564889.0A Pending CN109671723A (en) | 2018-12-20 | 2018-12-20 | A kind of tft array substrate |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109671723A (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1652004A (en) * | 2005-03-22 | 2005-08-10 | 广辉电子股份有限公司 | TFT array substrate of liquid crystal display, liquid crystal display panel and manufacturing method thereof |
| CN1702530A (en) * | 2004-05-27 | 2005-11-30 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN101105615A (en) * | 2006-06-29 | 2008-01-16 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN203465496U (en) * | 2013-09-27 | 2014-03-05 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal display device |
| CN104269414A (en) * | 2014-09-25 | 2015-01-07 | 合肥京东方光电科技有限公司 | Array substrate, array substrate manufacturing method and display device |
| CN104810382A (en) * | 2015-05-07 | 2015-07-29 | 深圳市华星光电技术有限公司 | AMOLED (active matrix/organic light emitting diode) backboard production method and AMOLED backboard structure |
| CN107634034A (en) * | 2017-09-15 | 2018-01-26 | 惠科股份有限公司 | Method for manufacturing active array switch |
-
2018
- 2018-12-20 CN CN201811564889.0A patent/CN109671723A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1702530A (en) * | 2004-05-27 | 2005-11-30 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and fabricating method thereof |
| CN1652004A (en) * | 2005-03-22 | 2005-08-10 | 广辉电子股份有限公司 | TFT array substrate of liquid crystal display, liquid crystal display panel and manufacturing method thereof |
| CN101105615A (en) * | 2006-06-29 | 2008-01-16 | Lg.菲利浦Lcd株式会社 | Liquid crystal display device and method for fabricating the same |
| CN203465496U (en) * | 2013-09-27 | 2014-03-05 | 京东方科技集团股份有限公司 | Array substrate and liquid crystal display device |
| CN104269414A (en) * | 2014-09-25 | 2015-01-07 | 合肥京东方光电科技有限公司 | Array substrate, array substrate manufacturing method and display device |
| CN104810382A (en) * | 2015-05-07 | 2015-07-29 | 深圳市华星光电技术有限公司 | AMOLED (active matrix/organic light emitting diode) backboard production method and AMOLED backboard structure |
| CN107634034A (en) * | 2017-09-15 | 2018-01-26 | 惠科股份有限公司 | Method for manufacturing active array switch |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20190423 |