CN101566768A - Pixel structure for thin film transistor liquid crystal display and manufacturing method thereof - Google Patents

Abstract

The invention provides a pixel structure of a thin film transistor liquid crystal display, in which a pixel electrode and a transparent conductive layer are formed on a substrate; a drain electrode is formed on the pixel electrode, a data scanning line and a source electrode are formed on the transparent conductive layer, and The source electrode is connected to the data scanning line, and the drain electrode is connected to the pixel electrode; an ohmic contact layer and a semiconductor layer are sequentially formed on the source electrode and the drain electrode, and the parts of the ohmic contact layer that are in contact with the source electrode and the drain electrode are not connected to each other; the source electrode A passivation layer is formed on the part of the drain electrode not covered by the ohmic contact layer, the part of the ohmic contact layer not covered by the semiconductor layer, and the semiconductor layer; a gate scanning line and a gate electrode are sequentially formed on the passivation layer, and gate insulating layer. The invention also provides a method for manufacturing a pixel structure of a thin film transistor liquid crystal display, the pixel structure and the method can save manufacturing process and increase storage capacitance.

Description

Thin film transistor liquid crystal display pixel structure and manufacturing method thereof

technical field

The invention relates to a thin film transistor (TFT) liquid crystal display (LCD) array substrate, in particular to a thin film transistor liquid crystal display pixel structure and a manufacturing method thereof.

Background technique

At present, the world has entered the era of information revolution, and display technology and display devices occupy a very important position in the development of information technology. Among them, due to the advantages of light weight, thin thickness, small size, no radiation, and no flicker, flat panel display has become the development direction of display technology. Among flat panel display technologies, TFT LCD has dominated the flat panel display market due to its low power consumption, relatively low manufacturing cost, and no radiation.

TFT LCD devices are formed by combining array glass substrates and color film glass substrates. Figure 1 to Figure 1b show the top view of a single pixel of the current mainstream amorphous silicon TFT structure, and the cross-sectional schematic diagrams of A-A and B-B parts. As shown in Figures 1 to 1b, the amorphous silicon TFT structure adopts a bottom gate structure with a back channel etched, and the array structure includes: a set of gate scan lines 1 and a set of data scan lines 5 perpendicular thereto. Adjacent gate scan lines 1 and data scan lines 5 define a pixel area. Each pixel includes a TFT switching device, a pixel electrode 10 and a part of the common electrode lead 11, and the TFT switching device is composed of a gate electrode 2, an ohmic contact layer 14, a semiconductor layer 3, a gate electrode insulating layer 4, and a source electrode 6 and the drain electrode 7; the gate electrode 2, the ohmic contact layer 14, the semiconductor layer 3, the gate electrode insulating layer 4, and the source electrode 6 and the drain electrode 7 are covered with a passivation layer 8, and, above the drain electrode 7 A passivation layer via hole 9 is formed; the pixel electrode 10 is connected to the drain electrode 7 of the TFT through the passivation layer via hole 9; a part of the pixel electrode 10 forms a storage capacitor (not shown in the figure) together with the gate scanning line 1 . In order to further reduce the light leakage between the pixels after the box is aligned, light blocking strips 12 are formed on both sides of the pixels parallel to the data scanning lines 5 .

The above-mentioned pixel structures shown in FIG. 1 to FIG. 1 b are generally manufactured using a 5-Mask process. The 5-Mask process is currently a typical process technology for manufacturing TFTs. Its main process steps are shown in Figure 2, including:

Steps 201-202: forming a gate electrode and its leads, forming a gate electrode insulating layer, an ohmic contact layer and a semiconductor layer;

Steps 203-205: forming source electrodes, drain electrodes and data scanning lines; forming a passivation layer and pixel electrodes.

Each step shown in Figure 2 includes a thin film deposition process, and patterning processes such as exposure and etching. In addition to the 5-Mask technology shown in FIG. 2 , in the prior art, by changing the Mask design and process flow, other Mask process technologies can also be produced, which will not be repeated here.

The pixel structure shown in FIGS. (not shown in ) is small, and thus the jump voltage is relatively large, which will affect the image display quality.

Contents of the invention

In view of this, the main purpose of the present invention is to provide a thin film transistor liquid crystal display pixel structure and a manufacturing method thereof, which can improve image display quality while simplifying the process.

In order to achieve the above object, technical solution of the present invention is achieved in that way:

The invention provides a pixel structure of a thin film transistor liquid crystal display, comprising a substrate; a pixel electrode and a transparent conductive layer are formed on the substrate;

A drain electrode is formed on the pixel electrode, a data scanning line and a source electrode are formed on the transparent conductive layer, and the source electrode is connected to the data scanning line, and the drain electrode is connected to the pixel electrode ;

An ohmic contact layer and a semiconductor layer are sequentially formed on the source electrode and the drain electrode, and the portions of the ohmic contact layer respectively in contact with the source electrode and the drain electrode are not connected to each other;

A passivation layer is formed on the source electrode, the part of the drain electrode not covered by the ohmic contact layer, the part of the ohmic contact layer not covered by the semiconductor layer, and the semiconductor layer;

A gate scanning line and a gate electrode are formed on the passivation layer;

A gate electrode insulating layer is formed on the gate scanning line and the gate electrode.

Wherein, the ohmic contact layer between the source electrode and the drain electrode includes a semiconductor doped region, and the semiconductor doped region makes the parts of the ohmic contact layer respectively connected to the source electrode and the drain electrode not connected to each other.

The pixel structure also includes:

A light-shielding strip and a common electrode lead are also formed on the passivation layer and under the gate electrode insulating layer, the light-shielding strip is parallel to the data scanning line, and the common electrode lead is parallel to the gate scanning line. Wire.

The gate scanning lines, data scanning lines, source electrodes, drain electrodes, common electrode leads or light-shielding strips are single layers composed of one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum and aluminum nickel, or the above metal materials Any combination of single or composite layers.

The pixel electrode and the transparent conductive layer are part of the same material, and the pixel electrode and the transparent conductive layer are not connected to each other.

The present invention simultaneously provides a method for manufacturing a pixel structure of a thin film transistor liquid crystal display, the method comprising:

A. Deposit a pixel electrode layer and a metal thin film sequentially on the substrate, form a pixel electrode, a source electrode, a drain electrode and a data scanning line on the substrate through a patterning process, and connect the source electrode to the data scanning line, the The drain electrode is connected to the pixel electrode;

B. Deposit the ohmic contact layer film on the substrate that completed step A, and make the parts of the ohmic contact layer film that are connected to the source electrode and the drain electrode not connected to each other through a certain process. After that, deposit the semiconductor layer film and pass the patterning process on the place. Forming an ohmic contact layer and a semiconductor layer on the source electrode and the drain electrode;

C. Depositing a passivation layer thin film on the substrate having completed step B to form a passivation layer;

D. Depositing a metal thin film on the substrate that has completed step C, and forming gate scanning lines and gate electrodes through a patterning process;

E. Forming a gate electrode insulating layer on the substrate after step D has been completed.

Wherein, the part where the ohmic contact layer film is respectively connected to the source electrode and the drain electrode through a certain process is not connected to each other is specifically:

First, coat a layer of photoresist on the deposited ohmic contact layer film, expose the ohmic contact layer film corresponding to the semiconductor doped region through an exposure and development process, and use a semiconductor doping process for the exposed ohmic contact layer film A semiconductor doped region is formed, and then the photoresist on the ohmic contact layer film is stripped off.

The parts of the ohmic contact layer thin film connected to the source electrode and the drain electrode are not connected to each other through a certain process, specifically:

First coat a layer of photoresist on the deposited ohmic contact layer film, expose the ohmic contact layer film corresponding to the semiconductor doped region through an exposure and development process, and use a patterning process to etch the exposed ohmic contact layer film , after that, peel off the photoresist on the ohmic contact layer film.

In step B, the ohmic contact layer and the semiconductor layer are formed simultaneously in a patterning process using the same mask plate after the peninsula doped region is formed.

Step A is specifically:

A pixel electrode layer and a metal thin film are sequentially deposited on the substrate, a layer of photoresist is coated on the metal thin film, and the data scanning line, source electrode, drain electrode and pixel area are fully exposed with a mask;

Perform ashing treatment on the pixel area, remove the photoresist on the pixel area, etch off the metal thin film layer in the pixel area to form a pixel electrode.

In step D, while forming the gate scanning lines and the gate electrodes through the patterning process, the common electrode leads and the light-shielding strips are also formed.

The forming of the gate electrode insulating layer is specifically:

Depositing a gate electrode insulating layer, and forming via holes around the substrate through a patterning process to expose signal leads around the substrate; or,

A gate electrode insulating layer is formed using a mask growth process.

In the thin film transistor liquid crystal display pixel structure and its manufacturing method provided by the present invention, the data scanning line, source electrode, drain electrode and pixel electrode are formed in one exposure process, instead of the data scanning line, source electrode and The electrode and the drain electrode are formed in one exposure process, and the pixel electrode is formed in another exposure process; the ohmic contact layer and the semiconductor layer are formed in one etching process instead of two etching processes respectively, so , which greatly simplifies the process. Moreover, since the data scanning line, source electrode, drain electrode and pixel electrode are formed in one exposure process, the gate insulating layer and the passivation layer via hole are canceled, thus, only the pixel electrode and the gate scanning line exist. The passivation layer reduces the distance between the pixel electrode and the gate scanning line, thereby increasing the storage capacitance and reducing the jump voltage, thereby effectively improving and improving the display quality of the picture.

Description of drawings

1 is a top view of a single pixel structure on a TFT LCD array substrate in the prior art;

Figure 1a is a schematic cross-sectional view of part A-A of Figure 1;

Figure 1b is a schematic cross-sectional view of the B-B part of Figure 1;

Fig. 2 is the schematic diagram of prior art 5-Mask technological process;

3 is a top view of a single pixel structure on a TFT LCD array substrate in the present invention;

Fig. 3 a is a schematic cross-sectional view of part C-C of Fig. 3;

Fig. 3b is another schematic cross-sectional view of part C-C of Fig. 3;

Figure 3c is a schematic cross-sectional view of the D-D part of Figure 3;

Fig. 4 is the schematic flow chart of TFT LCD pixel structure manufacturing method of the present invention;

Fig. 5a is a top view of the pixel structure after the patterning process of the pixel electrode layer of the manufacturing method shown in Fig. 4 of the present invention;

Figure 5b is a schematic cross-sectional view of the E-E part of the present invention after full exposure;

Figure 5c is a schematic cross-sectional view of the E-E part of the present invention after ashing treatment;

Figure 5d is a schematic cross-sectional view of the E-E part after the metal thin film layer is removed in the present invention;

Fig. 5e is a schematic cross-sectional view of part C-C of the pixel structure after the pixel electrode layer of the manufacturing method shown in Fig. 4 of the present invention undergoes a patterning process;

FIG. 6a is a top view of the pixel structure after forming an ohmic contact layer and a semiconductor layer through a patterning process in the manufacturing method shown in FIG. 4 of the present invention;

6b is a schematic cross-sectional view of the C-C part of the pixel structure after forming an ohmic contact layer and a semiconductor layer in the manufacturing method shown in FIG. 4 of the present invention through a patterning process;

Fig. 6c is a schematic cross-sectional view of the C-C part of the manufacturing method shown in Fig. 4 of the present invention after the semiconductor doping process forms the semiconductor doping region;

Fig. 6d is a schematic cross-sectional view of the C-C part after the semiconductor doped region is etched away by the manufacturing method shown in Fig. 4 of the present invention;

7 is a schematic cross-sectional view of part C-C after the passivation layer is deposited by the manufacturing method shown in FIG. 4 of the present invention;

FIG. 8 is a schematic cross-sectional view of part C-C of the pixel structure after the gate metal thin film of the manufacturing method shown in FIG. 4 has undergone a patterning process according to the present invention.

Reference signs: 1. Gate scanning line; 2. Gate electrode; 3. Semiconductor layer; 4. Gate insulating layer; 5. Data scanning line; 6. Source electrode; 7. Drain electrode; 8. Passivation layer; 9. Passivation layer via hole; 10. Pixel electrode; 11. Common electrode lead; 12. Light blocking strip; 14. Ohmic contact layer; 15. Semiconductor doped area; 16. Photoresist; 17. Transparent conductive layer; 18. Metal film layer.

Detailed ways

The basic idea of the present invention is to form the data scanning line, source electrode, drain electrode and pixel electrode in one exposure process, and form the semiconductor layer and ohmic contact layer in one etching process, while simplifying the process, increasing the large storage capacitor.

Further, when the source electrode and the drain electrode are respectively connected to the ohmic contact layer, a semiconductor doping process can be used for the ohmic contact layer between the source electrode and the drain electrode, so that the ohmic contact layers are not connected to each other, so as to ensure this Invention said pixel structure works normally.

Hereinafter, the implementation of the pixel structure and manufacturing method of the thin film transistor liquid crystal display of the present invention will be described in detail through specific embodiments in conjunction with the accompanying drawings.

Fig. 3 is a top view of a single pixel structure on a TFTLCD array substrate of the present invention; Fig. 3a and Fig. 3b are respectively a schematic cross-sectional view of part C-C and a schematic cross-sectional view of part D-D of Fig. 3 . As shown in Fig. 3-Fig. 3b, the array substrate of the TFT LCD has a group of gate scanning lines 1 and common electrode leads 11 parallel thereto, and a group of data scanning lines 5 and light blocking strips 12 perpendicular thereto; Each adjacent gate scan line 1 and data scan line 5 cross to define a pixel area; a pixel area includes a TFT switching device, pixel electrode 10 and common electrode lead 11, wherein the TFT switching device is composed of a gate electrode 2 , a semiconductor layer 3, a gate insulating layer 4, an ohmic contact layer 14, and a source electrode 6 and a drain electrode 7.

As shown in Figures 3-3b, the pixel structure provided by the present invention is specifically:

Above the glass substrate is a pixel electrode 10 and a transparent conductive layer 17, above the pixel electrode 10 is a drain electrode 7, above the transparent conductive layer 17 is a data scanning line 5 and a source electrode 6, and the source electrode 6 and The data scanning line 5 is connected, the drain electrode 7 is connected to the pixel electrode 10 , and the pixel electrode 10 is not connected to the transparent conductive layer 17 . Moreover, due to the relationship of the manufacturing method, for example, when using the manufacturing method shown in FIG. 4 of the present invention, the transparent conductive layer 17 that may be included under the data scanning line 5 and the source electrode 6 is the pixel electrode layer where the pixel electrode 10 is located. However, The part under the data scanning line 5 and the source electrode 6 is not connected to the drain electrode 7 and the pixel electrode 10, only the part of the pixel electrode layer connected to the drain electrode 7 is the pixel electrode 10, that is, the transparent The conductive layer 17 is not connected to the pixel electrode 10 . Among them, the pixel electrode 10 , the source electrode 6 , the drain electrode 7 and the data scanning line 5 are parts of different materials produced in the same patterning process such as coating, mask photolithography and etching. The material of the pixel electrode 10 and the transparent conductive layer 17 is generally indium tin oxide, indium zinc oxide or aluminum zinc oxide. The data scanning line 5, the source electrode 6, and the drain electrode 7 are a single layer composed of one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum, and aluminum nickel, or a single layer or a composite layer composed of any combination of the above metal materials .

On the source electrode 6 and the drain electrode 7 are the ohmic contact layer 14 and the semiconductor layer 3 in sequence, and the parts of the ohmic contact layer 14 connected to the source electrode 6 and the drain electrode 7 are not connected to each other, wherein the ohmic contact layer 14 The method of disconnecting each other may be: forming a semiconductor doped region 15 as shown in FIG. The semiconductor doped region 15 shown in FIG. 3a is etched away by a patterning process to form the cross-sectional view of the pixel structure shown in FIG. 3b , which can also achieve the purpose of disconnecting the ohmic contact layers. Wherein, the ohmic contact layer 14 and the semiconductor layer 3 are parts of different materials that are fabricated in photolithography and etching processes using the same mask. Wherein, which material to use belongs to the known technology, and will not be repeated here.

The parts of the source electrode 6 and the drain electrode 7 not covered by the ohmic contact layer 14 , the parts of the ohmic contact layer 14 not covered by the semiconductor layer 3 , and the semiconductor layer 3 are covered with a passivation layer 8 . Wherein, the material of the passivation layer 8 is generally: silicon nitride, silicon dioxide or aluminum oxide.

The passivation layer 8 includes gate scanning lines 1 , gate electrodes 2 , light-shielding strips 12 and common electrode leads 11 , and the light-shielding strips are parallel to the data scanning lines 5 . The gate electrode insulating layer 4 covers the uncovered part of the passivation layer 8 , the gate scanning line 1 , the gate electrode 2 , the light shielding strip 12 , and the common electrode lead 11 . Wherein, the gate scanning line 1, the common electrode lead 11 and the light-shielding strip 12 are parts of the same material produced in the same patterning process such as coating, mask photolithography and etching, which can be aluminum, chromium, tungsten, A single layer composed of one of tantalum, titanium, molybdenum and aluminum nickel, or a single layer or composite layer composed of any combination of the above metal materials.

In the prior art, as shown in Figures 1 to 1b, the semiconductor active layer 14 is below the source electrode 6 and the drain electrode 7, and the pixel electrode 10 is connected to the drain electrode 7 through the passivation layer via hole 9; while in the present invention In the pixel structure described above, as shown in Figures 3 to 3b, the pixel electrode 10, the source electrode 6 and the drain electrode 7 are completed in the same patterning process such as coating, mask photolithography, and etching, and the passivation layer via hole is cancelled. 9, and adopt the top gate structure, which saves one-step exposure process.

The TFT LCD pixel structure shown in Figures 3 to 3b is only a typical structure of the present invention. In practical applications, pixel structures of other shapes and patterns can also be used. As long as the source electrode is connected to the data scanning line, the drain electrode Connected to the pixel electrode, the ohmic contact layer and the semiconductor layer are located above the data scanning line; and if the ohmic contact layer is connected to the source electrode and the drain electrode, the part of the ohmic contact layer connected to the source electrode and the part connected to the drain electrode are not connected to each other. Can.

Fig. 4 is a method for manufacturing a pixel structure of a thin film transistor liquid crystal display according to the present invention, and referring to Fig. 3 to Fig. 3b at the same time, the method includes:

Step 401: Deposit the pixel electrode layer and metal thin film sequentially on the substrate, and form the pixel electrode 10, the source electrode 6, the drain electrode 7 and the data scanning line 5 on the substrate through patterning processes such as exposure process and etching process.

至1000

之间；然后，使用磁控溅射方法在像素电极层上再沉积一层厚度在1000

到7000

金属薄膜；之后，在所述金属薄膜之上涂布一层光刻胶16，用掩膜板全曝光出数据扫描线5、源电极6、漏电极7和像素区域，所述像素区域即为图5b中像素电极10所对应的部分，像素电极10之上覆盖有与数据扫描线5材料相同的金属薄膜层18，所述数据扫描线5、源电极6、漏电极7和像素区域均为双层金属结构，位于数据扫描线5以及源电极6之下的像素电极层为透明导电层17，而像素区域与漏电极7相连接，完成全曝光之后的数据扫描线5以及所述金属薄膜层18之上覆盖有完整的光刻胶，如图5b所示。之后，进行灰化处理，去掉覆盖在金属薄膜层18上的光刻胶16，此时的E-E部分横截面示意图如图5c所示。最后，用物理或化学刻蚀方法去掉像素区域双层金属上的第一层金属，也即像素电极10之上的金属薄膜层18，形成像素电极10的图形，此时的E-E部分横截面示意图如图5d所示。Use a certain metal deposition method, such as the magnetron sputtering method, to deposit a layer of pixel electrode layer on the glass substrate, using a transparent electrode mask with a thickness of 100

to 1000

Between; Then, use the magnetron sputtering method to deposit a layer thickness of 1000 on the pixel electrode layer

to 7000

Metal thin film; Afterwards, coat one deck photoresist 16 on described metal thin film, go out data scan line 5, source electrode 6, drain electrode 7 and pixel region with mask plate full exposure, described pixel region is In the part corresponding to the pixel electrode 10 in Fig. 5b, the metal film layer 18 of the same material as the data scanning line 5 is covered on the pixel electrode 10, and the data scanning line 5, the source electrode 6, the drain electrode 7 and the pixel area are all Double-layer metal structure, the pixel electrode layer located under the data scanning line 5 and the source electrode 6 is a transparent conductive layer 17, and the pixel area is connected to the drain electrode 7, the data scanning line 5 and the metal thin film after the full exposure are completed Layer 18 is covered with a complete photoresist, as shown in Figure 5b. Afterwards, an ashing process is performed to remove the photoresist 16 covering the metal thin film layer 18, and the cross-sectional schematic diagram of the EE part at this time is shown in FIG. 5c. Finally, the first layer of metal on the double-layer metal in the pixel area is removed by physical or chemical etching, that is, the metal thin film layer 18 on the pixel electrode 10, to form the pattern of the pixel electrode 10, and the cross-sectional schematic diagram of the EE part at this time As shown in Figure 5d.

The top view of the pixel structure after step 401 and the cross-sectional schematic diagram of part C-C are shown in Figures 5a and 5e. Combining with Figure 5d, it can be known that the source electrode 6 is connected to the data line 5, and the source electrode 6 and the drain electrode 7 contain a pixel electrode layer below, and The pixel electrode layer contained under the data scanning line 5 and the source electrode 6 is the transparent conductive layer 17 described in the present invention. The transparent conductive layer 17 is not connected to the drain electrode 7 and is not included in the pixel electrode 10. , only the part of the pixel electrode layer connected to the drain electrode 7 is called the pixel electrode 10 .

The commonly used material for the pixel electrode 10 is indium tin oxide (ITO) or indium zinc oxide (IZO); the metal material used for the metal film can usually be molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper and other metals, a combination structure of the above-mentioned several metal material films can also be used.

Wherein, specifically how to use the magnetron sputtering method for the deposition, how to perform the exposure, and the use of the etching method are all known technologies, and will not be repeated here.

Step 402: Deposit an ohmic contact layer thin film on the substrate completed in step 401, form a semiconductor doped region 15 through a semiconductor doping process, and then deposit a semiconductor layer thin film again, and through patterning processes such as an exposure process and an etching process, in the source Ohmic contact layer 14 and semiconductor layer 3 are formed on electrode 6 and drain electrode 7 .

到2000

的N+a-Si薄膜，在所述N+a-Si薄膜上涂布一层光刻胶16，通过曝光显影工艺，使得欧姆接触层薄膜中的半导体掺杂区域15暴露出来。在半导体掺杂区域15处进行半导体掺杂工艺，使得半导体掺杂区域15中掺杂有P型硅，此时，C-C部分横截面示意图如图6c所示，之后，剥离掉欧姆接触层薄膜上的光刻胶16。利用一定的金属沉积方法，例如化学汽相沉积法，在阵列基板上沉积500

到4000

的非晶硅薄膜，用半导体层3的掩膜版进行曝光后对非晶硅进行干法刻蚀，同时形成欧姆接触层14和半导体层3，欧姆接触层14和半导体层3为使用同一掩膜板在光刻和刻蚀等构图工艺中完成制作的不同材料部分。Using a certain deposition method, such as chemical vapor deposition, deposit 500 on the array substrate

to 2000

A layer of photoresist 16 is coated on the N+a-Si film, and the semiconductor doped region 15 in the ohmic contact layer film is exposed through an exposure and development process. The semiconductor doping process is carried out at the semiconductor doped region 15, so that P-type silicon is doped in the semiconductor doped region 15. At this time, the cross-sectional schematic diagram of the CC part is shown in FIG. photoresist16. Using a certain metal deposition method, such as chemical vapor deposition, deposit 500 on the array substrate

to 4000

The amorphous silicon thin film is dry-etched after the mask plate of the semiconductor layer 3 is used to form the ohmic contact layer 14 and the semiconductor layer 3. The ohmic contact layer 14 and the semiconductor layer 3 use the same mask The different material parts of the film plate are completed in the patterning process such as photolithography and etching.

Wherein, the ohmic contact layer 14 partially covered on the source electrode 6 and the drain electrode 7 is N-type amorphous silicon, and the semiconductor doped region 15 of the ohmic contact layer 14 between the source electrode 6 and the drain electrode 7 is P-type amorphous silicon. silicon. The top view of the pixel structure after this step is shown in FIG. 6 a , and the cross-sectional schematic diagram of part C-C is shown in FIG. 6 b .

Wherein, specifically how to use the chemical vapor deposition method to perform the deposition, and how to perform the etching process and the doping process belong to known technologies, and will not be repeated here.

到6000

的钝化层。Step 403: Using a certain deposition method, such as chemical vapor deposition, continuously deposit 1000

to 6000

passivation layer.

The schematic cross-sectional view of the C-C part of the pixel structure after this step is shown in FIG. A passivation layer 8 is deposited on the part of the contact layer 14 not covered by the semiconductor layer 3 and on the semiconductor layer 3 .

The material of the passivation layer is generally silicon nitride, silicon dioxide or aluminum oxide.

Step 404: Deposit a metal thin film on the substrate completed in step 403, and form gate scan lines 1, gate electrodes 2, common electrode leads 11, and light-shielding strips 12 through patterning processes such as exposure process and etching process.

至7000的栅金属薄膜，用栅电极掩膜版通过曝光工艺和刻蚀工艺等构图工艺，在玻璃基板的一定区域上形成栅极扫描线1、栅电极2、公共电极引线11和挡光条12的图案。Use a certain metal deposition method, such as magnetron sputtering method, to prepare a layer with a thickness of 1000 on the glass substrate

to 7000 The gate metal thin film is used to form the gate scanning line 1, the gate electrode 2, the common electrode lead 11 and the light blocking strip 12 on a certain area of the glass substrate through the patterning process such as the exposure process and the etching process with the gate electrode mask. pattern.

A schematic cross-sectional view of part C-C of the pixel structure after this step is shown in FIG. 8 , and the gate electrode 2 is formed on the passivation layer 8 .

Wherein, the gate metal material used for the gate metal film may be metals such as molybdenum, aluminum, aluminum-nickel alloy, molybdenum-tungsten alloy, chromium, or copper, or a combination structure of the above gate metal material films may also be used.

Step 405: depositing a gate electrode insulating layer 4 on the substrate after step 404 is completed.

至4000

的栅电极绝缘层4。在实际应用中，沉积栅电极绝缘层4后，还需要通过曝光及刻蚀等构图工艺，在阵列基板周边形成过孔图形，将阵列基板周边信号引线暴露出来，以实现外加信号的输入。Using a certain deposition method, such as chemical vapor deposition, deposit a layer with a thickness of 1000 on the glass substrate

to 4000

The gate electrode insulating layer 4. In practical application, after depositing the insulating layer 4 of the gate electrode, it is necessary to form a pattern of via holes around the array substrate through patterning processes such as exposure and etching, so as to expose the signal leads around the array substrate to realize the input of external signals.

The material of the gate electrode insulating layer is generally silicon nitride, silicon dioxide or aluminum oxide.

Alternatively, in this step, the gate electrode insulating layer 4 may also be formed directly on the substrate after step 404 by using a mask growth process. At this time, the mask growth process used can ensure that the lead (PAD) area and the ITO shock area of the lead are not covered with the gate electrode insulating layer 4, thereby saving the process of exposing the surrounding signal leads by using a patterning process such as exposure. Specifically, how to form the gate electrode insulating layer 4 by using a mask growth process belongs to the known technology, and will not be repeated here.

Wherein, in step 402 of the pixel structure manufacturing method shown in FIG. 4 , for the semiconductor doped region 15, the semiconductor doping process may not be used, but the patterning process such as dry etching may be used to etch all the semiconductor doped regions 15 directly. The aforementioned semiconductor doped region 15 can also achieve the purpose of making the ohmic contact layers disconnected from each other. A schematic cross-sectional view of part C-C after etching away the semiconductor doped region 15 is shown in FIG. 6d. At this time, the specific operations of other steps are the same as the manufacturing method shown in FIG. 4 , and will not be repeated here.

The above descriptions are only preferred embodiments of the present invention, and are not intended to limit the protection scope of the present invention.

Claims (12)

1. A pixel structure of a thin film transistor liquid crystal display comprises a substrate; the liquid crystal display panel is characterized in that a pixel electrode and a transparent conducting layer are formed on the substrate;

a drain electrode is formed on the pixel electrode, a data scanning line and a source electrode are formed on the transparent conductive layer, the source electrode is connected with the data scanning line, and the drain electrode is connected with the pixel electrode;

an ohmic contact layer and a semiconductor layer are sequentially formed on the source electrode and the drain electrode, and the ohmic contact layer is not connected with the contact parts of the source electrode and the drain electrode respectively;

a passivation layer is formed on the source electrode, the part of the drain electrode, which is not covered by the ohmic contact layer, the part of the ohmic contact layer, which is not covered by the semiconductor layer, and the semiconductor layer;

a grid scanning line and a grid electrode are formed on the passivation layer;

a gate electrode insulating layer is formed on the gate scan line and the gate electrode.

2. The pixel structure according to claim 1, wherein the ohmic contact layer between the source electrode and the drain electrode comprises a semiconductor doping region which makes a portion of the ohmic contact layer connected to the source electrode and the drain electrode, respectively, unconnected.

3. The pixel structure of claim 2, further comprising:

light blocking strips and common electrode leads are further formed on the passivation layer and below the gate electrode insulating layer, the light blocking strips are parallel to the data scanning lines, and the common electrode leads are parallel to the gate scanning lines.

4. The pixel structure according to claim 3, wherein the gate scan line, the data scan line, the source electrode, the drain electrode, the common electrode lead, or the light blocking strip is a single layer of one of aluminum, chromium, tungsten, tantalum, titanium, molybdenum, and aluminum nickel, or a single layer or a composite layer of any combination of the above metal materials.

5. The pixel structure according to any one of claims 1 to 3, wherein the pixel electrode and the transparent conductive layer are portions of the same material, and the pixel electrode and the transparent conductive layer are not connected to each other.

6. A method for manufacturing a pixel structure of a thin film transistor liquid crystal display is characterized by comprising the following steps:

A. sequentially depositing a pixel electrode layer and a metal film on a substrate, forming a pixel electrode, a source electrode, a drain electrode and a data scanning line on the substrate through a composition process, and enabling the source electrode to be connected with the data scanning line and the drain electrode to be connected with the pixel electrode;

B. depositing an ohmic contact layer film on the substrate which is subjected to the step A, enabling the ohmic contact layer film to be not connected with the parts which are respectively connected with the source electrode and the drain electrode through a certain process, then depositing a semiconductor layer film, and forming an ohmic contact layer and a semiconductor layer on the source electrode and the drain electrode through a composition process;

C. depositing a passivation layer film on the substrate after the step B to form a passivation layer;

D. depositing a metal film on the substrate after the step C is finished, and forming a grid scanning line and a grid electrode through a composition process;

E. and forming a gate electrode insulating layer on the substrate after the step D is completed.

7. The manufacturing method according to claim 6, wherein the step of making the ohmic contact layer film and the source electrode and the drain electrode respectively connected to each other by a certain process is specifically:

firstly, coating a layer of photoresist on a deposited ohmic contact layer film, exposing the ohmic contact layer film corresponding to a semiconductor doping region through an exposure and development process, forming the semiconductor doping region on the exposed ohmic contact layer film by using a semiconductor doping process, and then stripping the photoresist on the ohmic contact layer film.

8. The manufacturing method according to claim 6, wherein the step of making the ohmic contact layer film and the source electrode and the drain electrode respectively connected to each other by a certain process is specifically:

coating a layer of photoresist on the deposited ohmic contact layer film, exposing the ohmic contact layer film corresponding to the semiconductor doping region through an exposure and development process, etching the exposed ohmic contact layer film by using a patterning process, and stripping the photoresist on the ohmic contact layer film.

9. The manufacturing method according to any one of claims 6 to 8, wherein the ohmic contact layer and the semiconductor layer are simultaneously formed in a patterning process using the same mask after the formation of the peninsula doped region in step B.

10. The manufacturing method according to any one of claims 6 to 8, wherein step A is in particular:

sequentially depositing a pixel electrode layer and a metal film on a substrate, coating a layer of photoresist on the metal film, and fully exposing a data scanning line, a source electrode, a drain electrode and a pixel area by using a mask plate;

and carrying out ashing treatment on the pixel area, removing the photoresist on the pixel area, and etching the metal film layer of the pixel area to form a pixel electrode.

11. The manufacturing method according to any one of claims 6 to 8, wherein a common electrode wiring and a light blocking bar are formed at the same time as the gate scan line and the gate electrode are formed by a patterning process in step D.

12. The manufacturing method according to any one of claims 6 to 8, wherein the forming of the gate electrode insulating layer is specifically:

depositing a gate electrode insulating layer, and forming via holes at the periphery of the substrate through a composition process to expose signal leads at the periphery of the substrate; or,

a gate electrode insulating layer is formed using a mask growth process.

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