CN100339970C - Method for testing chip synchronous clock and chip capable of synchronously testing clock function - Google Patents

Abstract

A method for testing a chip synchronous clock and a chip capable of synchronously testing clock functions are provided. The chip at least comprises a first logic part driven by a first clock signal and a second logic part driven by a second clock signal, wherein the working frequency of the first clock is higher than the working frequency of the second clock and is not an integral multiple of the working frequency of the second clock signal, and the test method comprises the following steps: and generating a third clock signal with the working frequency greater than the first clock signal and an integral multiple of the working frequency of the second clock signal. The first clock signal is replaced with a third clock signal. And testing the parts of the chip except the first clock generation device according to the second clock signal and the third clock signal. The first logic portion is operated independently of the second logic portion according to the first clock signal, and the first clock generation device is tested according to the output of the first logic portion.

Description

Method for testing chip synchronous clock and chip capable of synchronously testing clock function

technical field

The invention relates to a chip testing method, in particular to a chip testing method capable of avoiding sampling errors produced by asynchronous effects.

Background technique

Generally, in the chip manufacturing process, the chip testing process must be passed at the end to confirm the manufacturing quality of the chip. In the process of chip testing, the computer simulates the ideal output signal of the chip at a specific input signal and records it; then, the same specific input signal is provided to the chip to be tested, and then the output signal of the chip under test is compared with the The ideal output signal is compared to determine whether it is consistent, and to determine whether there is a defect in the chip manufacturing process.

In order to meet different requirements of electronic products, the operating frequencies required by each chip specification are different, for example, chips with two different operating frequencies. However, if a chip with two different operating frequencies is to be tested, the chip test may become relatively difficult due to the asynchronous effect.

The impact of the asynchronous effect on the chip test will be described below with reference to FIG. 1 and FIG. 2 . Figure 1 shows a typical flip-flop logic circuit, which can be included in a chip.

As shown in FIG. 1, if the input signal D2 is in the second flip-flop 2, the second flip-flop 2 will sample the input signal D2 according to the first clock signal CLK2 to output the signal Q2 to the logic circuit Lg, and through the logic circuit Lg output signal D1. When the first flip-flop 1 receives the signal D1, it samples the signal D1 according to the first clock signal CLK1 to output the signal Q1. Wherein, the delay time between the signal Q2 and the signal D1 will be affected by the manufacturing difference of the logic circuit Lg. For example, this delay time is 1.7-2.3 ns.

As shown in FIG. 2 , FIG. 2 shows waveform diagrams of the first clock CLK1 and the second clock CLK2 in FIG. 1 . Wherein, the operating frequency of the first clock signal CLK1 is higher than the operating frequency of the second clock signal CLK2, and the operating frequency of the first clock signal CLK1 is not an integer multiple of the operating frequency of the second clock signal CLK2. The first clock signal CLK1 is, for example, 250 MHz, and the second clock signal CLK2 is, for example, 66 MHz. When the signal D2 is sampled at 30 ns, the second flip-flop 2 outputs the signal Q2 to the logic circuit Lg. If the delay time between the signal D1 and the signal Q2 outputted by the logic circuit Lg is 1.7 ns-2.3 ns, that is, the logic circuit Lg may send the signal D1 at 31.7 ns-32.3 ns after receiving the signal Q2 at 30 ns. Therefore, according to the positive edge trigger of the first clock signal CLK1 , the first flip-flop 1 may sample the signal D1 at 32 ns, and may also sample the signal D1 at 36 ns. It can be known from the above that, in the same sampling clock, the first flip-flop 1 has two sampling times, therefore, it is easy to cause a sampling error of the first flip-flop 1 , which is an asynchronous effect.

Similarly, when the logic circuit Lg receives the signal Q2 at 15ns, if the delay time between the signal D1 output by the logic circuit Lg and the signal Q2 is 0.8ns~1.2ns, then the first flip-flop 1 may perform a signal at 16ns or 20ns. Sampling, therefore, will produce an asynchronous effect; in addition, when the logic circuit Lg receives the signal Q2 at 45ns, if the delay time between the signal D1 output by the logic circuit Lg and the signal Q2 is 2.8ns ~ 3.2ns, the first flip-flop 2 It will be possible to sample the signal at 48ns or 52ns, which will also produce asynchronous effects.

Asynchronous effects do not affect the normal operation of the chip. However, when performing chip testing, since the output signal of the chip must be compared with the ideal signal, and when the output signal is completely consistent with the ideal signal, the manufacturing quality of the chip can be confirmed to be flawless. Therefore, the sampling caused by the asynchronous effect Errors will affect the results of the test.

It can be seen from the above that in order to avoid the asynchronous effect from affecting the chip test results, the delay time of the logic circuit Lg cannot exceed 1ns (0.8ns~1.2ns), 2ns (1.7~3.2ns) and 3ns (2.8ns~3.2ns). Therefore, In the design of the flip-flop logic circuit, the delay time of the logic circuit Lg must be limited, which leads to difficulties in chip design.

Contents of the invention

In view of this, the present invention proposes a method for testing a chip synchronous clock to avoid problems caused by asynchronous effects and improve the accuracy of chip testing.

The present invention proposes a method for chip synchronous clock testing, wherein the chip includes a first logic part driven by a first clock signal and a second logic part driven by a second clock signal, and the test method includes : generating a third clock signal according to the second clock signal; testing the first logic part according to the third clock signal; and testing the second logic part according to the second clock signal; wherein the first The operating frequency of the clock signal is higher than the operating frequency of the second clock signal and is not an integer multiple of the operating frequency of the second clock signal, and wherein the operating frequency of the third clock signal is greater than the operating frequency of the first clock signal and is Integer multiples of the operating frequency of the second clock signal.

The present invention also proposes a chip capable of synchronously testing the clock function, the chip comprising: a first clock generating device for generating a first clock signal; a second clock generating device for generating a second clock signal and a third clock signal; a selection device, receiving the first clock signal and the third clock signal, for selecting and outputting one of the first clock signal or the third clock signal; a first logic unit connected to To the selection device, used to receive the clock signal selected by the selection device to test the first logic part; and a second logic part, connected to the second clock generation device, to receive the second clock signal; Wherein, the operating frequency of the first clock signal is higher than the operating frequency of the second clock signal and is not an integral multiple of the operating frequency of the second clock signal, and the operating frequency of the third clock signal is greater than the operating frequency of the first clock signal and is an integer multiple of the operating frequency of the second clock signal.

Since the operating frequency of the third clock signal is an integral multiple of the operating frequency of the second clock signal, the method of testing the above-mentioned chip with the third clock signal instead of the first signal can effectively avoid asynchronous effects and improve chip performance. The accuracy of the test.

In order to make the above-mentioned purpose, features and advantages of the present invention more comprehensible, a preferred embodiment is specifically cited below and described in detail with reference to the accompanying drawings.

Description of drawings:

Figure 1 shows a typical flip-flop logic circuit.

FIG. 2 shows a waveform diagram of the first clock CLK1 and the second clock CLK2 in FIG. 1 .

Fig. 3 shows a chip to which the chip testing method of the present invention is applied.

FIG. 4 is a waveform diagram illustrating the second clock signal CLK2 and the third clock signal CLK3 for testing the chip 3 .

Fig. 5 shows a flow chart of the chip testing method of the present invention.

Explanation of reference symbols:

1, 2～trigger; Lg～logic circuit; D2～chip input signal; Q2, D1～logic signal; Q1～chip output signal; CLK1, CLK2, CLK3～clock signal; 3～chip; 30～clock generating device; 31~selection device; 32~first logic unit; 33~second logic unit; 40~first clock generation device; 41~second clock generation device; Vo~output signal.

Detailed ways

The invention provides a chip testing method, which can avoid problems caused by asynchronous effects and improve the accuracy of chip testing.

Fig. 3 shows a chip to which the chip testing method of the present invention is applied. Wherein, the chip 3 includes a clock generating device 30 , a selecting device 31 , a first logic part 32 and a second logic part 33 . During normal operation, the first logic part 32 is driven by the first clock signal CLK1, the second logic part 33 is driven by the second clock signal CLK2, and the operating frequency of the first clock CLK1 is higher than that of the second clock CLK2 and is not Integer multiples of the working frequency of the second clock signal CLK2. The clock generating device 30 includes a first clock generating device 40 and a second clock generating device 41; the first clock generating device 40 is used to generate the first clock signal CLK1, and the second clock generating device 41 is used to generate the second clock signal CLK2 and the third clock signal CLK3. The selection device 31 is used to select and output the first clock signal CLK1 or the third clock signal CLK3 to provide a normal operation signal or a test signal of the chip 3 .

In this embodiment, the chip 3 is, for example, a graphics processing chip. The chip 3 can use the first logic part 32 to process the instruction signal of the central processing unit (not shown), and use the second logic part 33 to control the computer graphics interface (computer graphics interface) (not shown). If it is assumed that the operating frequency of the first clock signal CLK1 is 250 MHz, and the operating frequency of the second clock signal CLK2 is 66 MHz, but during the test, since the operating frequency of the first clock signal CLK1 is not an integer of the operating frequency of the second clock signal CLK2 Therefore, if the chip 3 is supplied with the first clock signal CLK1 and the second clock signal CLK2, it will obviously cause an asynchronous effect and cause test errors.

Therefore, when testing the chip 3 , the selection device 31 selects and outputs the third clock signal CLK3 to replace the first clock signal CLK1 , so as to use the second clock signal CLK2 and the third clock signal CLK3 to test the graphics processing chip 3 . Wherein, the working frequency f3 of the third clock signal CLK3 needs to satisfy f3=f2*k, and f2*(k-1)<f1<f3, k is an integer.

When the first logic part 32 receives the third clock signal CLK3 and the second logic part 33 receives the second clock signal CLK2, the first and second logic parts 32 can perform corresponding actions through the communication of the logic signal Sc. Therefore, when the first logic unit 32 receives the third clock signal CLK3 and the logic signal Sc, it can sample the input signal of the chip according to the third clock signal CLK3 and the logic signal Sc, so as to output the test signal.

FIG. 4 is a waveform diagram illustrating the second clock signal CLK2 and the third clock signal CLK3 for testing the chip 3 . Wherein, in this embodiment, the working frequency f2 of the second clock signal CLK2 is, for example, 66 MHz, and the working frequency f3 of the third clock signal CLK3 is, for example, 266 MHz.

As shown in Figure 4, if the second logic part 33 outputs the logic signal Sc at 15ns, then the first logic part 32 can sample the input signal of the chip and output the test signal at 18.75ns or 22.5ns, therefore, the first logic The sampling time difference of part 32 is 3.75ns (18.75ns-15ns=3.75ns) or 7.5ns (22.5ns-15ns=7.5ns); Similarly, if the second logic part 33 outputs the logic signal Sc at 30ns, the first logic The sampling time difference of part 32 is also 3.75ns (33.75ns-30ns=3.75ns) or 7.5ns (37.5ns-30ns=7.5ns); Similarly, if the second logic part 33 outputs the logic signal Sc at 45ns, the first The sampling time difference of the logic part 32 is also 3.75ns (48.75ns-45ns=3.75ns) or 7.5ns (47.5ns-45ns=7.5ns). It can be seen that, when testing the chip 3, if the first clock signal CLK1 is replaced by the third clock signal CLK3, the sampling time difference in each sampling period is the same. Therefore, when the delay time of the logic circuit Lg does not exceed 3.75 ns, Then the first logic unit 32 can obtain the correct sampling signal according to the same sampling time difference. Compared with FIG. 3 , the delay requirement of the logic circuit Lg cannot exceed 1 ns, 2 ns and 3 ns, and FIG. 4 only requires that it cannot exceed 3.75 ns. It can be known from the above that the chip testing method of the present invention can effectively avoid the sampling error caused by the asynchronous effect, and increase the correctness of the chip testing results.

When using the second clock signal to test the second logic part, the output signal of the second logic part can be used to judge whether the second clock generating device correctly generates the second clock signal. At the same time, when the third clock signal is used to test the first logic part, the output signal of the first logic part can be used to judge whether the second clock generating device correctly generates the third clock signal.

In addition, the chip testing method of the present invention can also test the first clock signal CLK1 of the first clock generating device 40 . Since the first clock signal CLK1 is replaced by the third clock signal CLK3 during testing, the first clock generating device 40 cannot be tested. In order to test the first clock generating device, firstly, the operation of the first logic unit 32 is independent of the first clock generating device. Two logic parts 33, that is to say, there is no communication of signal Sc between the first logic part 32 and the second logic part logic 33, and then provide the first clock signal CLK1 in the first logic part 32, thereby by the first logic part 32 The output signal Vo is used to judge whether the first clock generating device 40 outputs the first clock signal CLK1 normally.

In this embodiment, the selection switch 31 is, for example, a multiplexer, and the first clock generating device 40 and the second clock generating device 41 are, for example, phase-locked circuits.

Fig. 5 shows a flow chart of the chip testing method of the present invention. First, a third clock signal is generated according to a second clock signal, and its operating frequency is greater than the first clock signal and is an integer multiple of the operating frequency of the second clock signal (S501); then, the third clock signal is used to replace the first clock signal (S502); Utilize the second clock signal and the third clock signal respectively again, test chip 3 other parts except the first clock generating device (S503); Finally, the first logic part in the chip is independent from the second logic The first logic part is tested by using the first clock signal, and it is judged according to the output signal of the first logic part whether the first clock generating device correctly reads and generates the first clock signal (S504).

Wherein, the operating frequencies of the first, second and third clocks are respectively f1, f2 and f3, and f3=f2*k, f2*(k-1)<f1<f3, k is an integer.

The preferred embodiments of the present invention disclosed above are only used to help understand the implementation of the present invention, and are not intended to limit the spirit of the present invention. Those skilled in the art will not depart from the spirit of the present invention after comprehending the spirit of the present invention. Under the premise of the scope, some modifications and equivalent changes can be made, and the scope of patent protection is based on the claims of the present invention.

Claims (10)

1. A method for chip synchronous clock testing, wherein the chip includes a first logic unit driven by a first clock signal, and a second logic unit driven by a second clock signal, the test method comprising: generating a third clock signal according to the second clock signal; testing the first logic part according to the third clock signal; and testing the second logic part according to the second clock signal; Wherein the operating frequency of the first clock signal is higher than the operating frequency of the second clock signal and is not an integral multiple of the operating frequency of the second clock signal, and wherein the operating frequency of the third clock signal is greater than that of the first clock signal The working frequency is an integer multiple of the working frequency of the second clock signal. 2. The method for chip synchronous clock test as claimed in claim 1, wherein the operating frequencies of the first, second and third clocks are respectively f1, f2, f3, and f3=f2*k, f2*(k-1 )<f1<f3, k is an integer. 3. The method for chip synchronous clock testing as claimed in claim 1, wherein the first clock signal is generated by a first clock generating device of the chip. 4. The method for chip synchronous clock testing according to claim 3, further comprising making the operation of the first logic part independent of the second logic part, and providing the first clock signal to the first logic part, And according to an output signal of the first logic part, it is tested whether the first clock generating device normally outputs the first clock signal. 5. A chip capable of synchronously testing the clock function, the chip comprising: A first clock generating device, used to generate a first clock signal; A second clock generating device for generating a second clock signal and a third clock signal; a selection device, receiving the first clock signal and the third clock signal, for selecting and outputting one of the first clock signal or the third clock signal; a first logic part, connected to the selection device, for receiving the clock signal selected by the selection device to test the first logic part; and a second logic part, connected to the second clock generating device, for receiving the second clock signal; Wherein, the operating frequency of the first clock signal is higher than the operating frequency of the second clock signal and is not an integral multiple of the operating frequency of the second clock signal, and the operating frequency of the third clock signal is greater than the operating frequency of the first clock signal and is an integer multiple of the operating frequency of the second clock signal. 6. The chip capable of synchronously testing clock functions as claimed in claim 5, wherein when the operating frequency of the first clock signal is higher than the operating frequency of the second clock signal and is not an integer multiple of the operating frequency of the second clock signal , the selection device selects the third clock signal to test the first logic part. 7. The chip capable of synchronously testing the clock function as claimed in claim 5, wherein the signal output by the second logic part is used to determine whether the second clock generating device correctly generates the second clock signal. 8. The chip capable of synchronously testing clock functions as claimed in claim 5, wherein the selecting means selects the first clock signal to control and test the first clock generating means. 9. The chip capable of synchronously testing the clock function as claimed in claim 8, wherein it is judged according to the signal output by the first logic part whether the first generating device correctly outputs the first clock signal. 10. The chip capable of synchronously testing the clock function as claimed in claim 5, wherein the operating frequencies of the first clock signal, the second clock signal and the third clock signal are respectively f1, f2, f3, and f3=f2 *k, f2*(k-1)<f1<f3, k is an integer.

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