JPH117461A - Logic simulation method and test pattern generator - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a simulation method which is applied regardless of circuit configuration and depends on an input signal including skew by changing an input signal of all event changes except a clock signal into a pulse signal of a cycle that is below time corresponding to skew a device checking device has. SOLUTION: A test pattern generator 30 is provided with a CPU 32 to which an output end of an inputting part 31 to which an input signal is inputted, memory 33 to which the CPU 32 is connected and an outputting part 34 to which an output end of the CPU 32 is connected. A test pattern is produced with an input signal that is inputted from the part 31. A signal output for check based on the test pattern is applied to non-check semiconductor integrated circuit 50 through a device checking device 40. Timing is confirmed about all signals by generating a test pattern for logic simulation that respectively has one pulse signal before and after event changes of all pin inputs except a clock signal in this way.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a logic simulation method used in inspection of a semiconductor integrated circuit and a test pattern generation device therefor.

[0002]

2. Description of the Related Art A skew occurs between input signals applied to a plurality of terminals of a device by a device inspection apparatus for inspecting a device such as a semiconductor integrated circuit due to an error of the device inspection apparatus. Therefore, an input signal may not be applied at a desired time. As a result, even in the case of a test pattern whose timing has been confirmed by a logic simulation, a malfunction may occur due to the skew and correct inspection may not be performed.

In the prior art disclosed in Japanese Patent Application Laid-Open No. Hei 5-189517, in order to solve this problem, an input event change (input) is applied to each input signal pin (connection terminal) of the device under test except for a clock signal. Immediately after the signal state change), a circuit for generating an indefinite state (a state in which the signal is not known as 0 or 1) corresponding to the skew is inserted. Then, a circuit for delaying the clock signal by a period shorter than the period corresponding to the skew, for example, a half period of the period corresponding to the skew is inserted into the pin of the clock signal. According to the above method, the timing is confirmed by a logic simulation including a skew generated by the device inspection apparatus.

[0004]

However, in the above-mentioned prior art, the input signal pins of the semiconductor integrated circuit do not pass through a sequential circuit such as a flip-flop, but only through a combinational circuit such as an AND circuit, an OR circuit, and an inverter. Therefore, if the input signal pin is in an undefined state when connected to a storage element with an asynchronous reset or set, the undefined state propagates to the reset or set pin of the storage element, and the output of the storage element becomes undefined. Become.

For this reason, when an event (state of an input signal) for canceling the reset or set of the storage element occurs, it is necessary to reset or set the memory element after the event has occurred. There is a possibility that an undefined state may enter between a logic state to be reset and a logic state not to be reset or set. In this case, there is a problem that the output of the storage element remains in an undefined state, and the expected value of the output signal is changed. To solve this problem, in the conventional technology, a circuit that generates an indeterminate state is not inserted into an input signal pin connected to an asynchronous reset or set terminal of a storage element only through a combinational circuit, and skew is included. It was excluded from the simulation.

SUMMARY OF THE INVENTION The present invention solves the above-mentioned conventional problems, and a simulation method using an input signal including a skew which can be applied without changing a circuit of a device inspection apparatus and irrespective of the circuit configuration, and a method thereof. It is an object to provide a test pattern generation device.

[0007]

According to the present invention, all input signal pins except for a clock signal applied to a semiconductor integrated circuit under test have a terminal skew before and after an event change of the input signal. The simulation is performed by applying a pulse signal having a period shorter than the corresponding time. The conversion from the skew-free normal input signal to the pulse signal is performed by software for generating a test pattern for logic simulation.

According to the present invention, a device inspection apparatus is provided by giving a time width to the event change of a normal input signal and inputting a signal having a clear logic to all input signal pins of a semiconductor integrated circuit. The timing of a signal including the generated skew can be confirmed by logic simulation.

Therefore, all the input signal pins except the clock signal, that is, the input signal pins connected to the asynchronous reset input or the set input of the storage element through only the combinational circuit are also included in the simulation including skew. Can be included. Also, by inserting a pulse signal before an input event change, there is no need to particularly delay the clock signal.

[0010]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described with reference to FIGS. FIG. 1 shows a simple example of a circuit under test for explaining the logic simulation method of the present invention.
FIG. 4 is a block diagram of a test pattern generation device 30 according to the present invention. The test pattern generation device 30 includes a CPU 3 to which an output terminal of an input unit 31 to which an input signal is input is connected.
2. Memory 33 and CPU 32 connected to CPU 32
Is provided with an output unit 34 to which the output terminal of the. A test pattern is generated based on an input signal input from the input unit 31, and a signal output for inspection based on the test pattern is applied to the device to be inspected, for example, the semiconductor integrated circuit 50 via the device inspection apparatus 40.

Referring to FIG. 1, a case where an input signal Data1 is input to an input terminal D of a flip-flop 8 via an input buffer 6 and a clock signal Clock2 is input to an input terminal CK via an input buffer 7 will be described below.

FIG. 2A shows the waveform of the input signal Data1. The logic simulation test pattern generation device 30 generates a test pattern based on the input signal Data1.

The input signal Data1 is processed into an input signal S_Data10 having a waveform shown in FIG. 2B by software stored in the memory 33 in advance. For rising the event R, before the event change time t ₁ of the input signal Data1, to insert a positive pulse 11 of the pulse width equal to the negative skew period T ₁ of the device inspecting apparatus 40. Further inserted negative pulse 12 of the pulse width equal to the positive skew period T ₂ of the device inspecting apparatus 40 after the event change time t _1. Device In the case of the falling event F, insert the negative pulse 12 of the pulse width equal to the negative skew period T ₁ of the device inspecting apparatus 40 prior to the event change time t _2, after the event change time t ₂ inserting a positive pulse 11 of the pulse width equal to the positive skew period T ₂ of the testing apparatus 40. The input signal S-Data1 processed as described above
0 is input to the input terminal D via the input buffer 6 instead of the input signal Data1.

FIG. 3A shows a processed input signal S_D.
The signal interS_Data 13 in a state where the data 10 reaches the input terminal D of the flip-flop 8 is shown. FIG.
(B) shows a signal interC when the clock signal Clock2 reaches the input terminal CK of the flip-flop 8.
lock14. FIG. 3C shows the signal output interQOut 15 of the flip-flop 8. If there is no skew in the signal interS_Data13, the high level is fetched and the signal output interQO
ut15 should be high. . But Figure 3
When the inspection apparatus has a positive skew as shown in (a) of FIG.
The lock 14 captures the low level of the signal interS_Data, and the signal output interQOut becomes low level. If the low-level output gives a result different from a normal state to a predetermined external output terminal of the semiconductor integrated circuit 50, the logic simulator issues a warning of an expected value error. That is, it is known in advance that a failure occurs due to the skew of the device inspection apparatus at the input timing of the test pattern.

FIG. 5 shows the operation of the test pattern generator 30.
This will be described with reference to the flowchart of FIG.

Each time an event of an input signal occurs (step 17 in FIG. 5), the type of the pin of the signal is determined (step 18). When the input signal is a clock signal, the event change is simply converted into a test pattern (step 19). If the input signal is not a clock signal, this event change is converted to a test pattern at a time T ₁ before the event occurrence time (step 2).
0). Next, at the event occurrence time, the event change is converted into a test pattern of the event change which is the reverse of the event change (step 21). Finally converted from the event occurrence time of this event changes to the test pattern in time after time T ₂ (the step 22). This process is repeated until all occurrences of events are completed. If all the events have been completed, the test patterns are rearranged in chronological order (step 24). The processing from step 17 to step 24 is performed by the test pattern generation device 30 shown in FIG.
Is performed by the CPU 32 and the memory 33. Time T _1, T ₂ are, in the case specifically device inspection apparatus of the time accuracy is ± 0.6 ns of the input signal applied to the device, the time T ₁ is 0.6 ns, the time T ₂ are a value of 0.6 ns become.

[0017]

According to the logic simulation method of the present invention,
By generating test patterns for logic simulation each having one pulse signal before and after the event change of the input of the pin of all the input signals except the clock signal, the device measuring apparatus is generated for all the input signals. Timing can be checked by logic simulation including skew.

Since the clock signal does not need to be changed, it is not necessary to adjust the time at which the expected value of the output signal is compared. Conventionally, it was necessary to add a circuit, but the test pattern generation device of the present invention has a CPU and a memory, and is implemented by incorporating a function of generating the above test pattern into a program for generating a test pattern for logic simulation of the memory. As a result, there is no need for new equipment and there is also an effect of reducing the number of development steps.

[Brief description of the drawings]

FIG. 1 is a logic circuit diagram for explaining an embodiment of the present invention.

FIGS. 2A and 2B show examples of test pattern conversion according to the present invention.

FIG. 3 is a timing chart for explaining an embodiment of the present invention.

FIG. 4 is a block diagram of a test pattern generation device according to an embodiment of the present invention.

FIG. 5 is a flowchart for explaining an embodiment of the present invention.

[Explanation of symbols]

 1 input signal Data 2 clock Clock 6 input buffer 7 input buffer 8 flip-flop 10 input signal S_Data 11 positive pulse 12 negative pulse 13 signal interS_Data 14 signal interClock 15 signal output interQOut

Claims (3)

[Claims] 1. An input signal of all event changes except a clock signal applied from a device inspection apparatus to a semiconductor integrated circuit to be inspected is converted into a pulse signal having a period equal to or less than a time corresponding to a skew of the device inspection apparatus. A logic simulation method characterized by changing. Detecting an event change of a normal input signal which is a reference of an input signal applied from the device inspection apparatus to the semiconductor integrated circuit to be inspected; A logic simulation pattern generating step of converting the pulse signal into a pulse signal having a period equal to or shorter than the time corresponding to the skew of the inspection device. 3. An event change detecting means for detecting an event change of an input signal applied from the device inspection apparatus to the semiconductor integrated circuit to be inspected, and the device inspection apparatus has the event change detecting means detecting the event change. Means for generating a pulse signal having a period equal to or less than the time corresponding to the skew, and a test pattern generation apparatus for a logic simulation.