CN112526326A - Time sequence testing method, system, device and storage medium - Google Patents
Time sequence testing method, system, device and storage medium Download PDFInfo
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Abstract
本申请提供时序测试方法、系统、装置及存储介质，方法中通过从待测的数字电路模块的预设时序参数数据提取时序信息；根据所述预设时序参数数据产生噪声信息；根据所述时序信息产生严格时序要求的第一时序激励信号；令所述噪声信息作用于所述第一时序激励信号以得到第二时序激励信号，以用于所述数字电路模块的时序仿真而得到时序仿真结果，并根据所述时序仿真结果得到对待测的数字电路模块的时序测试结果。在数字电路模块的时序验证中引入噪声，使时序验证更加贴合实际运行环境，令验证结果更加可靠，且对于一些定制化电路设计中的未考虑噪声的时序验证方式，能有效提升其可靠性。
The present application provides a timing test method, system, device and storage medium. In the method, timing information is extracted from preset timing parameter data of a digital circuit module to be tested; noise information is generated according to the preset timing parameter data; information to generate a first timing excitation signal with strict timing requirements; make the noise information act on the first timing excitation signal to obtain a second timing excitation signal, which is used for timing simulation of the digital circuit module to obtain a timing simulation result , and obtain the timing test result of the digital circuit module to be tested according to the timing simulation result. Noise is introduced in the timing verification of digital circuit modules, so that the timing verification is more suitable for the actual operating environment, and the verification results are more reliable, and for some customized circuit design timing verification methods that do not consider noise can effectively improve their reliability. .
Description
Technical Field
The embodiment of the application relates to the technical field of chip design, in particular to a time sequence testing method, a time sequence testing system, a time sequence testing device and a storage medium.
Background
In a digital integrated circuit, an Intellectual Property core or an Intellectual Property (IP) module is usually mentioned, which refers to a pre-designed circuit function module, and digital IP is a pre-designed digital circuit module with a specific function.
For digital circuit modules, correct timing is the primary parameter to ensure their function to be normal and their performance to meet the standard. On the contrary, the timing violation affects the performance slightly, so that the digital circuit module does not reach the expected speed, and the functional error is serious, thereby causing the functional errors of the downstream layer and the upper layer.
Many integrated circuit Design companies and Electronic Design Automation (EDA) manufacturers Design a large number of Quality Assurance (QA) methods and abstract models to simulate circuit timing and check the correctness of the simulated timing results.
For example, in the physical design stage, the circuit netlist with the parasitic resistance-capacitance parameters after the layout is formed is subjected to post-simulation to check the timing sequence, the power consumption margin and the like, a timing sequence parameter file (such as a lib format) is extracted, and then various detections are performed around the timing sequence parameter file to avoid timing sequence violation and guarantee the accuracy of the timing sequence.
The effects of some analog circuits are increasingly being considered in digital circuit design, given the continuing increase in process yield and the continuing decrease in process feature size. For example, miller effect when fast signals are transmitted to gate-level circuits, noise such as signal crosstalk between metal lines, etc.
For digital circuits that need to operate at high speed, the requirement for the correctness of the operation timing is more strict, so these noises should be considered, but there is still a certain deficiency in this respect in the timing verification of the current simulation.
Disclosure of Invention
In view of this, embodiments of the present application provide a timing testing method, system, apparatus, and storage medium, which solve the problems in the prior art.
The embodiment of the application provides a time sequence testing method, which comprises the following steps: extracting time sequence information from preset time sequence parameter data of a digital circuit module to be tested; generating noise information according to the preset time sequence parameter data; generating a first timing excitation signal with strict timing requirements according to the timing information; and enabling the noise information to act on the first time sequence excitation signal to obtain a second time sequence excitation signal, so as to be used for time sequence simulation of the digital circuit module to obtain a time sequence simulation result, and obtaining a time sequence test result of the digital circuit module to be tested according to the time sequence simulation result.
Optionally, the strict timing requirement refers to: the time sequence parameter used for generating the first time sequence excitation signal and obtained from the time sequence information is the same as or shorter than the corresponding time sequence parameter in the preset time sequence parameter data; the corresponding timing parameters include: setup time and hold time of the signal.
Optionally, the corresponding timing parameter further includes: at least one of path delay and cycle time.
Optionally, the generating noise information according to the preset time sequence parameter data includes:
extracting noise model parameters from the preset time sequence parameter data;
establishing a noise model according to the noise model parameters;
generating the noise information by the noise model.
Optionally, the type of the noise model includes one of: a composite current source noise model, an effective current source noise model, a static noise model, a dynamic noise model, and a noise immunity model.
Optionally, the mode of applying the noise information to the digital circuit module includes at least one of:
introducing negative noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
introducing positive noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
introducing negative noise to a data path in the digital circuit module and introducing positive noise to a clock path in the digital circuit module;
positive noise is introduced to the data path in the digital circuit block and positive noise is introduced to the clock path in the digital circuit block.
Optionally, the making the noise information act on the first timing excitation signal to obtain a second timing excitation signal, so as to be used for timing simulation of the digital circuit module to obtain a timing simulation result, and obtain a timing test result of the digital circuit module to be tested according to the timing simulation result, including:
and comparing the measurement index corresponding to the time sequence simulation result with the standard measurement index to obtain a time sequence test result.
Optionally, the standard measurement indicator is obtained in a manner that:
obtaining a loose excitation signal according to the first time sequence excitation signal or the second time sequence excitation signal, and obtaining a loose time sequence simulation result for the time sequence simulation of the digital circuit module;
and obtaining the measurement index of the loose time sequence simulation result as the standard measurement index.
Optionally, the measurement indicator includes at least one of the following: a functional index; performance index.
Optionally, the timing sequence testing method further includes:
and when the time sequence test result is passed, iteratively executing the steps of the time sequence test method until the time sequence test result is passed.
Optionally, the digital circuit module corresponds to a design in the post-layout netlist.
Optionally, the preset time sequence parameter data is stored in a preset time sequence parameter file corresponding to the digital circuit module.
The embodiment of the application provides a time sequence test system, including:
the time sequence information extraction module is used for extracting time sequence information from preset time sequence parameter data of the digital circuit module to be tested;
the noise generation module is used for generating noise information according to the preset time sequence parameter data;
the signal generating module is used for generating a first time sequence excitation signal with strict time sequence requirements according to the time sequence information;
and the simulation detection module is used for enabling the noise information to act on the first time sequence excitation signal to obtain a second time sequence excitation signal, so as to be used for time sequence simulation of the digital circuit module to obtain a time sequence simulation result, and obtaining a time sequence test result of the digital circuit module to be tested according to the time sequence simulation result.
The embodiment of the application provides a computer device, which comprises a memory and a processor, wherein a computer program capable of being run by the processor is stored in the memory, and the steps in the time sequence testing method are executed when the processor runs the computer program.
The embodiment of the application provides a computer readable storage medium, wherein an executable program code is stored on the computer readable storage medium, and the executable program code executes the time sequence testing method when running.
Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:
on one hand, the scheme in the embodiment of the application introduces noise in the time sequence verification of the digital circuit module, so that the time sequence verification is more fit with the actual operation environment, and the verification result is more reliable.
On the other hand, the scheme in the embodiment of the application can further improve the reliability of the timing verification in some specific verification modes, for example, the influence of noise information is considered in a full-speed test, and the actual operation environment is more strictly attached on the basis of strict timing, so that the timing test result is more reliable.
Drawings
Fig. 1A is a schematic diagram of an exemplary circuit.
Fig. 1B shows a waveform diagram of signals at the input and output of the circuit in fig. 1A, which are affected by crosstalk.
Fig. 2A is a schematic diagram of another exemplary circuit.
Fig. 2B-2D are waveform diagrams illustrating the invaded network in fig. 2A being interfered by different signal states of the invaded network.
FIG. 3 shows a timing diagram labeled setup time and hold time.
Fig. 4 is a flowchart illustrating a timing testing method according to an embodiment of the present application.
Fig. 5 is a schematic diagram showing the specific steps of the noise generation process in step S402 in the embodiment of the present application.
Fig. 6 shows a schematic diagram of an implementation principle of noise information introduction in the embodiment of the present application.
Fig. 7A shows a waveform diagram of introducing a positive noise increase delay in the embodiment of the present application.
Fig. 7B shows a waveform schematic diagram of introducing negative noise reduction delay in the embodiment of the present application.
Fig. 8 is a schematic diagram illustrating a specific process of performing timing verification according to a simulation result in step S404 in the embodiment of the present application.
FIG. 9 is a block diagram of a timing test system according to an embodiment of the present application.
Fig. 10 is a schematic structural diagram of a computer device according to an embodiment of the present application.
Detailed Description
As previously mentioned, in digital circuit design, the effect of analog circuit effects in digital circuit design has to be considered. For example, miller effect when fast signals are transmitted to gate-level circuits, noise such as signal crosstalk between metal lines, etc.
As shown in fig. 1A, a schematic diagram of an exemplary circuit is shown.
As shown, IN the circuit, two metal semiconductor transistors (MOSFETs) (IN other examples, transistors are also used) connected between a power supply terminal (VDD) and a ground terminal (GND) are exemplarily shown, and an upper P-type MOSFET and a lower N-type MOSFET are connected to form an inverter circuit, that is, signals of an input terminal (IN) and an output terminal (OUT) are IN opposite states as shown IN fig. 1B; a capacitor C is connected between the input end and the output endm。
Due to the fact that in practical situations parasitic capacitances exist in the MOSFET, e.g. the capacitance C between the gate and the sourcegsAnd the parasitic capacitances are expanded by a certain factor in the process of inputting signals to the output due to the miller effect, so that the input and output signals are influenced.
As shown IN fig. 1B, IN the waveform of the input signal at the input terminal (IN) without taking the miller effect into account, the dotted line at a represents an ideal case of the input signal without taking the miller effect into account, while the dotted line at B represents a practical possible case of the partial input signal with taking the miller effect into account, and IN the case that the transverse axis of the waveform IN the figure is time, it can be found that B has a certain time delay with respect to a IN the partial input signals at A, B.
Accordingly, in the waveform of the output signal at the output terminal (OUT), a part of the output signal waveform not considering the miller effect is shown by a fine broken line at C, and a part of the output signal waveform considering the miller effect is shown at D, and it can be found that D is delayed from C as shown by Δ t in the figure.
From fig. 1A and 1B, it can be found that the miller effect has a non-negligible effect on the output signal of the digital circuit block.
Referring again to fig. 2A, a schematic diagram of yet another example of a circuit is shown.
In fig. 2A, z 1-z 4 are circuit devices or circuit blocks, the aggressor network a1 is opposite to the victim network N1, the victim network N1 and the aggressor network a1 are exemplarily represented as adjacent metal lines, and the coupling capacitance Cc is distributed between the two metal lines.
Fig. 2B, 2C, and 2D respectively illustrate an exemplary case where the victim network N1 may or may not be affected by N1 crosstalk when the signal flips from low to high.
In fig. 2B, the aggressor network a1 is shown in a state where the signal flips from high to low, and the ideal signal waveform of N1, represented by the solid line in the figure, is distorted into a state like F at E due to the crosstalk of a1 to N1, with a delay; in fig. 2C, the aggressor network a1 is shown in a steady state (i.e., unchanged), shown as a dashed line, while the signal of N1 is shown as a solid line, a1 may not have an effect on N1 in the steady state; as shown in fig. 2D, the aggressor network a1 is in a state where the signal flips from low to high, as shown by the long dashed line in G, and the ideal signal of N1 is shown by the solid line H, but due to the crosstalk, its actual signal is shown by the short dashed line I. It can be seen that under the influence of crosstalk of the aggressor network a, the actual signal I of N1 is advanced, i.e., reduced in delay, compared to H.
The indexes to be analyzed in the static timing analysis of the digital circuit module at least comprise:
setup time (setup time) is the time that data must be stable before the clock signal source arrives, and if the setup time is not met, the data cannot be correctly driven into the sequential logic cell.
Hold time (hold time) the time that data must settle after the clock signal source arrives, if the hold time is not sufficient, the data is latched correctly by the sequential logic cells.
Optionally, the digital circuit module may also need to analyze a cycle time (cycle time).
As shown in fig. 3, a schematic diagram of setup time and hold time is shown.
At the rising edge X of the clock signal in the figure, a period of time before the rising edge X is the setup time, and a period of time after the rising edge X is the hold time, which must be stabilized to ensure that the data is correctly read and written, so that the digital circuit module operates correctly.
However, in the examples of fig. 1A to 1B and fig. 2A to 2B, noises such as the influence of miller effect and crosstalk invading the network, which are shown, may affect the setup time and the hold time and affect the digital circuit module.
However, in the design flow of a digital IP circuit module (e.g. a memory IP module) for high-Speed operation, a full-Speed Test (At-Speed Test) is performed in post-simulation, and the full-Speed Test means that very strict requirements are imposed on the timing correctness of the digital circuit module, especially the requirements on setup time and hold time are more strict; however, since the full-speed test may be performed by using the predetermined timing parameter data of the digital circuit module to generate the stimulus signal for timing verification itself, or it is considered that the timing requirement is strict enough, and the problem that the predetermined timing parameter data needs to consider the actual noise effect is ignored.
Since the digital circuit module, which requires high-speed operation, is tested at full speed during timing verification, noise information is introduced in the embodiment of the present application to be further strict based on the strict timing requirement, so as to effectively ensure the reliability of timing verification (e.g., full-speed test).
Optionally, the clock information may further include other parameters, such as at least one of path delay, cycle time, and the like. The path delay refers to signal delay of a clock path and a data path in the digital circuit module; the cycle time refers to a time length of each cycle of the periodic signal. That is, under the strict timing requirements, the path delay, cycle time, etc. according to which the stimulus signal is generated also need to be consistent with, or more strict than, those in the clock parameter data.
Fig. 4 is a schematic flow chart showing a timing testing method according to an embodiment of the present application.
In the embodiment of fig. 4, the flow of the timing testing method specifically includes:
step S401: and extracting time sequence information from the preset time sequence parameter data of the digital circuit module to be tested.
In a specific implementation, the digital circuit block corresponds to a design in a post-layout netlist. It should be noted that, since the integrated circuits are designed, simulated and verified by using EDA software, the digital circuit module may refer to a digital circuit module that is realized by related data simulation, and is not necessarily a real physical digital circuit module.
In some examples, the predetermined timing parameter data is stored in a predetermined timing parameter file corresponding to the digital circuit Module, such as various timing files including, but not limited to, one or more of setup time, hold time, cycle information, Composite Current Source Module (CCS) information, Effective Current Source Module (ECSM) information, power consumption information, and the like, in formats including, but not limited to, lib files,. sdf,. cdB files. The timing information may include various timing parameters, such as setup time, hold time (which may also include at least one of path delay and cycle time), etc., defined for generating stimuli, so as to generate corresponding timing stimulus signals for timing verification in subsequent steps.
In some examples, the manner in which timing information is extracted from the preset timing parameter file includes, but is not limited to, utilizing, for example, known EDA tools or written automation scripts, and the like.
Step S402: and generating a first time sequence excitation signal with strict time sequence requirements according to the time sequence information.
Specifically, the strict timing requirement refers to: the time sequence parameter used for generating the first time sequence excitation signal and obtained from the time sequence information is the same as or shorter than the corresponding time sequence parameter in the preset time sequence parameter data; the corresponding timing parameters include: setup time and hold time of the signal.
For example, if the setup time and the hold time recorded in the preset timing parameter file are t1 and t2, the setup time and the hold time for generating the first timing excitation signal are t1 and t2, respectively; alternatively, in other examples, a more strict timing requirement for the digital electrical module may be adopted, such as a reduction of a certain value or ratio, e.g., 5%, based on the establishment time t1 and the retention time t2 of the required timing information.
Step S403: and generating noise information according to the preset time sequence parameter data.
It should be noted that, the precedence relationship between step S402 and step S403 is not strictly limited, and may be selected according to actual situations.
In some examples, the preset timing parameter data includes, for example, Composite Current Source Module (CCS) information, Effective Current Source Module (ECSM) information, wherein CCS is a model expressing timing and noise based on a signal Current waveform, and ECSM is a model expressing timing and noise based on a signal voltage waveform, and a corresponding noise model may be established according to information related to noise, so as to generate noise information.
In a specific implementation, as shown in fig. 5, a specific step flow of step S402 is shown, which includes:
step S501: and extracting noise model parameters from the preset time sequence parameter data.
In particular implementations, the manner in which the noise model parameters are extracted includes, but is not limited to, utilizing known software tools such as automation or written automation scripts, and the like.
Taking the establishment of a CCS noise model or an ECSM noise model as an example, the noise model parameters may specifically include: 1) the static current (DC current) of the logic gate connected with the input port of the digital circuit module; 2) the transmission characteristic (Propagation) of the logic gate connected with the input port of the digital circuit module to noise; 3) the digital circuit block switches the edge characteristics (transitions) at the output of the logic gate to which the input port is connected.
Step S502: and establishing a noise model according to the noise model parameters.
For example, a corresponding CCS noise model or ECSM noise model is built based on the noise model parameters extracted by the above example.
It should be noted that the noise model is not limited to the CCS noise model or the ECSM noise model, and may be a static noise model, a dynamic noise model, a noise immune model, or the like.
Step S503: generating the noise information by the noise model.
The noise information may be equivalent to, for example, a level-jittered waveform signal or the like, and may delay or advance the superimposed signal.
After step S403 in fig. 1, the method further includes:
step S404: and enabling the noise information to act on the first time sequence excitation signal to obtain a second time sequence excitation signal, so as to be used for time sequence simulation of the digital circuit module to obtain a time sequence simulation result, and obtaining a time sequence test result of the digital circuit module to be tested according to the time sequence simulation result.
In some examples, in the simulation, when the noise information is added to the first timing driving signal, a delay or an advance of the first timing driving signal is generated to form a second timing driving signal, and the second timing driving signal can be applied to an input port of the digital circuit module, such as a clock input port and a data input port.
In a specific implementation, the manner in which the noise information acts on the digital circuit module includes at least one of:
1) introducing negative noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
2) introducing positive noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
3) introducing negative noise to a data path in the digital circuit module and introducing positive noise to a clock path in the digital circuit module;
4) positive noise is introduced to the data path in the digital circuit block and positive noise is introduced to the clock path in the digital circuit block.
For example, the clock path in the above cases is, for example, a path where a clock signal reaches a clock end of the digital circuit module from a clock end; the data path in the above cases is, for example, a path from the data output terminal of one logic gate circuit to the data input terminal of another logic gate circuit.
Cases 1) to 4) are four types of cases covering the influence of any noise on the setup time and the hold time of the signal, so that the influence of the introduced noise information on the time sequence of the digital circuit module can be explained, and the influence of other noises on the time sequence can be analogized in the same way.
The setup time of a signal is the difference of the data path delay minus the clock path delay, and the hold time is the difference of the clock path delay minus the data delay; moreover, noise information is superimposed on the first timing excitation signal, positive noise may generate a delay effect on the first timing excitation signal, and negative noise may generate an advance effect on the first timing excitation signal, for example, the positive noise acts on a rising edge of the first timing excitation signal, which may be referred to as fig. 2B and fig. 2D before; thus, for cases 1) and 4) above), the data path delay and the clock path delay are either increased or decreased simultaneously in cases 1) and 4) compared to the case where the input port applies or does not apply noise information; when noise information is not applied, the data path delay and the clock path delay are not changed, so that the difference between the establishment time and the retention time of the signal under the FullSpeed QA is small, and the sensitivity degree of a logic gate connected with a data port and a logic gate connected with a clock port to noise is influenced; and for case 2), the delay of the data path is increased and the delay of the clock path is decreased, so the setup time of the signal is increased and the hold time is decreased; for case 3), the delay of the data path is decreased and the delay of the clock path is increased, contrary to case 2), so that the setup time of the signal becomes smaller and the hold time becomes larger.
In some examples, the noise model is established and the noise information is introduced to simulate the noise effect of the digital circuit module in real environment, however, it is required to ensure that the output of the logic gate circuit at the input port of the digital circuit module is not mistakenly inverted due to the introduction of the noise, i.e. the introduced noise is ensured not to exceed the maximum tolerable noise of the input port. Optionally, the maximum tolerable noise may be extracted from preset timing parameter data, or may be obtained by simulating a logic gate connected to the input port.
Fig. 6 is a schematic diagram showing an implementation of introducing noise information into an input port of a digital circuit module to be tested according to an embodiment of the present application.
In fig. 6, an upstream module 601 transmits a signal X to an input port 621 of a digital circuit module 602 to be tested, and a resistor and a capacitor are exemplarily connected therebetween, and the digital circuit module 602 has a logic gate circuit 622 connected to the input port 601; in the timing verification, the transmitted signal X reaches the signal Y (i.e., the first excitation signal) at the input port 601 after passing through the resistor and capacitor circuit, and is superimposed on the signal Y at the input port 621 by outputting noise information through the established noise model 603 to form a signal Z (i.e., the second excitation signal).
The noise information may produce a delay or time advance for Y, denoted as Δ t; the principle of noise information generation Δ t is illustratively represented graphically in the noise model of fig. 6.
Further referring to fig. 7A and 7B, the principle of obtaining the signal Z by delaying and advancing the signal Y by Δ t according to the noise information is shown respectively. In fig. 7A, the solid line represents the ideal waveform of the signal Y at the input port, and the long dashed line represents the noise information (shown as a jitter that returns high from high to low) superimposed on the signal Y, resulting in a delay of Δ t for the ideal waveform of the signal at the input port, as shown by the short dashed line J in the figure; alternatively, in fig. 7B, the solid line represents the ideal waveform of the signal Y at the input port, and the long dashed line represents superimposed noise information (shown as a signal jitter that returns back low from low to high) that produces an advance of Δ t to the ideal waveform of the signal at the input port, shown as the short dashed line K.
It should be particularly noted that the noise information and the signal Y in fig. 7A and 7B are only schematic theoretical illustrations presented for the convenience of intuitively understanding the principle thereof, and in an actual scenario, the noise information and the signal Y do not need to be actually processed into a signal form of a medium waveform, and may be presented in an EDA software as a code form; for example, the noise information may be described by a code for its charge information to be converted into a voltage influence on the signal Y at the time of simulation to distort its signal waveform to form the signal Z.
In a specific example, the standard measurement indicator is obtained by: obtaining a loose excitation signal according to the first time sequence excitation signal or the second time sequence excitation signal, and obtaining a loose time sequence simulation result for the time sequence simulation of the digital circuit module; and obtaining the measurement index of the loose time sequence simulation result as the standard measurement index.
The loose excitation signal may be an excitation signal generated by multiplying the timing information generating the timing excitation signal by a certain factor, for example, the setup time and the hold time of the timing information are multiplied by 100 times to relax the timing constraint, so that the loose excitation signal does not cause timing violation and functional error of the digital circuit module due to timing problems; therefore, the measurement index corresponding to the loose excitation signal should be correct and can be used as the standard measurement index.
Optionally, the measurement index may be an index set according to a function and a performance of the digital circuit module, where the function index includes, for example, no function error; the performance indicators include no performance loss or performance loss below a threshold, such as a data processing or transmission speed threshold, a percentage threshold, and the like.
In connection with this example, as shown in fig. 8, step S404 may exemplarily include:
step S801: obtaining a first timing simulation result of the second timing excitation signal;
step S802: obtaining a second timing simulation result of the relaxed stimulus signal of the first timing stimulus signal or the second timing stimulus signal.
Since the loose excitation signal may be generated by amplifying the extracted timing information by a factor, in some examples, if the factor is large enough, the influence of the delay or advance of the noise information may be negligible by comparison, so that either the first timing excitation signal or the second timing excitation signal may be selected to generate the loose excitation signal; of course, if noise effects are considered, the second timing excitation signal may be selected to generate a corresponding relaxed excitation signal.
Step S803: and comparing the measurement index of the second time sequence simulation result serving as a standard measurement index with the measurement index of the first time sequence simulation result to judge whether the time sequence verification requirement is met.
In implementations, the requirements may include, for example, that the digital circuit block function needs to be correct, that performance needs not be lost or that the loss does not exceed a threshold, and so on.
Step S804: and if the measurement index of the first time sequence simulation result does not reach the time sequence verification requirement compared with the standard measurement index, judging that the time sequence verification is not passed.
Step S805: and if the measurement index of the first time sequence simulation result is compared with the standard measurement index and reaches the time sequence verification requirement, judging that the time sequence verification is passed.
In other examples, the standard measurement indicator may also be changed, for example, by using a measurement indicator corresponding to a post-simulation result of an RTL code or the like during the design of the digital circuit module, which is not limited to the above.
In the entire timing verification process, the timing test result may not pass, and processing is also required. For example, in the above example of fig. 4 or fig. 8, if the timing test result is failed, the step S401 may be returned to iteratively execute the steps of the timing test method until the timing test result is satisfied as passed.
As shown in fig. 9, a timing test system provided in the embodiment of the present application is shown. The implementation principle of the timing sequence testing system can refer to the embodiment of the timing sequence testing method, and repeated description is omitted here.
The timing test system 900 includes:
a timing information extraction module 901, configured to extract timing information from preset timing parameter data of a digital circuit module to be tested;
a signal generating module 902, configured to generate a first timing excitation signal with strict timing requirement according to the timing information;
a noise generation module 903, configured to generate noise information according to the preset timing parameter data;
the simulation detection module 904 is configured to enable the noise information to act on the first timing excitation signal to obtain a second timing excitation signal, so as to be used for timing simulation of the digital circuit module to obtain a timing simulation result, and obtain a timing test result for the digital circuit module to be tested according to the timing simulation result.
Optionally, the strict timing requirement refers to: the time sequence parameter used for generating the first time sequence excitation signal and obtained from the time sequence information is the same as or shorter than the corresponding time sequence parameter in the preset time sequence parameter data; the corresponding timing parameters include: setup time and hold time of the signal.
Optionally, the generating noise information according to the preset time sequence parameter data includes:
extracting noise model parameters from the preset time sequence parameter data;
establishing a noise model according to the noise model parameters;
generating the noise information by the noise model.
Optionally, the type of the noise model includes one of: a composite current source noise model, an effective current source noise model, a static noise model, a dynamic noise model, and a noise immunity model.
Optionally, the mode of applying the noise information to the digital circuit module includes at least one of:
introducing negative noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
introducing positive noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
introducing negative noise to a data path in the digital circuit module and introducing positive noise to a clock path in the digital circuit module;
positive noise is introduced to the data path in the digital circuit block and positive noise is introduced to the clock path in the digital circuit block.
Optionally, the making the noise information act on the first timing excitation signal to obtain a second timing excitation signal, so as to be used for timing simulation of the digital circuit module to obtain a timing simulation result, and obtain a timing test result of the digital circuit module to be tested according to the timing simulation result, including:
and comparing the measurement index corresponding to the time sequence simulation result with the standard measurement index to obtain a time sequence test result.
Optionally, the standard measurement indicator is obtained in a manner that:
obtaining a loose excitation signal according to the first time sequence excitation signal or the second time sequence excitation signal, and obtaining a loose time sequence simulation result for the time sequence simulation of the digital circuit module;
and obtaining the measurement index of the loose time sequence simulation result as the standard measurement index.
Optionally, the measurement indicator includes at least one of the following: a functional index; performance index.
Optionally, when the time sequence test result is not passed, the time sequence test system iteratively executes obtaining of the time sequence test result until the time sequence test result is passed.
Optionally, the digital circuit module corresponds to a design in the post-layout netlist.
Optionally, the preset time sequence parameter data is stored in a preset time sequence parameter file corresponding to the digital circuit module.
It should be noted that the timing test method, the timing test system, and the like in the above embodiments may be implemented by a part of program codes in the EDA software, or implemented by some plug-in loaded on the EDA software.
Fig. 10 is a schematic structural diagram of a computer device in the embodiment of the present application.
The computer device comprises a memory 1001 and a processor 1002, the memory 1001 having stored thereon a computer program operable on the processor 1002; the processor 1002 executes the computer program to perform the steps of the timing testing method described above, for example, in fig. 4, 5, and 8.
In some examples, the processor 1002 may be a combination that implements a computing function, such as a combination including one or more microprocessors, Digital Signal Processing (DSP), an ASIC, or the like; the memory 1001 may comprise a high-speed RAM memory and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory.
In some examples, the computer apparatus 1000 may be implemented in, for example, a server bank, a desktop, a laptop, a smartphone, a tablet, a smart band, a smart watch, or other smart devices, or a processing system formed by communicatively coupling such smart devices.
A computer-readable storage medium may also be provided in an embodiment of the present application, where the computer program is stored thereon, and when the computer program runs, the steps in the timing testing method described in the foregoing embodiments (for example, the embodiments in fig. 4, fig. 5, and fig. 8) are performed.
That is, the method flow in the embodiments of the present application (such as the embodiments of fig. 4, 5, 8) may be implemented as software or computer code that can be stored in a recording medium (such as a CDROM, RAM, floppy disk, hard disk, or magneto-optical disk), or as computer code that is originally stored in a remote recording medium or a non-transitory machine-readable medium and is to be stored in a local recording medium downloaded through a network, so that the method described herein can be stored in such software processing on a recording medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware (such as an ASIC or FPGA). It will be appreciated that the computer, processor, microprocessor controller or programmable hardware includes memory components (e.g., RAM, ROM, flash memory, etc.) that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the page table management method, dirty page information acquisition method described herein. Further, when a general-purpose computer accesses code for implementing the methods illustrated herein, execution of the code transforms the general-purpose computer into a special-purpose computer for performing the methods illustrated herein.
Compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:
compared with the prior art, the technical scheme of the embodiment of the application has the following beneficial effects:
on one hand, the scheme in the embodiment of the application introduces noise in the time sequence verification of the digital circuit module, so that the time sequence verification is more fit with the actual operation environment, and the verification result is more reliable.
On the other hand, the scheme in the embodiment of the application can further improve the reliability of the timing verification in some specific verification modes, for example, the influence of noise information is considered in a full-speed test, and the actual operation environment is more strictly attached on the basis of strict timing, so that the timing test result is more reliable.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs. The procedures or functions according to the present application are generated in whole or in part when the computer program instructions are loaded and executed on a computer. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer program may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium.
For example, the functional modules (or sub-modules) in the foregoing fig. 9 embodiment and the like may be implemented by software; or may be implemented by a combination of hardware and software, for example, a computer program executed by a processor in a computer device embodiment; alternatively, the present invention may be implemented by a hardware circuit.
In addition, functional modules in the embodiments of the present application may be integrated into one processing component, or each module may exist alone physically, or two or more modules are integrated into one component. The integrated components can be realized in a hardware form, and can also be realized in a software functional module form. The integrated components described above may also be stored in a computer-readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. The storage medium may be a read-only memory, a magnetic or optical disk, or the like.
For example, in the foregoing embodiment shown in fig. 9, each functional module (or sub-module) may be implemented by a single independent program, or may be implemented by different program segments in a program, and in some implementation scenarios, these functional modules may be located in one physical device, or may be located in different physical devices but communicatively coupled to each other.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example," or "some examples," etc., mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the application. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, various embodiments or examples and features of different embodiments or examples described in this specification can be combined and combined by one skilled in the art without contradiction.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present application, "a plurality" means two or more unless specifically limited otherwise.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process. And the scope of the preferred embodiments of the present application includes other implementations in which functions may be performed out of the order shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions.
For example, the order of the method steps in the embodiments of fig. 4, fig. 5, fig. 8, etc. described above may be changed in specific scenarios, and is not limited to the above description.
Although the embodiments of the present application are disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected by one skilled in the art without departing from the spirit and scope of the embodiments of the invention as defined by the appended claims.
Claims (15)
1. A timing test method, comprising:
extracting time sequence information from preset time sequence parameter data of a digital circuit module to be tested;
generating a first timing excitation signal with strict timing requirements according to the timing information;
generating noise information according to the preset time sequence parameter data;
and enabling the noise information to act on the first time sequence excitation signal to obtain a second time sequence excitation signal, so as to be used for time sequence simulation of the digital circuit module to obtain a time sequence simulation result, and obtaining a time sequence test result of the digital circuit module to be tested according to the time sequence simulation result.
2. The timing test method of claim 1, wherein the strict timing requirement refers to: the time sequence parameter used for generating the first time sequence excitation signal and obtained from the time sequence information is the same as or shorter than the corresponding time sequence parameter in the preset time sequence parameter data; the corresponding timing parameters include: setup time and hold time of the signal.
3. The timing test method of claim 2, wherein the corresponding timing parameters further comprise: at least one of path delay and cycle time.
4. The timing test method of claim 1, wherein the generating noise information according to the predetermined timing parameter data comprises:
extracting noise model parameters from the preset time sequence parameter data;
establishing a noise model according to the noise model parameters;
generating the noise information by the noise model.
5. The timing test method of claim 4, wherein the type of the noise model comprises one of: a composite current source noise model, an effective current source noise model, a static noise model, a dynamic noise model, and a noise immunity model.
6. The timing test method of claim 1 or 2, wherein the noise information is applied to the digital circuit block in a manner that includes at least one of:
introducing negative noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
introducing positive noise to a data path in the digital circuit module and introducing negative noise to a clock path in the digital circuit module;
introducing negative noise to a data path in the digital circuit module and introducing positive noise to a clock path in the digital circuit module;
positive noise is introduced to the data path in the digital circuit block and positive noise is introduced to the clock path in the digital circuit block.
7. The timing sequence test method according to claim 1, wherein the making the noise information act on the first timing excitation signal to obtain a second timing excitation signal for the timing sequence simulation of the digital circuit module to obtain a timing sequence simulation result, and obtaining the timing sequence test result of the digital circuit module to be tested according to the timing sequence simulation result, comprises:
and comparing the measurement index corresponding to the time sequence simulation result with the standard measurement index to obtain a time sequence test result.
8. The method of claim 7, wherein the obtaining of the standard measurement indicators comprises:
obtaining a loose excitation signal according to the first time sequence excitation signal or the second time sequence excitation signal, and obtaining a loose time sequence simulation result for the time sequence simulation of the digital circuit module;
and obtaining the measurement index of the loose time sequence simulation result as the standard measurement index.
9. The timing testing method of claim 7, wherein the measurement indicators comprise at least one of: a functional index; performance index.
10. The timing test method according to claim 1 or 7, further comprising:
and when the time sequence test result is passed, iteratively executing the steps of the time sequence test method until the time sequence test result is passed.
11. The timing test method of claim 1, wherein the digital circuit block corresponds to a design in a post-layout netlist.
12. The timing sequence test method of claim 1, wherein the predetermined timing sequence parameter data is stored in a predetermined timing sequence parameter file corresponding to the digital circuit module.
13. A timing test system, comprising:
the time sequence information extraction module is used for extracting time sequence information from preset time sequence parameter data of the digital circuit module to be tested;
the signal generating module is used for generating a first time sequence excitation signal with strict time sequence requirements according to the time sequence information;
the noise generation module is used for generating noise information according to the preset time sequence parameter data;
and the simulation detection module is used for enabling the noise information to act on the first time sequence excitation signal to obtain a second time sequence excitation signal, so as to be used for time sequence simulation of the digital circuit module to obtain a time sequence simulation result, and obtaining a time sequence test result of the digital circuit module to be tested according to the time sequence simulation result.
14. A computer arrangement comprising a memory and a processor, the memory having stored thereon a computer program executable by the processor, wherein the processor, when executing the computer program, performs the steps of the timing test method according to any one of claims 1 to 12.
15. A computer readable storage medium having stored thereon executable program code, wherein the executable program code when executed performs the timing test method of any of claims 1 to 12.
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