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ATE545952T1 - Verfahren zur reduktion der seedlayer-topographie in bicmos-prozessen - Google Patents

Verfahren zur reduktion der seedlayer-topographie in bicmos-prozessen

Info

Publication number
ATE545952T1
ATE545952T1 AT04801525T AT04801525T ATE545952T1 AT E545952 T1 ATE545952 T1 AT E545952T1 AT 04801525 T AT04801525 T AT 04801525T AT 04801525 T AT04801525 T AT 04801525T AT E545952 T1 ATE545952 T1 AT E545952T1
Authority
AT
Austria
Prior art keywords
silicon
seed layer
silicon nitride
stack
layer
Prior art date
Application number
AT04801525T
Other languages
English (en)
Inventor
Johannes J T M Donkers
Petrus Magnee
Eddy Kunnen
Francois Neuilly
Original Assignee
Nxp Bv
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nxp Bv filed Critical Nxp Bv
Application granted granted Critical
Publication of ATE545952T1 publication Critical patent/ATE545952T1/de

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34—Bipolar devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/021—Manufacture or treatment of heterojunction BJTs [HBT]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D10/00—Bipolar junction transistors [BJT]
    • H10D10/01—Manufacture or treatment
    • H10D10/051—Manufacture or treatment of vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Bipolar Transistors (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Element Separation (AREA)
  • Bipolar Integrated Circuits (AREA)
AT04801525T 2003-12-12 2004-12-09 Verfahren zur reduktion der seedlayer-topographie in bicmos-prozessen ATE545952T1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US52902803P 2003-12-12 2003-12-12
PCT/IB2004/052742 WO2005059989A1 (en) 2003-12-12 2004-12-09 Method to reduce seedlayer topography in bicmos process

Publications (1)

Publication Number Publication Date
ATE545952T1 true ATE545952T1 (de) 2012-03-15

Family

ID=34699930

Family Applications (1)

Application Number Title Priority Date Filing Date
AT04801525T ATE545952T1 (de) 2003-12-12 2004-12-09 Verfahren zur reduktion der seedlayer-topographie in bicmos-prozessen

Country Status (7)

Country Link
US (1) US7566919B2 (de)
EP (1) EP1695380B1 (de)
JP (1) JP4874119B2 (de)
KR (1) KR101060426B1 (de)
CN (1) CN100499043C (de)
AT (1) ATE545952T1 (de)
WO (1) WO2005059989A1 (de)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102117740B (zh) * 2010-01-06 2012-11-07 上海华虹Nec电子有限公司 改善锗硅或锗硅碳单晶体与多晶体交界面形貌的方法
CN105609415B (zh) * 2015-12-25 2018-04-03 中国科学院微电子研究所 一种刻蚀方法

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5731619A (en) 1996-05-22 1998-03-24 International Business Machines Corporation CMOS structure with FETS having isolated wells with merged depletions and methods of making same
JP4147605B2 (ja) * 1998-02-17 2008-09-10 沖電気工業株式会社 バイポーラトランジスタの製造方法
FR2778022B1 (fr) 1998-04-22 2001-07-13 France Telecom Transistor bibolaire vertical, en particulier a base a heterojonction sige, et procede de fabrication
JP2002524853A (ja) * 1998-08-31 2002-08-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ バイポーラトランジスタを備える半導体デバイスの製造方法
JP2002141476A (ja) * 2000-11-07 2002-05-17 Hitachi Ltd ＢｉＣＭＯＳ半導体集積回路装置およびその製造方法
DE10061199A1 (de) * 2000-12-08 2002-06-13 Ihp Gmbh Verfahren zur Herstellung von schnellen vertikalen npn-Bipolartransistoren und komplementären MOS-Transistoren auf einem Chip
JP2003257987A (ja) * 2002-02-28 2003-09-12 Sony Corp 半導体装置およびその製造方法
JP3719998B2 (ja) * 2002-04-01 2005-11-24 松下電器産業株式会社 半導体装置の製造方法
WO2003100845A1 (en) * 2002-05-29 2003-12-04 Koninklijke Philips Electronics N.V. Method of fabrication sige heterojunction bipolar transistor

Also Published As

Publication number Publication date
KR101060426B1 (ko) 2011-08-29
CN100499043C (zh) 2009-06-10
KR20060118541A (ko) 2006-11-23
WO2005059989A1 (en) 2005-06-30
EP1695380A1 (de) 2006-08-30
US7566919B2 (en) 2009-07-28
CN1890786A (zh) 2007-01-03
JP2007514314A (ja) 2007-05-31
EP1695380B1 (de) 2012-02-15
US20070111485A1 (en) 2007-05-17
JP4874119B2 (ja) 2012-02-15

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