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ATE504082T1 - Verfahren zur herstellung einer heteroepitaktischen mikrostruktur - Google Patents

Verfahren zur herstellung einer heteroepitaktischen mikrostruktur

Info

Publication number
ATE504082T1
ATE504082T1 AT03291284T AT03291284T ATE504082T1 AT E504082 T1 ATE504082 T1 AT E504082T1 AT 03291284 T AT03291284 T AT 03291284T AT 03291284 T AT03291284 T AT 03291284T AT E504082 T1 ATE504082 T1 AT E504082T1
Authority
AT
Austria
Prior art keywords
microstructure
heteroepitactic
producing
carrier structure
epitaxial
Prior art date
Application number
AT03291284T
Other languages
English (en)
Inventor
Bruce Faure
Fabrice Letertre
Original Assignee
Soitec Silicon On Insulator
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Soitec Silicon On Insulator filed Critical Soitec Silicon On Insulator
Application granted granted Critical
Publication of ATE504082T1 publication Critical patent/ATE504082T1/de

Links

Classifications

    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B25/00—Single-crystal growth by chemical reaction of reactive gases, e.g. chemical vapour-deposition growth
    • C30B25/02—Epitaxial-layer growth
    • C30B25/18—Epitaxial-layer growth characterised by the substrate
    • C30B25/183—Epitaxial-layer growth characterised by the substrate being provided with a buffer layer, e.g. a lattice matching layer
    • C—CHEMISTRY; METALLURGY
    • C30—CRYSTAL GROWTH
    • C30B—SINGLE-CRYSTAL GROWTH; UNIDIRECTIONAL SOLIDIFICATION OF EUTECTIC MATERIAL OR UNIDIRECTIONAL DEMIXING OF EUTECTOID MATERIAL; REFINING BY ZONE-MELTING OF MATERIAL; PRODUCTION OF A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; SINGLE CRYSTALS OR HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; AFTER-TREATMENT OF SINGLE CRYSTALS OR A HOMOGENEOUS POLYCRYSTALLINE MATERIAL WITH DEFINED STRUCTURE; APPARATUS THEREFOR
    • C30B33/00—After-treatment of single crystals or homogeneous polycrystalline material with defined structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT03291284T 2003-05-27 2003-05-27 Verfahren zur herstellung einer heteroepitaktischen mikrostruktur ATE504082T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP03291284A EP1482549B1 (de) 2003-05-27 2003-05-27 Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur

Publications (1)

Publication Number Publication Date
ATE504082T1 true ATE504082T1 (de) 2011-04-15

Family

ID=33104212

Family Applications (1)

Application Number Title Priority Date Filing Date
AT03291284T ATE504082T1 (de) 2003-05-27 2003-05-27 Verfahren zur herstellung einer heteroepitaktischen mikrostruktur

Country Status (5)

Country Link
US (3) US6946317B2 (de)
EP (1) EP1482549B1 (de)
JP (1) JP2005047792A (de)
AT (1) ATE504082T1 (de)
DE (1) DE60336543D1 (de)

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WO2011146015A1 (en) 2010-05-18 2011-11-24 Agency For Science, Technology And Research Method of forming a light emitting diode structure and a light emitting diode structure
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US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
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FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
JP2013089741A (ja) * 2011-10-18 2013-05-13 Renesas Electronics Corp 半導体装置、半導体基板、半導体装置の製造方法、及び半導体基板の製造方法
FR3079533B1 (fr) * 2018-03-28 2021-04-09 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau lno et substrat pour croissance par epitaxie d'une couche monocristalline de materiau lno
FR3079532B1 (fr) * 2018-03-28 2022-03-25 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau ain et substrat pour croissance par epitaxie d'une couche monocristalline de materiau ain
FR3079531B1 (fr) * 2018-03-28 2022-03-18 Soitec Silicon On Insulator Procede de fabrication d'une couche monocristalline de materiau pzt et substrat pour croissance par epitaxie d'une couche monocristalline de materiau pzt
CN113223928B (zh) * 2021-04-16 2024-01-12 西安电子科技大学 一种基于转移键合的氧化镓外延生长方法
CN113658849B (zh) * 2021-07-06 2025-02-21 华为技术有限公司 复合衬底及其制备方法、半导体器件、电子设备

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FR2817395B1 (fr) * 2000-11-27 2003-10-31 Soitec Silicon On Insulator Procede de fabrication d'un substrat notamment pour l'optique, l'electronique ou l'optoelectronique et substrat obtenu par ce procede
EP1482549B1 (de) * 2003-05-27 2011-03-30 S.O.I. Tec Silicon on Insulator Technologies S.A. Verfahren zur Herstellung einer heteroepitaktischen Mikrostruktur
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Also Published As

Publication number Publication date
JP2005047792A (ja) 2005-02-24
US20080210975A1 (en) 2008-09-04
US7646038B2 (en) 2010-01-12
US20050266626A1 (en) 2005-12-01
US7288430B2 (en) 2007-10-30
EP1482549A1 (de) 2004-12-01
US20040241975A1 (en) 2004-12-02
DE60336543D1 (de) 2011-05-12
US6946317B2 (en) 2005-09-20
EP1482549B1 (de) 2011-03-30

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