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ATE263429T1 - Verfahren zur herstellung eines halbleitergegenstands - Google Patents

Verfahren zur herstellung eines halbleitergegenstands

Info

Publication number
ATE263429T1
ATE263429T1 AT97309195T AT97309195T ATE263429T1 AT E263429 T1 ATE263429 T1 AT E263429T1 AT 97309195 T AT97309195 T AT 97309195T AT 97309195 T AT97309195 T AT 97309195T AT E263429 T1 ATE263429 T1 AT E263429T1
Authority
AT
Austria
Prior art keywords
image
substrate
porous silicon
silicon layer
forming
Prior art date
Application number
AT97309195T
Other languages
English (en)
Inventor
Kiyofumi Sakaguchi
Takao Yonehara
Original Assignee
Canon Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Canon Kk filed Critical Canon Kk
Application granted granted Critical
Publication of ATE263429T1 publication Critical patent/ATE263429T1/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76259—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along a porous layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/96—Porous semiconductor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/977—Thinning or removal of substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Bipolar Transistors (AREA)
  • Mechanical Treatment Of Semiconductor (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
AT97309195T 1996-11-15 1997-11-14 Verfahren zur herstellung eines halbleitergegenstands ATE263429T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP30454096 1996-11-15

Publications (1)

Publication Number Publication Date
ATE263429T1 true ATE263429T1 (de) 2004-04-15

Family

ID=17934239

Family Applications (1)

Application Number Title Priority Date Filing Date
AT97309195T ATE263429T1 (de) 1996-11-15 1997-11-14 Verfahren zur herstellung eines halbleitergegenstands

Country Status (11)

Country Link
US (1) US6100165A (de)
EP (1) EP0843345B1 (de)
KR (1) KR100282111B1 (de)
CN (1) CN1123915C (de)
AT (1) ATE263429T1 (de)
AU (1) AU745460B2 (de)
CA (1) CA2221245C (de)
DE (1) DE69728355T2 (de)
MY (1) MY115115A (de)
SG (1) SG55413A1 (de)
TW (1) TW373330B (de)

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JP4343295B2 (ja) * 1998-11-06 2009-10-14 キヤノン株式会社 試料の処理システム
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TW484184B (en) 1998-11-06 2002-04-21 Canon Kk Sample separating apparatus and method, and substrate manufacturing method
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FR2834820B1 (fr) 2002-01-16 2005-03-18 Procede de clivage de couches d'une tranche de materiau
JP2004103600A (ja) * 2002-09-04 2004-04-02 Canon Inc 基板及びその製造方法
EP1396883A3 (de) * 2002-09-04 2005-11-30 Canon Kabushiki Kaisha Substrat und Herstellungsverfahren dafür
JP2004103855A (ja) * 2002-09-10 2004-04-02 Canon Inc 基板及びその製造方法
JP2004103946A (ja) * 2002-09-11 2004-04-02 Canon Inc 基板及びその製造方法
JP2004335662A (ja) * 2003-05-06 2004-11-25 Canon Inc 部材及び部材の製造方法
FR2858715B1 (fr) * 2003-08-04 2005-12-30 Soitec Silicon On Insulator Procede de detachement de couche de semiconducteur
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US20070111468A1 (en) * 2005-07-19 2007-05-17 The Regents Of The University Of California Method for fabricating dislocation-free stressed thin films
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CA2740363A1 (en) * 2009-02-04 2010-08-12 Heliovolt Corporation Method of forming an indium-containing transparent conductive oxide film, metal targets used in the method and photovoltaic devices utilizing said films
KR20130122693A (ko) * 2009-06-05 2013-11-07 헬리오볼트 코오퍼레이션 비-접촉 압력 용기를 통해 박막 혹은 복합층을 합성하는 프로세스
US8256621B2 (en) * 2009-09-11 2012-09-04 Pro-Pak Industries, Inc. Load tray and method for unitizing a palletized load
US8021641B2 (en) * 2010-02-04 2011-09-20 Alliance For Sustainable Energy, Llc Methods of making copper selenium precursor compositions with a targeted copper selenide content and precursor compositions and thin films resulting therefrom
WO2011146115A1 (en) 2010-05-21 2011-11-24 Heliovolt Corporation Liquid precursor for deposition of copper selenide and method of preparing the same
WO2012023973A2 (en) 2010-08-16 2012-02-23 Heliovolt Corporation Liquid precursor for deposition of indium selenide and method of preparing the same
CN102157618A (zh) * 2011-01-30 2011-08-17 中国科学院宁波材料技术与工程研究所 一种低成本晶体硅太阳能电池的扩散方法
US9105797B2 (en) 2012-05-31 2015-08-11 Alliance For Sustainable Energy, Llc Liquid precursor inks for deposition of In—Se, Ga—Se and In—Ga—Se
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Also Published As

Publication number Publication date
KR19980042474A (ko) 1998-08-17
MY115115A (en) 2003-03-31
DE69728355T2 (de) 2004-09-09
AU745460B2 (en) 2002-03-21
CA2221245A1 (en) 1998-05-15
CN1123915C (zh) 2003-10-08
EP0843345A3 (de) 1998-07-08
SG55413A1 (en) 1998-12-21
CA2221245C (en) 2002-02-19
US6100165A (en) 2000-08-08
CN1188981A (zh) 1998-07-29
KR100282111B1 (ko) 2001-02-15
TW373330B (en) 1999-11-01
EP0843345B1 (de) 2004-03-31
EP0843345A2 (de) 1998-05-20
DE69728355D1 (de) 2004-05-06
AU4517397A (en) 1998-05-21

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Legal Events

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RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties