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AR010217A1 - Sistema de memoria - Google Patents

Sistema de memoria

Info

Publication number
AR010217A1
AR010217A1 ARP970103951A ARP970103951A AR010217A1 AR 010217 A1 AR010217 A1 AR 010217A1 AR P970103951 A ARP970103951 A AR P970103951A AR P970103951 A ARP970103951 A AR P970103951A AR 010217 A1 AR010217 A1 AR 010217A1
Authority
AR
Argentina
Prior art keywords
memory system
memory
Prior art date
Application number
ARP970103951A
Other languages
English (en)
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of AR010217A1 publication Critical patent/AR010217A1/es

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1016—Error in accessing a memory location, i.e. addressing error
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
    • G06F11/1028—Adjacent errors, e.g. error in n-bit (n>1) wide storage units, i.e. package error
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11B—INFORMATION STORAGE BASED ON RELATIVE MOVEMENT BETWEEN RECORD CARRIER AND TRANSDUCER
    • G11B20/00—Signal processing not specific to the method of recording or reproducing; Circuits therefor
    • G11B20/10—Digital recording or reproducing
    • G11B20/18—Error detection or correction; Testing, e.g. of drop-outs
    • G11B20/1833—Error detection or correction; Testing, e.g. of drop-outs by adding special lists or symbols to the coded information

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Quality & Reliability (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
ARP970103951A 1996-08-30 1997-08-29 Sistema de memoria AR010217A1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE19635237A DE19635237A1 (de) 1996-08-30 1996-08-30 Speichersystem

Publications (1)

Publication Number Publication Date
AR010217A1 true AR010217A1 (es) 2000-06-07

Family

ID=7804212

Family Applications (1)

Application Number Title Priority Date Filing Date
ARP970103951A AR010217A1 (es) 1996-08-30 1997-08-29 Sistema de memoria

Country Status (6)

Country Link
US (1) US6539504B1 (es)
EP (1) EP0922251B1 (es)
JP (1) JP2000517080A (es)
AR (1) AR010217A1 (es)
DE (2) DE19635237A1 (es)
WO (1) WO1998009216A1 (es)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6981091B2 (en) * 2001-10-25 2005-12-27 Xilinx,Inc. Using transfer bits during data transfer from non-volatile to volatile memories
US7927313B2 (en) * 2004-05-27 2011-04-19 Baxter International Inc. Medical device configuration based on recognition of identification information
US8961461B2 (en) 2004-05-27 2015-02-24 Baxter International Inc. Multi-state alarm system for a medical pump
US20050277873A1 (en) * 2004-05-27 2005-12-15 Janice Stewart Identification information recognition system for a medical device
US7203890B1 (en) 2004-06-16 2007-04-10 Azul Systems, Inc. Address error detection by merging a polynomial-based CRC code of address bits with two nibbles of data or data ECC bits
US11907559B1 (en) 2022-08-09 2024-02-20 Winbond Electronics Corporation Physically secure memory partitioning

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3528902C2 (de) * 1984-12-13 1994-06-09 Siemens Ag Durch einen EDC-Code gesichertes Speichersystem
US5043990A (en) * 1987-12-04 1991-08-27 Hitachi, Ltd. Semiconductor integrated circuit device
ATE132986T1 (de) * 1988-08-02 1996-01-15 Siemens Ag Verfahren zur fehlersicherung in speichersystemen von datenverarbeitungsanlagen, insbesondere fernsprechvermittlungsanlagen
US4993028A (en) * 1988-09-07 1991-02-12 Thinking Machines Corporation Error detection and correction coding
US5872780A (en) * 1992-05-21 1999-02-16 Alcatel Network Systems, Inc. Sonet data transfer protocol between facility interfaces and cross-connect
US5379415A (en) * 1992-09-29 1995-01-03 Zitel Corporation Fault tolerant memory system
KR960000681B1 (ko) * 1992-11-23 1996-01-11 삼성전자주식회사 반도체메모리장치 및 그 메모리쎌 어레이 배열방법
US5907717A (en) * 1996-02-23 1999-05-25 Lsi Logic Corporation Cross-connected memory system for allocating pool buffers in each frame buffer and providing addresses thereof

Also Published As

Publication number Publication date
DE59701775D1 (de) 2000-06-29
WO1998009216A1 (de) 1998-03-05
US6539504B1 (en) 2003-03-25
DE19635237A1 (de) 1998-03-05
JP2000517080A (ja) 2000-12-19
EP0922251B1 (de) 2000-05-24
EP0922251A1 (de) 1999-06-16

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