- Leibniz-Rechenzentrum der Bayerischen Akademie der Wissenschaften
Boltzmannstr. 1
D-85748 Garching bei Muenchen
Volker Weinberg
Leibniz Supercomputing Centre, High Performance Systems Division, Department Member
- Volker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre... moreVolker Weinberg studied physics at the Ludwig Maximilian University of Munich and later worked at the research centre DESY. He received his PhD from the Free University of Berlin for his studies in the field of lattice QCD. Since 2008 he is working in the HPC group at the Leibniz Supercomputing Centre and is responsible for education and training at LRZ, new programming languages and accelerators. As a lecturer he has provided many courses about basic and advanced OpenMP and MPI programming, Intel manycore programming and optimization, GPU programming using OpenACC/OpenMP and Mathematica. Within PRACE, the Partnership for Advanced Computing in Europe, he is coordinating PRACE training at LRZ and is currently also involved as leader of the workpackage WP5 "HPC Planning and Commissioning". He is a member of the PRACE-6IP Technical Board and LRZ representative in the OpenMP Architecture Review Board (ARB). Furthermore, he is leading the workpackage "Education and Training" within GCS, the Gauss Centre for Supercomputing, which combines the three national supercomputing centres High Performance Computing Center Stuttgart (HLRS), Jülich Supercomputing Centre (JSC), and Leibniz Supercomputing Centre (LRZ) into Germany’s foremost supercomputing institution. Volker is one of 4 elected spokespersons of the scientific employees of the Bavarian Academy of Sciences and Humanities.edit
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This book presents the latest findings and ongoing research in the field of environmental informatics. It addresses a wide range of cross-cutting activities, such as efficient computing, virtual reality, disruption management, big data,... more
This book presents the latest findings and ongoing research in the field of environmental informatics. It addresses a wide range of cross-cutting activities, such as efficient computing, virtual reality, disruption management, big data, open science and the internet of things, and showcases how these green information & communication technologies (ICT) can be used to effectively address environmental and societal challenges. Presenting a selection of extended contributions to the 32nd edition of the International Conference EnviroInfo 2018, at the Leibniz Supercomputing Centre in Garching near Munich, it is essential reading for anyone looking to expand their expertise in the area.
This book presents the latest findings and ongoing research in the field of environmental informatics. It addresses a wide range of cross-cutting activities such as recent advances in environmental informatics, Internet of Things... more
This book presents the latest findings and ongoing research in the field of environmental informatics. It addresses a wide range of cross-cutting activities such as recent advances in environmental informatics, Internet of Things technologies, challenges in ICT-technologies, disaster management, energy aware software-engineering and development, environmental health informatics, environmental information systems, machine learning, open science and sustainable mobility. The book contains selected short and work in progress papers of the 32nd International Conference EnviroInfo 2018 at the Leibniz Supercomputing Centre of the Bavarian Academy of Sciences and Humanities (LRZ) in Garching near Munich.
This Best Practice Guide written from scratch provides information about Intel's Haswell/Broadwell architecture in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from... more
This Best Practice Guide written from scratch provides information about Intel's Haswell/Broadwell architecture in order to enable programmers to achieve good performance of their applications. The guide covers a wide range of topics from the description and comparison of the hardware of the Haswell/Broadwell processor, through information about the compiler usage as well as information about porting programs up to tools and strategies how to analyse and improve the performance of applications. With the introduction of extra vector instructions with these processors (fused multiply add etc.) stronger focus is placed on vectorisation. In the tuning context several of the tuning tools provided by Intel are demonstrated and examples are given on how to use command line tools to collect data in batch mode. Furthermore, the guide provides information about the following European Intel Haswell/Broadwell based European systems: Hazel Hen @ HLRS, Germany, Minotauro @ BSC, Spain, Salomon @ IT4Innovations, Czech Republic, SuperMUC Phase 2 @ LRZ, Germany.
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This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs). GPUs were originally developed for computer gaming and other graphical tasks, but for many years have been exploited for general purpose... more
This Best Practice Guide describes general purpose computation on Graphics Processing Units (GPUs). GPUs were originally developed for computer gaming and other graphical tasks, but for many years have been exploited for general purpose computing across a number of areas. They offer advantages over traditional CPUs because they have greater computational capability and use high-bandwidth memory systems (with memory bandwidth being the main bottleneck for many scientific applications). The guide includes information on how to get started with programming GPUs, which cannot be used in isolation but only as "accelerators" in conjunction with CPUs, and how to get good performance. Focus is given to NVIDIA GPUs, which are most widespread today. The GPGPU Best Practice Guide is based on the PRACE-2IP GPGPU Best Practice Mini-Guide. The following new topics were added: GPU architecture especially highlighting new features of NVIDIA Pascal, OpenCL Programming, OpenMP 4.x Offloading. Several existing sections have been updated to reflect recent changes.
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This Best Practice Guide provides information about Intel’s MIC architecture and programming models for the first generation Intel® Xeon Phi™ coprocessor named Knights Corner (KNC) in order to enable programmers to achieve good... more
This Best Practice Guide provides information about Intel’s MIC architecture and programming models for the first generation Intel® Xeon Phi™ coprocessor named Knights Corner (KNC) in order to enable programmers to achieve good performance out of their applications. The guide covers a wide range of topics from the description of the hardware of the Intel® Xeon Phi™ coprocessor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyse and improve the performance of applications. The guide was created based on the PRACE-3IP Intel® Xeon Phi™ Best Practice Guide. New is the inclusion of information about European Intel® Xeon Phi™ based systems. The following systems are now described: •Avitohol @ IICT-BAS, Bulgary, MareNostrum @ BSC, Spain, Salomon @ IT4Innovations, Czech Republic, SuperMIC @ LRZ, Germany. Furthermore, the following new sections are included: OpenMP 4.x Offloading, OpenCL, Intel Cilk Plus / MYO, Information about some selected applications ported to Intel® Xeon Phi™, Benchmark results using e.g. the PRACE Accelerator Benchmark Suite. Several existing sections have been updated to reflect recent changes.
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This best practice guide provides information about Intel's MIC architecture and programming models for the Intel Xeon Phi coprocessor in order to enable programmers to achieve good performance of their pplications. The guide covers a... more
This best practice guide provides information about Intel's MIC architecture and programming models for the Intel Xeon Phi coprocessor in order to enable programmers to achieve good performance of their pplications. The guide covers a wide range of topics from the description of the hardware of the Intel Xeon Phi coprocessor through information about the basic programming models as well as information about porting programs up to tools and strategies how to analyze and improve the performance of applications.
This best practice guide provides information about SuperMUC in order to enable users of the system to achieve good performance of their applications. The guide covers a wide range of topics from the detailed description of the hardware... more
This best practice guide provides information about SuperMUC in order to enable users of the system to achieve good performance of their applications. The guide covers a wide range of topics from the detailed description of the hardware through information about the basic production environment including how to login and the accounting procedure as well as information about porting and submitting jobs, up to tools and strategies on how to analyze and improve the performance of applications. The guide includes contributions from LRZ, Nikos Anastopoulos (NTUA/GRNET) and Petri Nikunen (CSC).
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As code optimisation techniques are getting more and more important in HPC, LRZ @ GCS as one of the six European PRACE Advanced Training Centres (PATC) has extended its curriculum by a new PATC course " HPC code optimisation workshop " ,... more
As code optimisation techniques are getting more and more important in HPC, LRZ @ GCS as one of the six European PRACE Advanced Training Centres (PATC) has extended its curriculum by a new PATC course " HPC code optimisation workshop " , which took place at LRZ on May 4, 2017 for the first time.
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For the fourth time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations... more
For the fourth time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations in the field of environmental sciences. The Czech-Bavarian Competence Centre was established in 2016 by the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of the Technical University of Munich (TUM) and the IT4Innovations National Supercomputing Centre of the Czech Republic to foster the Czech-German collaboration in high performance computing. One of the main objectives of the Competence Centre is to organise a series of Intel Xeon Phi specific technical workshops combined with scientific symposia on topics like optimisation of simulation codes in environmental science.
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The Leibniz Supercomputing Centre publishes in this booklet the complete material of the Intel MIC programming workshop that took place at LRZ on June 26 – 28, 2017. The workshop discussed Intel’s Many Integrated Core (MIC) architecture... more
The Leibniz Supercomputing Centre publishes in this booklet the complete material of the Intel MIC programming workshop that took place at LRZ on June 26 – 28, 2017. The workshop discussed Intel’s Many Integrated Core (MIC) architecture and various programming models for Intel Xeon Phi co-/processors. The workshop covered a wide range of topics from the description of the hardware of the Intel Xeon Phi co-/processors through information about the basic programming models as well as information about vectorisation and MCDRAM usage up to tools and strategies how to analyse and improve the performance of applications. The workshop mainly concentrated on techniques relevant for Knights Landing (KNL) based systems. During a plenary session on the last day 8 invited speakers from IPCC@LRZ, IPCC@TUM, IPCC@IT4Innovations, Intel, RRZE, the University of Regensburg, IPP and MPCDF talked about Intel Xeon Phi experience and best practice recommendations. Hands-on sessions were done on the Knights Corner (KNC) based system SuperMIC and two KNL test systems at LRZ.
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For the third time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations... more
For the third time the Czech-Bavarian Competence Centre for Supercomputing Applications, CzeBaCCA, has organised a technical Intel Many Integrated Core (MIC) programming workshop combined with a scientific workshop about HPC simulations in the field of geo- and environmental sciences. The Czech-Bavarian Competence Centre was established in 2016 by the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of the Technical University of Munich (TUM) and the IT4Innovations National Supercomputing Centre of the Czech Republic to foster the Czech-German collaboration in high performance computing. One of the main objectives of the Competence Centre is to trigger new collaborations between Germans and Czech via scientific workshops and many-core architecture specific technical trainings.
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To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of TUM and the National Supercomputing Centre of the Czech Republic, IT4Innovations, recently... more
To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of TUM and the National Supercomputing Centre of the Czech Republic, IT4Innovations, recently joined forces and established the Czech-Bavarian Competence Centre for Supercomputing Applications (CzeBaCCA). Besides their joint research program around simulation software and tools for Salomon, one of the main objectives of the new Competence Centre is to organise a series of scientific workshops and Intel MIC (Many Integrated Core) architecture specific trainings. The article reports on the second series of workshops that took place at LRZ in Garching in June 2016 and combined a three-day “Intel MIC Programming Workshop” (June 27 – 29, 2016) with a three-day scientific workshop on “High Performance Computing for Water Related Hazards” (June 29 – July 1, 2016).
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On 18-22 April 2016 the Leibniz Supercomputing Centre hosted the 21st VI-HPS Tuning Workshop in a very fruitful cooperation with the Jülich Supercomputing Centre (JSC) and the VI-HPS consortium. This series of tuning workshops gives an... more
On 18-22 April 2016 the Leibniz Supercomputing Centre hosted the 21st VI-HPS Tuning Workshop in a very fruitful cooperation with the Jülich Supercomputing Centre (JSC) and the VI-HPS consortium. This series of tuning workshops gives an overview of the VI-HPS performance analysis and tuning tools suite, explains the functionality of individual tools and how to use them effectively, and offers hands-on experience and expert assistance using these tools on participants' own applications.
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Most HPC systems are clusters of shared memory nodes. These SMP nodes can be small multi-core CPUs up to large many-core CPUs. Parallel programming may combine the distributed memory parallelisation on the node interconnect (e.g., using... more
Most HPC systems are clusters of shared memory nodes. These SMP nodes can be small multi-core CPUs up to large many-core CPUs. Parallel programming may combine the distributed memory parallelisation on the node interconnect (e.g., using MPI) with the shared memory parallelisation inside of each node (e.g., using OpenMP or MPI-3.0 shared memory). As such hybrid programming techniques are getting more and more important in HPC, GCS as one of the 6 European PRACE Advanced Training Centres (PATC) has extended its curriculum by a new PATC course on hybrid programming techniques, which took place at LRZ on January 14, 2016 for the first time.
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To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of TUM and the National Supercomputing Centre of the Czech Republic, IT4Innovations, recently... more
To foster the Czech-German collaboration in high performance computing, the Leibniz Supercomputing Centre (LRZ), the Department of Informatics of TUM and the National Supercomputing Centre of the Czech Republic, IT4Innovations, recently joined forces and established the Czech-Bavarian Competence Centre for Supercomputing Applications (CzeBaCCA).
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With the ever-increasing energy demands and prices and the need for uninterrupted services, data centre operators must find solutions to increase energy efficiency and reduce costs. Running from October 2011 to June 2015, the aim of the... more
With the ever-increasing energy demands and prices and the need for uninterrupted services, data centre operators must find solutions to increase energy efficiency and reduce costs. Running from October 2011 to June 2015, the aim of the European project Mont-Blanc has been to address this issue by developing an approach to Exascale computing based on embedded power-efficient technology. The main goals of the project were to i) build an HPC prototype using currently available energy-efficient embedded technology, ii) design a Next Generation system to overcome the limitations of the built prototype and iii) port a set of representative Exascale applications to the system.
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Since the standards of parallel programming languages are becoming more and more complex and extensive, it can be hard to stay up to date with recent developments. LRZ has thus invited leading HPC experts to give updates of recent... more
Since the standards of parallel programming languages are becoming more and more complex and extensive, it can be hard to stay up to date with recent developments. LRZ has thus invited leading HPC experts to give updates of recent advances in parallel programming languages during a 1-day workshop on June 8 2015 at LRZ.
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We discuss a detailed strong and weak scaling analysis of PICCANTE, an open source, massively parallel, fully-relativistic Particle-In-Cell (PIC) code. PIC codes are widely used in plasma physics and astrophysics to study the cases where... more
We discuss a detailed strong and weak scaling analysis of PICCANTE, an open source, massively parallel, fully-relativistic Particle-In-Cell (PIC) code. PIC codes are widely used in plasma physics and astrophysics to study the cases where kinetic effects are relevant. PICCANTE is primarily developed to study laser-plasma interaction. Within a PRACE Preparatory Access Project, various revisions of different routines of the code have been analysed on the HPC systems JUQUEEN at J\"ulich Supercomputing Centre (JSC), Germany, and FERMI at CINECA, Italy, to improve the parallel scalability and the I/O performance of the application. The diagnostic tool Scalasca is used to filter out suboptimal routines. Different output strategies are discussed. The detailed strong and weak scaling behaviour of the improved code is presented in comparison with the original version of the code.
We discuss a detailed weak scaling analysis of GEM, a 3D MPI-parallelised gyrofluid code used in theoretical plasma physics at the Max Planck Institute of Plasma Physics, IPP at Garching b. M\"unchen, Germany. Within a PRACE Preparatory... more
We discuss a detailed weak scaling analysis of GEM, a 3D MPI-parallelised gyrofluid code used in theoretical plasma physics at the Max Planck Institute of Plasma Physics, IPP at Garching b. M\"unchen, Germany. Within a PRACE Preparatory Access Project various versions of the code have been analysed on the HPC systems SuperMUC at LRZ and JUQUEEN at J\"ulich Supercomputing Centre (JSC) to improve the parallel scalability of the application. The diagnostic tool Scalasca has been used to filter out suboptimal routines. The code uses the electromagnetic gyrofluid model which is a superset of magnetohydrodynamic and drift-Alfv\'en microturbulance and also includes several relevant kinetic processes. GEM can be used with different geometries depending on the targeted use case, and has been proven to show good scalability when the computational domain is distributed amongst two dimensions. Such a distribution allows grids with sufficient size to describe small scale tokamak devices. In order to enable simulation of very large tokamaks (such as the next generation nuclear fusion device ITER in Cadarache, France) the third dimension has been parallelised and weak scaling has been achieved for significantly larger grids.
As the complexity and size of challenges in science and engineering are continually increasing, it is highly important that applications are able to scale strongly to very large numbers of cores (>100,000 cores) to enable HPC systems... more
As the complexity and size of challenges in science and engineering are continually increasing, it is highly important that applications are able to scale strongly to very large numbers of cores (>100,000 cores) to enable HPC systems to be utilised efficiently. This paper presents results of strong scaling tests performed with an MPI only and a hybrid MPI + OpenMP version of the Lattice QCD application BQCD on the European Tier-0 system SuperMUC at LRZ.
With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. In particular GPGPUs have recently become very popular, however programming... more
With the rapidly growing demand for computing power new accelerator based architectures have entered the world of high performance computing since around 5 years. In particular GPGPUs have recently become very popular, however programming GPGPUs using programming languages like CUDA or OpenCL is cumbersome and error-prone. Trying to overcome these difficulties, Intel developed their own Many Integrated Core (MIC) architecture which can be programmed using standard parallel programming techniques like OpenMP and MPI. In the beginning of 2013, the first production-level cards named Intel Xeon Phi came on the market. LRZ has been considered by Intel as a leading research centre for evaluating coprocessors based on the MIC architecture since 2010 under strict NDA. Since the Intel Xeon Phi is now generally available, we can share our experience on programming Intel's new MIC architecture.
Intel Array Building Blocks is a high-level data-parallel programming environment designed to produce scalable and portable results on existing and upcoming multi- and many-core platforms. We have chosen several mathematical kernels - a... more
Intel Array Building Blocks is a high-level data-parallel programming environment designed to produce scalable and portable results on existing and upcoming multi- and many-core platforms. We have chosen several mathematical kernels - a dense matrix-matrix multiplication, a sparse matrix-vector multiplication, a 1-D complex FFT and a conjugate gradients solver - as synthetic benchmarks and representatives of scientific codes and ported them to ArBB. This whitepaper describes the ArBB ports and presents performance and scaling measurements on the Westmere-EX based system SuperMIG at LRZ in comparison with OpenMP and MKL.
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Knowledge of the derivative of the topological susceptibility at zero momentum is important for assessing the validity of the Witten-Veneziano formula for the eta' mass, and likewise for the resolution of the EMC proton spin problem.... more
Knowledge of the derivative of the topological susceptibility at zero momentum is important for assessing the validity of the Witten-Veneziano formula for the eta' mass, and likewise for the resolution of the EMC proton spin problem. We investigate the momentum dependence of the topological susceptibility and its derivative at zero momentum using overlap fermions in quenched lattice QCD simulations. We expose the role of the low-lying Dirac eigenmodes for the topological charge density, and find a negative value for the derivative. While the sign of the derivative is consistent with the QCD sum rule for pure Yang-Mills theory, the absolute value is overestimated if the contribution from higher eigenmodes is ignored.
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A detailed comparison is made between the topological structure of quenched QCD as revealed by the recently proposed over-improved stout-link smearing in conjunction with an improved gluonic definition of the topological density on one... more
A detailed comparison is made between the topological structure of quenched QCD as revealed by the recently proposed over-improved stout-link smearing in conjunction with an improved gluonic definition of the topological density on one hand and a similar analysis made possible by the overlap-fermionic topological charge density both with and without variable ultraviolet cutoff lambdacut. The matching is twofold, provided
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We present selected recent results of the QCDSF collaboration on the localization and dimensionality of low overlap eigenmodes and of the topological density in the quenched SU(3) vacuum. We discuss the correlations between the... more
We present selected recent results of the QCDSF collaboration on the localization and dimensionality of low overlap eigenmodes and of the topological density in the quenched SU(3) vacuum. We discuss the correlations between the topological structure revealed by overlap fermions without filtering and the confining monopole and P-vortex structure obtained in the Indirect Maximal Center Gauge.
Overlap fermions are particularly well suited to study the finite temperature dynamics of the chiral symmetry restoration transition of QCD, which might be just an analytic crossover. Using gauge field configurations on a 24^3x10 lattice... more
Overlap fermions are particularly well suited to study the finite temperature dynamics of the chiral symmetry restoration transition of QCD, which might be just an analytic crossover. Using gauge field configurations on a 24^3x10 lattice with N_f=2 flavours of dynamical Wilson-clover quarks generated by the DIK collaboration, we compute the lowest 50 eigenmodes of the overlap Dirac operator and try to locate the transition by fermionic means. We analyse the spectral density, local chirality and localisation properties of the low-lying modes and illustrate the changing topological and (anti-) selfdual structure of the underlying gauge fields across the transition.
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These are the proceedings of the workshop on " Lattice QCD, Chiral Perturbation Theory and Hadron Phenomenology " held at the European Centre for Theoretical Studies in Nuclear Physics and Related Areas from October 2 to 6, 2006. The... more
These are the proceedings of the workshop on " Lattice QCD, Chiral Perturbation Theory and Hadron Phenomenology " held at the European Centre for Theoretical Studies in Nuclear Physics and Related Areas from October 2 to 6, 2006. The workshop concentrated on bringing together researchers working in lattice QCD and chiral perturbation theory with the aim of improving our understanding how hadron properties can be calculated and analyzed from first principles. Included are a short contribution per talk.
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High Performance Computing (HPC) is experiencing vast amount of changes in the road towards Exascale computing capability. These changes stretch throughout different levels: from technology and architectures to use cases. In order to... more
High Performance Computing (HPC) is experiencing vast amount of changes in the road towards Exascale computing capability. These changes stretch throughout different levels: from technology and architectures to use cases. In order to attain the best performing HPC system, it is imperative that the underlying technology and architecture match the requirements of the current and emerging applications.
This document aims to provide an overview of these requirements by assessing the needs of user communities and of HPC centres in terms of technologies and architectures for next generation HPC systems evolving towards Exascale. For this purpose, surveys have been conducted among recently started Centres of Excellences (CoEs) in Europe for collecting the requirements from HPC user communities. A different survey has been distributed to all PRACE Tier-0/Tier-1 HPC sites to understand how these requirements differ from the current state of the art, to determine the requirements of HPC centres, and possibly motivate related prototyping efforts.
This document aims to provide an overview of these requirements by assessing the needs of user communities and of HPC centres in terms of technologies and architectures for next generation HPC systems evolving towards Exascale. For this purpose, surveys have been conducted among recently started Centres of Excellences (CoEs) in Europe for collecting the requirements from HPC user communities. A different survey has been distributed to all PRACE Tier-0/Tier-1 HPC sites to understand how these requirements differ from the current state of the art, to determine the requirements of HPC centres, and possibly motivate related prototyping efforts.
The Training Work Package (WP4) of the PRACE Fifth Implementation Phase (PRACE-5IP) project is responsible for the training activities of PRACE. In addition to the extensive programme of face-to-face training delivered by the PRACE... more
The Training Work Package (WP4) of the PRACE Fifth Implementation Phase (PRACE-5IP) project is responsible for the training activities of PRACE. In addition to the extensive programme of face-to-face training delivered by the PRACE Advanced Training Centres (PATCs) and PRACE Training Centres (PTCs), the training activities also include the On-demand training events, a series of online training offerings such as the Massive Open Online Courses (MOOCs), the training code repository (CodeVault) and the training portal. This deliverable is a report of all the PRACE-5IP training activities during the initial 15 months of the project.
PRACE-5IP continued the training activities of PRACE-4IP starting from February 2017. Between February 2017 and April 2018, the six PATCs delivered 103 courses, 290 course-days with 2,396 participants, while the four PTCs delivered 12 courses, 21 course-days with 351 participants. The feedback responses received have been overwhelmingly positive (8.5/10 average overall rating for PATC courses).
Similarly, the PRACE Seasonal Schools in PRACE-5IP have been carefully selected via a formal selection process. The Seasonal Schools scheduled for this reporting period, namely the Autumn School 2017 in Gdańsk, Poland and the Winter Seasonal School 2018 in Bratislava, Slovak Republic, attracted 39 attendees in total, and obtained high overall ratings.
In addition, WP4 continued the collaboration with the Centres of Excellence (CoEs) where a number of On-demand events were organised. Finally, WP4 co-organised the 2017 International Summer School on HPC Challenges in Computational Sciences in Boulder, Colorado, United States of America, from 25-30June 2017.
All forms of face-to-face and online training are complementary. They contribute to the success of the PRACE training programme, and should be continued in future PRACE HPC training activities. In accordance with the PRACE-5IP goals, the majority of training events also address industrial users, and motivate them by showing the importance and benefits of HPC for the practice.
PRACE-5IP continued the training activities of PRACE-4IP starting from February 2017. Between February 2017 and April 2018, the six PATCs delivered 103 courses, 290 course-days with 2,396 participants, while the four PTCs delivered 12 courses, 21 course-days with 351 participants. The feedback responses received have been overwhelmingly positive (8.5/10 average overall rating for PATC courses).
Similarly, the PRACE Seasonal Schools in PRACE-5IP have been carefully selected via a formal selection process. The Seasonal Schools scheduled for this reporting period, namely the Autumn School 2017 in Gdańsk, Poland and the Winter Seasonal School 2018 in Bratislava, Slovak Republic, attracted 39 attendees in total, and obtained high overall ratings.
In addition, WP4 continued the collaboration with the Centres of Excellence (CoEs) where a number of On-demand events were organised. Finally, WP4 co-organised the 2017 International Summer School on HPC Challenges in Computational Sciences in Boulder, Colorado, United States of America, from 25-30June 2017.
All forms of face-to-face and online training are complementary. They contribute to the success of the PRACE training programme, and should be continued in future PRACE HPC training activities. In accordance with the PRACE-5IP goals, the majority of training events also address industrial users, and motivate them by showing the importance and benefits of HPC for the practice.
The Work Package 7 ‘Application Enabling and Support’ provides applications enabling support for HPC applications codes that are important for European academic and/or industrial researchers to ensure that these applications can... more
The Work Package 7 ‘Application Enabling and Support’ provides applications enabling support for HPC applications codes that are important for European academic and/or industrial researchers to ensure that these applications can effectively exploit current and future PRACE systems. Applications are selected for enabling via calls such as PRACE Preparatory Access (for Tier-0 or Tier-1), or SHAPE (SME HPC Adoption Programme in Europe). This applications enabling activity uses the most promising tools, algorithms and standards for optimisation and parallel scaling that have recently been developed through research and experience in PRACE and other projects. Through the applications-enabling work, the Work Package 7 develops specific expertise on most – if not all – of the architectures which make up the European HPC system. Technical results obtained within this Work Package have been disseminated though many technical whitepapers freely available on the PRACE RI web site. In addition to this enabling work on existing systems, the Work Package also progresses the technical work needed to ensure that key applications are able to use future PRACE Exascale systems, and investigate the tools, languages and libraries needed to exploit future PRACE Exascale systems. One of the main objectives of the Work Package is to support European HPC research communities through the provision of Best Practice Guides, benchmarks, and example parallel codes. The successful series of Best Practice Guides has been initiated in PRACE-1IP and has been continuously extended since then. Topics for these Best Practice Guides include: optimal porting of applications (e.g., choice of numerical libraries and compiler options); architecture specific optimisation and scaling techniques; optimal system environment (e.g., tuneable system parameters, job placement and optimised system libraries); debugging tools, performance analysis tools and programming environment. This report describes the process which led to the Best Practice Guides and the structure of the guides.
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Task T7.1 “Enabling Applications Codes for PRACE Systems” in Work Package 7 (WP7) of PRACE-4IP aims to provide application enabling support for the HPC applications which are important for the European researchers and small and medium... more
Task T7.1 “Enabling Applications Codes for PRACE Systems” in Work Package 7 (WP7) of PRACE-4IP aims to provide application enabling support for the HPC applications which are important for the European researchers and small and medium enterprises to ensure the applications can effectively exploit HPC systems.
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Work Package 7 ‘Application Enabling and Support’ provides applications enabling support for HPC applications codes which are important for European researchers to ensure that these applications can effectively exploit multi-petaflop... more
Work Package 7 ‘Application Enabling and Support’ provides applications enabling support for HPC applications codes which are important for European researchers to ensure that these applications can effectively exploit multi-petaflop systems. Applications will be selected either via PRACE Preparatory Access or identified as addressing major socio-economic challenges with the advice of the PRACE Scientific Steering Committee. This applications enabling activity will use the most promising tools, algorithms and standards for optimisation and parallel scaling that have recently been developed through research and experience in PRACE and other projects. Through the applications-enabling work, WP7 develops specific expertise on most, if not all, of the architectures which make up the European HPC system. PRACE-1IP provided best practice guides on the PRACE Tier-0 systems that cover programming techniques, compilers, tools and libraries. PRACE-2IP supplemented these with best practice gui...
Work Package 7 ‘Scaling Applications for Tier-0 and Tier-1 Users’ provides medium-term petascaling and optimisation support for European HPC applications to ensure that they can make effective use of both Tier-0 and Tier-1 systems. Such... more
Work Package 7 ‘Scaling Applications for Tier-0 and Tier-1 Users’ provides medium-term petascaling and optimisation support for European HPC applications to ensure that they can make effective use of both Tier-0 and Tier-1 systems. Such applications-enabling projects typically last around six months and provide direct benefits to European researchers. Through the applications-enabling work, WP7 develops specific expertise on most, if not all, of the architectures which make up the top two tiers of the European HPC system. PRACE- 1IP provided best practice guides on the PRACE Tier-0 systems that cover programming techniques, compilers, tools and libraries. PRACE-2IP supplements these with best practice guides for the other architectures which are important at Tier-1 to allow European researchers to make efficient use of these systems. PRACE-2IP Task 7.3 is called ‘Best Practice Guides for Tier-1 Architectures’. The main goal of this task is to investigate the efficient use of HPC sys...
Talk about HPC training within GCS, the Gauss Centre for Supercomputing, which combines the three national supercomputing centres High Performance Computing Center Stuttgart (HLRS), Jülich Supercomputing Centre (JSC), and Leibniz... more
Talk about HPC training within GCS, the Gauss Centre for Supercomputing, which combines the three national supercomputing centres High Performance Computing Center Stuttgart (HLRS), Jülich Supercomputing Centre (JSC), and Leibniz Supercomputing Centre (LRZ) into Germany’s foremost supercomputing institution.
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These are the proceedings of the workshop on ``Lattice QCD, Chiral Perturbation Theory and Hadron Phenomenology'' held at the European Centre for Theoretical Studies in Nuclear Physics and Related Areas from October 2 to 6, 2006. The... more
These are the proceedings of the workshop on ``Lattice QCD, Chiral Perturbation Theory and Hadron Phenomenology'' held at the European Centre for Theoretical Studies in Nuclear Physics and Related Areas from October 2 to 6, 2006. The workshop concentrated on bringing together researchers working in lattice QCD and chiral perturbation theory with the aim of improving our understanding how hadron properties can be calculated and analyzed from first principles. Included are a short contribution per talk.