Abstract
Nanoscale FinFET being a popular solution for low power applications, has been adopted by several predominant semiconductor companies such as Samsung, Intel, and TSMCin place of MOSFET devices. In this paper, the electrical characteristics of n-FinFET and p-FinFETdevices have been investigated at low power supply. The enhanced on-current (ION = 46.8 µA), improved current ratio (ION/IOFF = 3.49 × 106) ratio and raised transconductance (gm = 78 µA) have been obtained. The diminished off current (IOFF = 4.71 pA), subthreshold swing (SS = 65 mV/dec) and drain induced barrier lowering (DIBL = 40 mV/V) have also been observed for simulated device. The reports of ITRS revealed that about 95% of the chip area is occupied by memory. Therefore, the nanoscaled FinFET based SRAM cell has been designed and simulated with TCAD with the aim of reducing power dissipation, area, cost, and improving stability. SRAM stability is one of the primary constraint of VLSI system. The dependencies of read static noise margin (RSNM) and write static noise margin (WSNM) on supply voltage and temperature have also been demonstrated for SRAM cells.
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Acknowledgements
The authors are grateful to MHRD, Govt. of India for sanctioning the grant for the purchase of software used for research work through TEQIP-III to Guru Nanak Dev Engineering College, Ludhiana. Authors would also like to extend gratitude to I. K. Gujral Punjab Technical University, Kapurthala for support in completion of this research work.
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Kaur, G., Gill, S.S., Rattan, M. (2021). Design and Performance Analysis of FinFET Based SRAM Cell Stability. In: Singh, H., Singh Cheema, P.P., Garg, P. (eds) Sustainable Development Through Engineering Innovations. Lecture Notes in Civil Engineering, vol 113. Springer, Singapore. https://doi.org/10.1007/978-981-15-9554-7_50
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DOI: https://doi.org/10.1007/978-981-15-9554-7_50
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