Abstract
Complementary metal-oxide-semiconductor (CMOS) device faces various unknown short channel effects (SCEs) such as subthreshold leakage and drain-induced barrier lowering (DIBL) in advanced technologies. This degrades the circuit’s performance, especially SRAM cell, owing to the high demand for large density. Fin-shaped field-effect transistor (FinFET) is one of the trending choices for memory designers, which can improve the stability and minimize the SCEs of the CMOS devices. In this study, different SRAM cell topologies are redesigned and re-simulated by using 7-nm FinFET devices, and then, their performance metrics including the stability, access time, and power are measured at a certain range of supply voltage (VDD) below the nominal value of 0.7 V. Moreover, the layout of these SRAM cells is designed and compared in which the ST12T cell consumes the maximum area due to having a higher count of transistors. Simulated results inferred that the ST11T cell offers the highest RSNM among all the SRAM cells, which can be explained with the use of read decoupling technique and cross-coupled Schmitt-trigger inverters. Moreover, the ST12T cell has the highest WSNM in comparison to other SRAM cells because this cell performs its write operation in fully differential form along with a power-gating write-assist technique. In the view of power consumption, the ST11T and ST12T cell offers the least dynamic and leakage power dissipation, respectively, because the former cell is single-ended bitcell with a low frequency and the latter one has stacked transistors in its cell core in which the path from power VDD to GND is long. An electrical quality metric (EQM) is utilized to assess the overall performance of these SRAM cells, which displays the superiority of the ST12T cell.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
Explore related subjects
Discover the latest articles, news and stories from top researchers in related subjects.Availability of Data and Material (Data Transparency)
The associated data will be made available on request.
Code Availability (Software Application or Custom Code)
The simulation work has been carried out using HSPICE software.
References
Abbasian E, Gholipour M, Izadinasab F (2021) Performance evaluation of GNRFET and TMDFET devices in static random access memory cells design, International Journal of Circuit Theory and Applications. https://doi.org/10.1002/cta.3108
Ahmad SA (2016) Single-ended Schmitt-trigger-based robust low-power SRAM cell. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pp 2634–2642
Ahmad S, M. K. (2017) Low leakage single bitline 9 t (sb9t) static random access memory. Microelectron J 62:1–11
Ansari M-K-K (2015) A near-threshold 7T SRAM cell with high write and read margins and low write time for sub-20 nm FinFET technologies. Integration 50:91–106
Birla S (2019) Variability aware FinFET SRAM cell with improved stability and power for low power applications. Circuit World 45:196–207
Chang L, Fried DM, Hergenrother J, Sleight JW, Dennard RH, Montoye RK, Sekaric L, McNab SJ, Topol AW, Adams CD, Guarini KW, Haensch W (2005) Stable SRAM cell design for the 32 nm node and beyond, in Symp. VLSI Technology Dig., pp 128-129
Cotofana S (n.d.) Emerging phenomena-dependent non-CMOS Nanoelectronic devices-what are they? 4th IEEE international conference on Nano/Micro engineered and molecular systems, IEEE-NEMS, Shenzhen, pp 5–8. China: IEEE
Ensan SS (2018) A robust and low-power near-threshold SRAM in 10-nm FinFET technology. Analog integrated circuits and signal processing, pp 497-506
Frank DJ-S (2001) Device scaling limits of Si MOSFETs and their application dependencies. Proceedings of the IEEE, pp 259-288
Gholipour AA (2020a) A variation-aware design for storage cells using Schottky-barrier-type GNRFETs. J Comput Electronic:987–1001
Gholipour EA (2020b) Design of a Schmitt-Trigger-Based 7T SRAM cell for variation resilient low-energy consumption and reliable internet of things applications. Int J Electron Commun 153899
Golipour EA (2021) Single-ended half-select disturb-free 11T static random access memory cell for reliable and low power applications. Int J Circuit Theory Applications 970-989
Goser KP (2004) Nanoelectronics and nanosystems: from transistors to molecular and quantum devices. Springer Science \& Business Media
Haron NZ (2008) Why is CMOS scaling coming to an END? 3rd international design and test workshop, pp 98-103. IEEE
He YA (2019) A half-select disturb-free 11T SRAM cell with built-in write/read-assist scheme for ultralow-voltage operations. IEEE Transactions on Very Large Scale Integration (VLSI) Systems 27:2344–2353
Jiao HA (2016) Low power and robust memory circuits with asymmetrical ground gating. Microelectron J 48:109–119
Kulkarni JP (2011) Ultralow-voltage process-variation-tolerant Schmitt-trigger-based SRAM design. IEEE transactions on very large scale integration (VLSI) systems, 319-332
Mahmoodi E (2020) Design space exploration of low-power flip-flops in FinFET technology. Integration 75:52–62
NIMO PTM Model. Accessed: Sep. 2020. [Online]. Available: http://ptm.asu.edu/
Roy CA (2020) Design of differential TG based 8T SRAM cell for ultralow-power applications. Microsystem Technologies, pp 3299–3310
Salahuddin SA (2013) A novel 6T SRAM cell with asymmetrically gate underlap engineered FinFETs for enhanced read data stability and write ability. International symposium on quality electronic design (ISQED), pp 353-358. IEEE
Sanvale P, Gupta N, Neema V, Shah AP, Vishvakarma SK (2019) An improved read-assist energy efficient single ended PPN based 10T SRAM cell for wireless sensor network. Microelectronics Journal 2:104611-219
Tomar AS (2020) A Schmitt-trigger based low read power 12T SRAM cell. Analog integrated circuits and signal processing, pp 275-295
Zhirnov VV (2005) Emerging research logic devices. IEEE Circ Devices Mag 21:37–46
Acknowledgments
We acknowledge the support and lab facility provided by the Department of ECE, Manipal University Jaipur, Jaipur, and Babol Noshirvani University of Technology.
Author information
Authors and Affiliations
Contributions
NA Additional declarations.
Corresponding author
Ethics declarations
Conflicts of Interest/Competing Interests
There is no conflict of interest at any stage.
Ethics Approval
NA It is a simulation-based design and analysis. So, it does not produce any environmental hazards.
Consent to Participate
Yes, we are ready to participate.
Consent for Publication
We are ready for publication with your journal.
Additional information
Publisher’s Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Abbasian, E., Birla, S. & Gholipour, M. A Comprehensive Analysis of Different SRAM Cell Topologies in 7-nm FinFET Technology. Silicon 14, 6909–6920 (2022). https://doi.org/10.1007/s12633-021-01432-6
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s12633-021-01432-6