skywater
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
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Aug 15, 2024 - Python
Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
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Mar 26, 2022 - Verilog
Fully-differential asynchronous non-binary 12-bit SAR-ADC
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Jun 13, 2023 - Verilog
GitHub Actions for usage with Google's 130nm manufacturable PDK for SkyWater Technology found @ https://github.com/google/skywater-pdk
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Jun 3, 2021 - Python
This repository is dedicated to VLSI ASIC Design Flow using open-source tools! Here, we embark on a journey that starts with specifications, RTL DV, Synthesis, Physical Design, Signoff and Finally Tape-It-Out
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Jan 23, 2024 - Verilog
Standard cells for SKY90FD provided by SkyWater.
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Jul 28, 2022
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process, embedded in efabless Caravel
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Sep 24, 2022 - Verilog
Mixed-mode silicon cochlea implementing wavelet processing in 130nm skywater process
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Dec 31, 2021 - Tcl
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