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openram
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OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
magic
asic
rtl
verilog
vlsi
foundry
yosys
klayout
caravel
netgen
system-on-chip
openroad
openram
skywater
130nm
soc-design
rtl2gds
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Updated
Aug 15, 2024 - Python
Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
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Updated
May 2, 2021 - SourcePawn
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