default search action
Google
Google Scholar
Semantic Scholar
Internet Archive Scholar
CiteSeerX
ORCIDVLSI Circuits 2018: Honolulu, HI, USA
- 2018 IEEE Symposium on VLSI Circuits, Honolulu, HI, USA, June 18-22, 2018. IEEE 2018, ISBN 978-1-5386-4214-6
- William J. Dally, C. Thomas Gray, John Poulton, Brucek Khailany, John M. Wilson, Larry R. Dennison:
Hardware-Enabled Artificial Intelligence. 3-6 - Tsuneo Komatsuzaki, Yasushi Matsumoto, Yoshihiko Hiraoka, Yohei Kaieda, Hiroki Kunii:
Semiconductor Technologies Accelerate Our Future Vision: "ANSHIN Platform". 1-4 - Mahmut E. Sinangil, Yen-Ting Lin, Hung-Jen Liao, Jonathan Chang:
A 290MV Ultra-Low Voltage One-Port SRAM Compiler Design Using a 12T Write Contention and Read Upset Free Bit-Cell in 7NM FinFET Technology. 13-14 - Hoan Nguyen, Jihoon Jeong, Francois Atallah, Marc Jansen, Anthony Polomik, Daniel Yingling, Harsha Akkaraju, Brad Appel, Rahul Nadkarni, Keith A. Bowman
:
A 7NM Double-Pumped 6R6W Register File for Machine Learning Memory. 1-2 - Woong Choi, Jongsun Park, Hoonki Kim, Changnam Park, Taejoong Song:
Half-and-Half Compare Content Addressable Memory with Charge-Sharing Based Selective Match-Line Precharge Scheme. 17-18 - Makoto Yabuuchi, Masao Morimoto, Koji Nii, Shinji Tanaka:
12-NM Fin-FET 3.0G-Search/s 80-Bit × 128-Entry Dual-Port Ternary CAM. 19-20 - Amy Whitcombe, Borivoje Nikolic, Farhana Sheikh, Erkan Alpman, Ashoke Ravi:
A Dual-Mode Configurable RF-to-Digital Receiver in 16NM FinFET. 23-24 - Tong Wang, Yosuke Ogasawara, Yuki Tuda, Tuan Thanh Ta, Masayoshi Oshiro, Jun Ihara, Tatsuhiko Maruyama, Toru Hashimoto, Akihide Sai, Takashi Tokairin:
An 113DB-Link-Budget Bluetooth-5 SoC with an 8dBm 22%-Efficiency TX. 25-26 - Yuta Toeda, Takumi Fujimaki, Mototsugu Hamada, Tadahiro Kuroda:
Fully Integrated OOK-Powered Pad-Less Deep Sub-Wavelength-Sized 5-GHz RFID with On-Chip Antenna Using Adiabatic Logic in 0.18μM CMOS. 27-28 - Dongseok Shin, Kwang-Jin Koh:
A Fast Triple-Interferer Sensor (Detector and Digital Encoder) with In-Situ Reference Frequency Acquisition at 2.7-to-3.7GHz in 0.13μM CMOS. 29-30 - Zhe Yuan, Jinshan Yue, Huanrui Yang, Zhibo Wang, Jinyang Li, Yixiong Yang, Qingwei Guo, Xueqing Li, Meng-Fan Chang, Huazhong Yang, Yongpan Liu:
Sticker: A 0.41-62.1 TOPS/W 8Bit Neural Network Processor with Multi-Sparsity Compatible Convolution Arrays and Online Tuning Acceleration for Fully Connected Layers. 33-34 - Bruce M. Fleischer, Sunil Shukla, Matthew M. Ziegler, Joel Silberman, Jinwook Oh, Vijayalakshmi Srinivasan, Jungwook Choi, Silvia M. Mueller, Ankur Agrawal, Tina Babinsky, Nianzheng Cao, Chia-Yu Chen, Pierce Chuang, Thomas W. Fox, George Gristede, Michael Guillorn, Howard Haynie, Michael J. Klaiber, Dongsoo Lee, Shih-Hsien Lo, Gary W. Maier, Michael Scheuermann, Swagath Venkataramani, Christos Vezyrtzis, Naigang Wang, Fanchieh Yee, Ching Zhou, Pong-Fei Lu, Brian W. Curran, Leland Chang, Kailash Gopalakrishnan:
A Scalable Multi- TeraOPS Deep Learning Processor Core for AI Trainina and Inference. 35-36 - Shouyi Yin, Peng Ouyang, Jianxun Yang, Tianyi Lu, Xiudong Li, Leibo Liu, Shaojun Wei:
An Ultra-High Energy-Efficient Reconfigurable Processor for Deep Neural Networks with Binary/Ternary Weights in 28NM CMOS. 37-38 - Mark A. Anders, Himanshu Kaul, Sanu Mathew, Vikram B. Suresh, Sudhir Satpathy, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
2.9TOPS/W Reconfigurable Dense/Sparse Matrix-Multiply Accelerator with Unified INT8/INTI6/FP16 Datapath in 14NM Tri-Gate CMOS. 39-40 - Taro Fujii, Takao Toi, Teruhito Tanaka, Katsumi Togawa, Toshiro Kitaoka, Kengo Nishino, Noritsugu Nakamura, Hiroki Nakahara, Masato Motomura:
New Generation Dynamically Reconfigurable Processor Technology for Accelerating Embedded AI Applications. 41-42 - Kee Hian Tan, Ping-Chuan Chiang, Yipeng Wang, Haibing Zhao, Arianne Roldan, Hongyuan Zhao, Nakul Narang, Siok-Wei Lim, Declan Carey, Sai Lalith Chaitanya Ambatipudi, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112-GB/S PAM4 Transmitter in 16NM FinFET. 45-46 - James Hudner, Declan Carey, Ronan Casey, Kay Hearne, Pedro Wilson de Abreu Farias Neto, Ilias Chlis, Marc Erett, Chi Fung Poon, Asma Laraba, Hongtao Zhang, Sai Lalith Chaitanya Ambatipudi, David Mahashin, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 112GB/S PAM4 Wireline Receiver Using a 64-Way Time-Interleaved SAR ADC in 16NM FinFET. 47-48 - Koji Maeda, Takayasu Norimatsu, Kenji Kogo, Naohiro Kohmu, Kei Nishimura, Izumi Fukasaku:
An Active Copper-Cable Supporting 56-Gbit/s PAM4 and 28-Gbit/s NRZ with Continuous Time Linear Equalizer IC for to-Meters Reach Interconnection. 49-50 - Haram Ju, Moon-Chul Choi, Gyu-Seob Jeong, Deog-Kyoon Jeong:
A 64 GB/s 1.5 PJ/Bit PAM-4 Transmitter with 3-Tap FFE and GM-Regulated Active-Feedback Driver in 28 NM CMOS. 51-52 - Thomas Toifl, Christian Menolfi, Matthias Brändli, Alessandro Cevrero, Pier Andrea Francese, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Morf, Ilter Özkaya:
A 0.3PJ/Bit 112GB/S PAM4 1+0.5D TX-DFE Precoder and 8-Tap FFE in 14NM CMOS. 53-54 - Eiji Yoshida, S. Kazama, S. Kuwamura, S. Gokita, T. Miyoshi, Y. Noguchi, Y. Honda:
Memory Expansion Technology for Large-Scale Data Processing Using Software-Controlled SSD. 59-60 - Pi-Feng Chiu, Christopher Celio, Krste Asanovic, David A. Patterson, Borivoje Nikolic:
An Out-of-Order RISC-V Processor with Resilient Low-Voltage Operation in 28NM CMOS. 61-62 - Mehdi Saligane, Jeongsup Lee, Qing Dong, Makoto Yasuda, Kazuyuki Kumeno, Fumitaka Ohno, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester:
An Adaptive Body-Biaslna SoC Using in Situ Slack Monitoring for Runtime Replica Calibration. 63-64 - Fahim ur Rahman, Sung Kim, Naveen John, Roshan Kumar, Xi Li, Rajesh Pamula, Keith A. Bowman, Visvesh S. Sathe:
An All-Digital Unified Clock Frequency and Switched-Capacitor Voltage Regulator for Variation Tolerance in a Sub-Threshold ARM Cortex M0 Processor. 65-66 - Scott Lindner, Chao Zhang, Ivan Michel Antolovic, Martin Wolf, Edoardo Charbon:
A 252 × 144 SPAD Pixel Flash Lidar with 1728 Dual-Clock 48.8 PS TDCs, Integrated Histogramming and 14.9-to-1 Compression in 180NM CMOS Technology. 69-70 - Shinzo Koyama, Motonori Ishii, Shigeru Saito, Masato Takemoto, Yugo Nose, Akito Inoue, Yusuke Sakata, Yuki Sugiura, Manabu Usuda, Tatsuya Kabe, Shigetaka Kasuga, Mitsuyoshi Mori, Yutaka Hirose, Akihiro Odagawa, Tsuyoshi Tanaka:
A 220 M-Range Direct Time-of-Flight 688 × 384 CMOS Image Sensor with Sub-Photon Signal Extraction (SPSE) Pixels Using Vertical Avalanche Photo-Diodes and 6 KHz Light Pulse Counters. 71-72 - Augusto Carimatto, Arin C. Ulku, Scott Lindner, E. D'Aillon, Bruce Rae, Sara Pellegrini, Edoardo Charbon:
Multipurpose, Fully-Integrated 128×128 Event-Driven MD-SiPM with 512 16-Bit TDCs with 45 PS LSB and 20 NS Gating. 73-74 - Chen Cao, Yuya Shirakawa, Leyi Tan, Min-Woong Seo, Keiichiro Kagawa, Keita Yasutomi, Tomohiko Kosugi, Satoshi Aoyama, Nobukazu Teranishi, Norimichi Tsumura, Shoji Kawahito:
A Two-Tap NIR Lock-in Pixel CMOS Image Sensor with Background Light Cancelling Capability for Non-Contact Heart Rate Detection. 75-76 - Yi-Chun Shih, Chia-Fu Lee, Yen-An Chang, Po-Hao Lee, Hon-Jarn Lin, Yu-Lin Chen, Ku-Feng Lin, Ta-Ching Yeh, Hung-Chang Yu, Harry Chuang, Yu-Der Chih, Tsung-Yung Jonathan Chang:
Logic Process Compatible 40NM 16MB, Embedded Perpendicular-MRAM with Hybrid-Resistance Reference, Sub-μA Sensing Resolution, and 17.5NS Read Access Time. 79-80 - Kevin Garello, Kevin Garello Yasin, S. Couet, Laurent Souriau, Johan Swerts, Sidharth Rao, Simon Van Beek, Wonsub Kim, Enlong Liu, Shreya Kundu, Diana Tsvetanova, Kris Croes, N. Jossart, E. Grimaldi, M. Baumgartner, D. Crotti, Arnaud Fumemont, Pietro Gambardella, Gouri Sankar Kar:
SOT-MRAM 300MM Integration for Low Power and Ultrafast Embedded Memories. 81-82 - Naoharu Shimomura, Hiroaki Yoda, Tomoaki Inokuchi, Katsuhiko Koi, Hideyuki Sugiyama, Yushi Kato, Yuichi Ohsawa, Altansargai Buyandalai, Satoshi Shirotori, Soichi Oikawa, Mariko Shimizu, Mizue Ishikawa, Tiwari Ajay, Atsushi Kurobe:
High-Speed Voltage Control Spintronics Memory (VoCSM) Having Broad Design Windows. 83-84 - Supreet Jeloka, Zhehong Wang, Ruochen Xie, Sudhanshu Khanna, Steven Bartling, Dennis Sylvester, David T. Blaauw:
Energy Efficient Adiabatic FRAM with 0.99 PJ/Bit Write for IoT Applications. 85-86 - Eric Hunt-Schroeder, Darren Anand, John A. Fifield, Mark Jacunski, Michael Roberge, Dale E. Pontius, Kevin Batson, Toshiaki Kirihata:
14NM FinFET 1.5MB Embedded High-K Charge Trap Transistor One Time Programmable Memory Using Dynamic Adaptive Programming. 87-88 - Junhua Shen, Akira Shikata, Anping Liu, Frederick Chalifoux:
A 12-Bit 31.1UW 1MS/S SAR ADC with On-Chip Input-Signal-Independent Calibration Achieving 100.4DB SFDR Using 256FF Sampling Capacitance. 91-92 - Zhaoming Ding, Xiong Zhou, Qiang Li:
A 0.5-1.1V 10B Adaptive Bypassing SAR ADC Utilizing Oscillation Cycle Information of VCO-Based Comparator. 93-94 - Kenichi Ohhata:
A 2.3-MW, 950-MHz, 8-Bit Fully-Time-Based Subranging ADC Using Highly-Linear Dynamic VTC. 95-96 - Haiwen Chen, Xiong Zhot, Qiang Yu, Fan Zhang, Qiang Li:
A >3GHz ERBW 1.1GS/S 8B Two-Sten SAR ADC with Recursive-Weight DAC. 97-98 - Bruno Vaz, Bob Verbruggen, Christophe Erdmann, Diarmuid Collins, John McGrath, Ali Boumaalif, Edward Cullen, Darragh Walsh, Alonso Morgado, Conrado Mesadri, Brian Long, Rajitha Pathepuram, Ronnie De La Torre, Alvin Manlapat, Georgios Karyotis, Dimitris Tsaliagos, Patrick Lynch, Peng Lim, Daire Breathnach, Brendan Farley:
A 13Bit 5GS/S ADC with Time-Interleaved Chopping Calibration in 16NM FinFET. 99-100 - Nicolas Butzen, Michiel Steyaert:
A Single-Topology Continuously-Scalable-Conversion-Ratio Fully Integrated Switched-Capacitor DC-DC Converter with 0-to-2.22V Output and 93% Peak-Efficiency. 103-104 - Kuniyuki Kakushima, Takuya Hoshii, M. Watanabe, N. Shizyo, K. Furukawa, Takuya Saraya, T. Takakura, K. Itou, M. Fukui, S. Suzuki, Ken Takeuchi, Iriya Muneta, Hitoshi Wakabayashi, Y. Numasawa, Atsushi Ogura, Shinichi Nishizawa, Kazuo Tsutsui, Toshiro Hiramoto, Hiromichi Ohashi, Hiroshi Iwai:
New Methodology for Evaluating Minority Carrier Lifetime for Process Assessment. 105-106 - Sung-Won Choi, Yeunhee Huh, Sang-Hui Park, Kye-Seok Yoon, Jun-Suk Bang, Se-Un Shin, Yong-Min Ju, Yu-Jin Yang, Junghyuk Yoon, Changyong Ahn, Taekseung Kim, Sung-Wan Hong, Gyu-Hyeong Cho:
A Quasi-Digital Ultra-Fast Capacitor-Less Low-Dropout Regulator Based on Comparator Control for x8 Current Spike of PCRAM Systems. 107-108 - Doyun Kim, Sung Kim, Mingoo Seok, Hyunju Ham, Jongwhan Kim:
0.5V-VIN, 165-MA/MM2 Fully-Integrated Digital LDO Based on Event-Driven Self-Trisuerina Control. 109-110 - Cheng Wang, Xiang Yi, Mina Kim, Yaqing Zhang, Ruonan Han:
A CMOS Molecular Clock Probing 231.061-GHz Rotational Line of OCS with Sub-PPB Long-Term Stability and 66-MW DC Power. 113-114 - Masaya Miyahara, Yukiya Endo, Kenichi Okada, Akira Matsuzawa:
A 64μs Start-Up 26/40MHz Crystal Oscillator with Negative Resistance Boosting Technique Using Reconfigurable Multi-Stage Amplifier. 115-116 - Jongyup Lim, Tae-Kwang Jang, Mehdi Saligane, Makoto Yasuda, Satoru Miyoshi, Masaru Kawaminami, David T. Blaauw, Dennis Sylvester:
A 224 PW 260 PPM/°C Gate-Leakage-Based Timer for Ultra-Low Power Sensor Nodes with Second-Order Temperature Dependency Cancellation. 117-118 - Orazio Aiello, Paolo Crovetti, Massimo Alioto:
A Sub-Leakage PW-Power HZ-Range Relaxation Oscillator Operating with 0.3V-1.8V Unregulated Supply. 119-120 - Jaehyuk Lee, Kyoung-Rog Lee, Unsoo Ha, Ji-Hoon Kim, Kwonjoon Lee, Hoi-Jun Yoo:
A 0.8V 82.9µW In-Ear BCI Controller System with 8.8 PEF EEG Instrumentational Amplifier and Wireless BAN Transceiver. 123-124 - Adam E. Mendrela, Sung-Yun Park, Mihály Vöröslakos, Michael P. Flynn, Euisik Yoon:
A Battery-Powered Opto-Electrophysiology Neural Interface with Artifact-Preventing Optical Pulse Shaping. 125-126 - Mohammad Reza Pazhouhandeh, Hossein Kassiri, Aly Shoukry, Iliya Weisspapir, Peter L. Carlen, Roman Genov:
Artifact-Tolerant Opamp-Less Delta-Modulated Bidirectional Neuro-Interface. 127-128 - Mingyi Chen, Ivan Dario Castro, Qiuyang Lin, Tom Torfs, Filip Tavernier, Chris Van Hoof, Nick Van Helleputte:
A 400GΩ Input-Impedance, 220MVpp Linear-Input-Range, 2.8Vpp CM-Interference-Tolerant Active Electrode for Non-Contact Capacitively Coupled ECG Acquisition. 129-130 - Amr Suleiman, Zhengdong Zhang, Luca Carlone, Sertac Karaman, Vivienne Sze:
Navion: A Fully Integrated Energy-Efficient Visual-Inertial Odometry Accelerator for Autonomous Navigation of Nano Drones. 133-134 - Ziyun Li, Jingcheng Wang, Dennis Sylvester, David T. Blaauw, Hun-Seok Kim:
A1920 × 1080 25FPS, 2.4TOPS/W Unified Optical Flow and Depth 6D Vision Processor for Energy-Efficient, Low Power Autonomous Navigation. 135-136 - Sanghoon Kang, Jinmook Lee, Changhyeon Kim, Hoi-Jun Yoo:
B-Face: 0.2 MW CNN-Based Face Recognition Processor with Face Alignment for Mobile User Identification. 137-138 - Shouyi Yin, Peng Ouyang, Shixuan Zheng, Dandan Song, Xiudong Li, Leibo Liu, Shaojun Wei:
A 141 UW, 2.46 PJ/Neuron Binarized Convolutional Neural Network Based Self-Learning Speech Recognition Processor in 28NM CMOS. 139-140 - Hossein Valavi, Peter J. Ramadge, Eric Nestler, Naveen Verma:
A Mixed-Signal Binarized Convolutional-Neural-Network Accelerator Integrating Dense Weight Storage and Multiplication for Reduced Data Movement. 141-142 - Jay Im, Stanley Chen, Dave Freitas, Adam Chou, Lei Zhou, Ian Zhuang, Tim Cronin, David Mahashin, Winson Lin, Kok Lim Chan, Hongyuan Zhao, Kee Hian Tan, Ade Bekele, Didem Turker, Parag Upadhyaya, Yohan Frans, Ken Chang:
A 0.5-28GB/S Wireline Tranceiver with 15-Tap DFE and Fast-Locking Digital CDR in 7NM FinFET. 145-146 - Jin-Hyeok Baek, Chang-Kyo Lee, Kiho Kim, Daesik Moon, Gil-Hoon Cha, Jin-Seok Heo, Min-Su Ahn, Dong-Ju Kim, Jae-Joon Song, Seokhong Kwon, Jongmin Kim, Kyung-Soo Kim, Jinoh Ahn, Jeong-Sik Nam, Byung-Cheol Kim, Jeong-Hyeon Cho, Jeonghoon Oh, Seung-Jun Bae, Indal Song, Seok-Hun Hyun, Ilgweon Kim, Hyuck-Joon Kwon, Young-Soo Sohn, Jung-Hwan Choi, Kwang-Il Park, Seong-Jin Jang:
A sub-0.85V, 6.4GBP/S/Pin TX-Interleaved Transceiver with Fast Wake-Up Time Using 2-Step Charging Control and VOHCalibration in 20NM DRAM Process. 147-148 - Yuta Tsubouchi, Daisuke Miyashita, Yuji Satoh, Takashi Toi, Fumihiko Tachibana, Makoto Morimoto, Junji Wadatsumi, Jun Deguchi:
A 12.8 GB/S Daisy Chain-Based Downlink I/F Employing Spectrally Compressed Multi-Band Multiplexing for High-Bandwidth and Large-Capacity Storage Systems. 149-150 - Rajesh Inti, Mozhgan Mansuri, Joe Kennedy, Hariprasath Venkatram, Chun-Ming Hsu, Aaron Martin, James E. Jaussi, Bryan Casper:
A Digital-Intensive 2-to-9.2 GB/S/Pin Memory Controller I/O with Fast-Response LDO in 10NM CMOS. 151-152 - Eric Chang, Nathan Narevsky, Jaeduk Han, Elad Alon:
An Automated SerDes Frontend Generator Verified with a 16NM Instance Achieving 15 GB/S at 1.96 PJ/Bit. 153-154 - Arup K. George, Wooyoon Shim, Minkyu Je, Junghyup Lee:
A 114-AF RMS- Resolution 46-NF/10-MΩ -Range Digital-Intensive Reconfigurable RC-to-Digital Converter with Parasitic-Insensitive Femto-Farad Baseline Sensing. 157-158 - Hui Jiang, Samira Amani, Johan G. Vogel, Saleh Heidary Shalmany, Stoyan N. Nihtianov:
A 117DB in-Band CMRR 98.5DB SNR Capacitance-to-Digital Converter for Sub-NM Displacement Sensing with an Electrically Floating Target. 159-160 - Ippei Akita, Takayuki Okazawa, Yoshihiko Kurui, Akira Fujimoto, Takashi Asano:
A 181NW 970µG✓HZ Accelerometer Analog Front-End Employing Feedforward Noise Reduction Technique. 161-162 - Sujin Park, Geon-Hwi Lee, SeongHwan Cho:
A 2.69UW Dual Quantization-Based Capacitance-to-Digital Converter for Pressure, Humidity, and Acceleration Sensing in 0.18UM CMOS. 163-164 - Yuxuan Luo, Chun-Huat Heng:
An 8.2 µW 0.14 MM216-Channel CDMA-Like Period Modulation Capacitance-Tu-Diaital Converter with Reduced Data Throuahput. 165-166 - Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De:
An All-Digital Unified Static/Dynamic Entropy Generator Featuring Self-Calibrating Hierarchical Von Neumann Extraction for Secure Privacy-Preserving Mutual Authentication in IoT Mote Platforms. 169-170 - Kaiyuan Yang, Qing Dong, Zhehong Wang, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, David T. Blaauw, Dennis Sylvester:
A 28NM Integrated True Random Number Generator Harvesting Entropy from MRAM. 171-172 - Rajesh Pamula, Xun Sun, Sung Kim, Fahim ur Rahman, Baosen Zhang, Visvesh S. Sathe:
An All-Digital True-Random-Number Generator with Integrated De-correlation and Bias Correction at 3.2-to-86 MB/S, 2.58 PJ/Bit in 65-NM CMOS. 1-2 - Sudhir Satpathy, Vikram B. Suresh, Sanu Mathew, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
220MV-900MV 794/584/754 GBPS/W Reconfigurable GF(24)2 AES/SMS4/Camellia Symmetric-Key Cipher Accelerator in 14NM Tri-Gate CMOS. 175-176 - Ting-Kuei Kuan, Chin-Yang Wu, Ruei-Pin Shen, Chih-Hsien Chang, Kenny Hsieh, Mark Chen:
A Digital Bang-Bang Phase-Locked Loop with Background Injection Timing Calibration and Automatic Loop Gain Control in 7NM FinFET CMOS. 179-180 - Dhon-Gue Lee, Patrick P. Mercier:
AMASS PLL: An Active-Mixer-Adopted Sub-Sampling PLL Achieving an FOM of -255.5DB and a Reference Spur of -66.6DBC. 181-182 - Tsung-Hsien Tsai, Ruey-Bin Sheen, Chih-Hsien Chang, Robert Bogdan Staszewski:
A 0.2GHz to 4GHz Hybrid PLL (ADPLL/Charge-Pump-PLL) in 7NM FinFET CMOS Featuring 0.619PS Integrated Jitter and 0.6US Settling Time at 2.3MW. 183-184 - Seojin Choi, Seyeon Yoo, Yongsun Lee, Yongwoo Jo, Jeonghyun Lee, Younghyun Lim, Jaehyouk Choi:
153 FSRMS-Integrated-Jitter and 114-Multiplication Factor PVT-Robust 22.8 GHZ Ring-LC-Hybrid Injection-Locked Clock Multiplier. 185-186 - Ahmed Sawaby, Max L. Wang, Ernest So, Jun-Chau Chien, Hao Nan, Butrus T. Khuri-Yakub, Amin Arbabian:
A Wireless Implantable Ultrasound Array Receiver for Thermoacoustic Imaging. 189-190 - Xiao Wu, Inhee Lee, Qing Dong, Kaiyuan Yang, Dongkwun Kim, Jingcheng Wang, Yimai Peng, Yiqun Zhang, Mehdi Saligane, Makoto Yasuda, Kazuyuki Kumeno, Fumitaka Ohno, Satoru Miyoshi, Masaru Kawaminami, Dennis Sylvester, David T. Blaauw:
A 0.04MM316NW Wireless and Batteryless Sensor System with Integrated Cortex-M0+ Processor and Optical Communication for Cellular Temperature Measurement. 191-192 - Jiacheng Pan, Asad A. Abidi, Wenlong Jiang, Dejan Rozgic, Dejan Markovic:
Self-Regulated Wireless Power and Simultaneous 5MB/S Reverse Data over One Pair of Coils. 193-194 - Suhwan Kim, Vaibhav A. Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. 195-196 - Changwook Lee, Moon Hyung Jang, Youngcheol Chae:
A 1.2V 68µW 98.2DB-DR Audio Continuous-Time Delta-Sigma Modulator. 199-200 - Jiaxin Liu, Shaolan Li, Wenjuan Guo, Guangjun Wen, Nan Sun:
A 0.029MM2 17-FJ/Conv.-Step CT $\Delta\Sigma$ ADC with 2nd-Order Noise-Shaping SAR Quantizer. 201-202 - Yan Song, Yan Zhu, Chi-Hang Chan, Li Geng, Rui Paulo Martins:
A 77dB SNDR 12.5MHz Bandwidth 0-1 MASH ∑Δ ADC Based on the Pipelined-SAR Structure. 203-204 - Takato Katayama, Shiko Miyashita, Kazuki Sobue, Koichi Hamashita:
A 1.25MS/S Two-Step Incremental ADC with 100DB DR and 110DB SFDR. 205-206 - Biao Wang, Sai-Weng Sin, Seng-Pan U, Franco Maloberti, Rui Paulo Martins:
A 550µW 20kHz BW 100.8DB SNDR Linear-Exponential Multi-Bit Incremental Converter with 256-cycles in 65NM CMOS. 207-208 - Qian Zhong, Wooyeol Choi, Kenneth K. O:
Terahertz RF Front-End Employing Even-Order Subharmonic MOS Symmetric Varactor Mixers in 65-NM CMOS for Hydration Measurements at 560 GHz. 211-212 - Aoyang Zhang, Mike Shuo-Wei Chen:
A Sub-Harmonic Switching Digital Power Amplifier with Hybrid Class-G Operation for Enhancing Power Back-off Efficiency. 213-214 - Nereo Markulic, Pratap Renukaswarny, Ewout Martens, Barend van Liempd, Piet Wambacq, Jan Craninckx:
A 5.5 GHz Background-Calibrated Subsampling Polar Transmitter with -41.3 DB EVM at 1024 OAM in 28NM CMOS. 215-216 - Xiangyu Meng, Can Wang, Milad Kalantari, C. Patrick Yue:
A 16-GB/S 0-DB Power Back-Off 16-QAM Transmitter at 28 GHZ in 65-NM CMOS. 217-218 - Christophe Erdmann, Bob Verbruggen, Bruno Vaz, Roberto Pelliconi, John McGrath, Ryan Kinnerk, Ronnie De La Torre, John O'Dwyer, Patrick Lynch, Padraig Kelly, Peng Lim, Daire Breathnach, Brendan Farley:
A modular 16NM Direct-RF TX/RX Embedding 9GS/S DAC and 4.5GS/S ADC with 90DB Isolation and Sub-80PS Channel Alignment for Monolithic Integration in 5G Base-Station SoC. 219-220 - Danzhu Lu, Peng Liu, Suyi Yao, Langyuan Wang, Jie He:
A 95.3% Peak Efficiency, 135NA Quiescent Current Buck-Boost DC-DC Converter with Current-Slope-Based Mode Control. 223-224 - Yeunhee Huh, Se-Un Shin, Sung-Wan Hong, Young-Jin Woo, Yong-Min Ju, Sung-Won Choi, Gyu-Hyeong Cho:
A Hybrid Dual-Path Step-Down Converter with 96.2% Peak Efficiency Using a $250\text{m}$ μ Large-DCR Inductor. 225-226 - Yuki Karasawa, Takanobu Fukuoka, Kousuke Miyaji:
A 92.8% Efficiency Adaptive-On/Off-Time Control 3-Level Buck Converter for Wide Conversion Ratio with Shared Charge Pump Intermediate Voltage Regulator. 227-228 - Shao-Qi Chen, Chia-Ming Huang, Ke-Horng Chen, Ying-Hsi Lin, Shian-Ru Lin, Tsung-Yen Tsai:
An Ultra-low Quiescent Current 250NA Low Dropout Regulator for No-Load to 10MA Internet-of-Evervthing Applications. 229-230 - Jun-Eun Park, Deog-Kyoon Jeong:
A Fully Integrated 700MA Event-Driven Digital Low-Dropout Regulator with Residue-Tracking Loop for Fine-Grained Power Management Unit. 231-232 - Nandish Mehta, Johan H. Huijsing, Vladimir Stojanovic:
A 1MW -101DB THD+N Class-AB High-Fidelity Headphone Driver in 65NM CMOS. 235-236 - Tae-Kwang Jang, Jongyup Lim, Kyojin David Choo, Samuel Nason, Jeongsup Lee, Jeongsup Oh, Seokhyeon Jeong, Cynthia A. Chestek, Dennis Sylvester, David T. Blaauw:
A 2.2 NEF Neural-Recording Amplifier Using Discrete-Time Parametric Amplification. 237-238 - Jun-Suk Bang, Hyuntak Jeon, Minkyu Je, Gyu-Hyeong Cho:
6.5µW 92.3DB-DR Biopotential-Recording Front-End with 360MVPP Linear Input Range. 239-240 - Komail M. H. Badami, Kushal Dakshina Murthy, Pieter Harpe, Marian Verhelst:
A 0.6V 54DB SNR Analog Frontend with 0.18% THD for Low Power Sensory Applications in 65NM CMOS. 241-242 - Laurent Millet, Stéphane Chevobbe, Caaliph Andriamisaina, Edith Beigné, Fabrice Guellec, Thomas Dombek, Lamine Benaissa, Edouard Deschaseaux, Marc Duranton, K. Benchehida, Mehdi Darouich, Maria Lepecq:
A 5500FPS 85GOPS/W 3D Stacked BSI Vision Chip Based on Parallel in-Focal-Plane Acquisition and Processing. 245-246 - Xiaopeng Zhong, Qian Yu, Amine Bermak, Chi-Ying Tsui, May-Kay Law:
A 2PJ/Pixel/Direction MIMO Processing Based CMOS Image Sensor for Omnidirectional Local Binary Pattern Extraction and Edge Detection. 247-248 - Mohamed I. Ibrahim, Christopher Foy, Donggyu Kim, Dirk R. Englund, Ruonan Han:
Room-Temperature Quantum Sensing in CMOS: On-Chip Detection of Electronic Spin States in Diamond Color Centers for Magnetometry. 249-250 - Inhee Lee, Gyouho Kim, Eunseong Moon, Seokhyeon Jeong, Dongkwun Kim, Jamie Phillips, David T. Blaauw:
A 179-Lux Energy-Autonomous Fully-Encapsulated 17-mm3 Sensor Node with Initial Charge Delay Circuit for Battery Protection. 251-252 - Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. 255-256 - Tsu-Ming Liu, Chang-Hung Tsai, Tung-Hsing Wu, Jia-Ying Lin, Li-Heng Chen, Han-Liang Chou, Chi-Cheng Ju:
A 0.76MM2 0.22NJ/Pixel DL-Assisted 4K Video Encoder LSI for Quality-of-Experience Over Smart-Phones. 257-258 - Shuo-An Huang, Kai-Chieh Chang, Horng-Huei Liou, Chia-Hsiang Yang:
A 1.9MW SVM Processor with On-Chip Active Learning for Epileptic Seizure Control. 259-260 - Yu-Zhe Wang, Yao-Pin Wang, Yi-Chung Wu, Chia-Hsiang Yang:
A 12.6MW 573-2, 901KS/S Reconfigurable Processor for Reconstruction of Compressively-Sensed Phvsiological Signals. 261-262 - Kentaro Yoshioka, Yosuke Toyama, Koichiro Ban, Daisuke Yashima, Shigeru Maya, Akihide Sai, Kohei Onizuka:
PhaseMAC: A 14 TOPS/W 8bit GRO Based Phase Domain MAC Circuit for in-Sensor-Computed Deep Learning Accelerators. 263-264 - Pier Andrea Francese, Alessandro Cevrero, Ilter Özkaya, Matthias Brändli, Christian Menolfi, Thomas Morf, Marcel A. Kossel, Lukas Kull, Danny Luu, Thomas Toifl:
A 50GB/S 1.6PJ/B RX Data-Path with Quarter-Rate 3-Tap Speculative DFE. 267-268 - Kevin Zheng, Yohan Frans, Sai Lalith Ambatipudi, Santiago Asuncion, Hari Teja Reddy, Ken Chang, Boris Murmann:
An Inverter-Based Analog Front End for a 56 GB/S PAM4 Wireline Transceiver in 16NMCMOS. 269-270 - Long Kong, Yikun Chang, Behzad Razavi:
A 14 µM × 26 µM 20-GB/S 3-MW CDR Circuit with High Jitter Tolerance. 271-272 - Sen Lin, Sajjad Moazeni, Vladimir Stojanovic:
A 40GB/S Optical NRZ Transmitter Based on Monolithic Microring Modulators in 45NM SOI CMOS. 273-274 - Lukas Kull, Danny Luu, Christian Menolfi, Thomas Morf, Pier Andrea Francese, Matthias Braendli, Marcel A. Kossel, Alessandro Cevrero, Ilter Özkaya, Thomas Toifl:
A 10-Bit 20-40 GS/S ADC with 37 dB SNDR at 40 GHz Input Using First Order Sampling Bandwidth Calibration. 275-276
manage site settings
To protect your privacy, all features that rely on external API calls from your browser are turned off by default. You need to opt-in for them to become active. All settings here will be stored as cookies with your web browser. For more information see our F.A.Q.
last updated on 2024-11-18 20:33 CET by the dblp team
all metadata released as open data under CC0 1.0 license
see also: Terms of Use | Privacy Policy | Imprint
dblp was originally created in 1993 at:
since 2018, dblp has been operated and maintained by:
the dblp computer science bibliography is funded and supported by:
