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ORCIDGregory K. Chen
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2020 – today
- 2024
[j18]Chuan-Tung Lin
, Dewei Wang, Bo Zhang, Gregory K. Chen, Phil C. Knag, Ram Kumar Krishnamurthy, Mingoo Seok:
DIMCA: An Area-Efficient Digital In-Memory Computing Macro Featuring Approximate Arithmetic Hardware in 28 nm. IEEE J. Solid State Circuits 59(3): 960-971 (2024)- 2023
- [j17]Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy:
An Eight-Core RISC-V Processor With Compute Near Last Level Cache in Intel 4 CMOS. IEEE J. Solid State Circuits 58(4): 1117-1128 (2023) - [c38]Dewei Wang, Jonghyun Oh, Gregory K. Chen, Phil C. Knag, Ram K. Krishnamurthy, Mingoo Seok:
microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware. ESSCIRC 2023: 421-424 - 2022
- [c37]Dewei Wang, Chuan-Tung Lin, Gregory K. Chen, Phil C. Knag, Ram Kumar Krishnamurthy, Mingoo Seok:
DIMC: 2219TOPS/W 2569F2/b Digital In-Memory Computing Macro in 28nm Based on Approximate Arithmetic Hardware. ISSCC 2022: 266-268 - [c36]Gregory K. Chen, Phil C. Knag, Carlos Tokunaga, Ram K. Krishnamurthy:
An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS. VLSI Technology and Circuits 2022: 68-69 - 2021
- [j16]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Mark A. Anders, Himanshu Kaul, Ram K. Krishnamurthy:
A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 56(4): 1082-1092 (2021) - 2020
- [j15]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek De, Sanu K. Mathew:
A 4900- $\mu$ m2 839-Mb/s Side-Channel Attack- Resistant AES-128 in 14-nm CMOS With Heterogeneous Sboxes, Linear Masked MixColumns, and Dual-Rail Key Addition. IEEE J. Solid State Circuits 55(4): 945-955 (2020) - [c35]Amit Agarwal, Steven Hsu, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Sanu Mathew, Mahesh Kumashikar, Ram Krishnamurthy, Vivek De:
25.7 Time-Borrowing Fast Mux-D Scan Flip-Flop with On-Chip Timing/Power/VMIN Characterization Circuits in 10nm CMOS. ISSCC 2020: 392-394 - [c34]Mark A. Anders, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De:
25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range. ISSCC 2020: 396-398 - [c33]Steven Hsu, Amit Agarwal, Simeon Realov, Mark A. Anders, Gregory K. Chen, Monodeep Kar, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Himanshu Kaul, Vikram B. Suresh, Sanu Mathew, Iqbal Rajwani, Satish Damaraju, Ram Krishnamurthy, Vivek De:
Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS. VLSI Circuits 2020: 1-2 - [c32]Monodeep Kar, Amit Agarwal, Steven Hsu, David Moloney, Gregory K. Chen, Raghavan Kumar, Huseyin Sumbul, Phil C. Knag, Mark A. Anders, Himanshu Kaul, Jonathan Byrne, Luca Sarti, Ram Krishnamurthy, Vivek De:
A Ray-Casting Accelerator in 10nm CMOS for Efficient 3D Scene Reconstruction in Edge Robotics and Augmented Reality Applications. VLSI Circuits 2020: 1-2 - [c31]Phil C. Knag, Gregory K. Chen, Huseyin Ekin Sumbul, Raghavan Kumar, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Monodeep Kar, Seongjong Kim, Ram K. Krishnamurthy:
A 617 TOPS/W All Digital Binary Neural Network Accelerator in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j14]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8-pJ/SOP Spiking Neural Network With On-Chip STDP Learning and Sparse Weights in 10-nm FinFET CMOS. IEEE J. Solid State Circuits 54(4): 992-1002 (2019) - [c30]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Debbie Marr, Aravind Dasu:
Why Compete When You Can Work Together: FPGA-ASIC Integration for Persistent RNNs. FCCM 2019: 199-207 - [c29]Eriko Nurvitadhi, Dongup Kwon, Ali Jafari, Andrew Boutros, Jaewoong Sim, Phillip Tomson, Huseyin Sumbul, Gregory K. Chen, Phil C. Knag, Raghavan Kumar, Ram Krishnamurthy, Debbie Marr, Sergey Gribok, Bogdan Pasca, Martin Langhammer, Aravind Dasu:
Evaluating and Enhancing Intel® Stratix® 10 FPGAs for Persistent Real-Time AI. FPGA 2019: 119 - [c28]Raghavan Kumar, Vikram B. Suresh, Monodeep Kar, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De, Sanu Mathew:
A 4900×m2 839Mbps Side-Channel Attack Resistant AES-128 in 14nm CMOS with Heterogeneous Sboxes, Linear Masked MixColumns and Dual-Rail Key Addition. VLSI Circuits 2019: 234- - 2018
- [c27]Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Ram K. Krishnamurthy:
A 4096-Neuron 1M-Synapse 3.8PJ/SOP Spiking Neural Network with On-Chip STDP Learning and Sparse Weights in 10NM FinFET CMOS. VLSI Circuits 2018: 255-256 - 2017
- [j13]Sudhir Satpathy, Sanu K. Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy, Vivek K. De:
A 4-fJ/b Delay-Hardened Physically Unclonable Function Circuit With Selective Bit Destabilization in 14-nm Trigate CMOS. IEEE J. Solid State Circuits 52(4): 940-949 (2017) - [c26]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and hardware design of discrete-time spiking neural networks based on back propagation with binary activations. BioCAS 2017: 1-5 - [i1]Shihui Yin, Shreyas K. Venkataramanaiah, Gregory K. Chen, Ram Krishnamurthy, Yu Cao, Chaitali Chakrabarti, Jae-sun Seo:
Algorithm and Hardware Design of Discrete-Time Spiking Neural Networks Based on Back Propagation with Binary Activations. CoRR abs/1709.06206 (2017) - 2016
- [j12]Sanu K. Mathew, David Johnston, Sudhir Satpathy, Vikram B. Suresh, Paul Newman, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram K. Krishnamurthy:
µRNG: A 300-950 mV, 323 Gbps/W All-Digital Full-Entropy True Random Number Generator in 14 nm FinFET CMOS. IEEE J. Solid State Circuits 51(7): 1695-1704 (2016) - [c25]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Gregory K. Chen, Himanshu Kaul, Amit Agarwal, Steven Hsu, Ram Krishnamurthy, Vivek De:
A 305mV-850mV 400μW 45GSamples/J reconfigurable compressive sensing engine with early-termination for ultra-low energy target detection in 14nm tri-gate CMOS. A-SSCC 2016: 253-256 - [c24]Himanshu Kaul, Mark A. Anders, Sanu K. Mathew, Gregory K. Chen, Sudhir Satpathy, Steven Hsu, Amit Agarwal, Ram Krishnamurthy:
14.4 A 21.5M-query-vectors/s 3.37nJ/vector reconfigurable k-nearest-neighbor accelerator with adaptive precision in 14nm tri-gate CMOS. ISSCC 2016: 260-261 - [c23]Amit Agarwal, Steven Hsu, Mark A. Anders, Sanu Mathew, Gregory K. Chen, Himanshu Kaul, Sudhir Satpathy, Ram Krishnamurthy:
A 350mV-900mV 2.1GHz 0.011mm2 regular expression matching accelerator with aging-tolerant low-VMIN circuits in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [c22]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy, Vivek De:
A 4fJ/bit delay-hardened physically unclonable function circuit with selective bit destabilization in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [c21]Sudhir Satpathy, Sanu Mathew, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
250mV-950mV 1.1Tbps/W double-affine mapped Sbox based composite-field SMS4 encrypt/decrypt accelerator in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j11]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven Hsu, Amit Agarwal, Ram Krishnamurthy, Vivek De, Shekhar Borkar:
A 340 mV-to-0.9 V 20.2 Tb/s Source-Synchronous Hybrid Packet/Circuit-Switched 16 × 16 Network-on-Chip in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(1): 59-67 (2015) - [j10]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Amit Agarwal, Steven Hsu, Gregory K. Chen, Ram Krishnamurthy:
340 mV-1.1 V, 289 Gbps/W, 2090-Gate NanoAES Hardware Accelerator With Area-Optimized Encrypt/Decrypt GF(2 4 ) 2 Polynomials in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(4): 1048-1058 (2015) - [c20]Sanu Mathew, David Johnston, Paul Newman, Sudhir Satpathy, Vikram B. Suresh, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
μRNG: A 300-950mV 323Gbps/W all-digital full-entropy true random number generator in 14nm FinFET CMOS. ESSCIRC 2015: 116-119 - 2014
- [c19]Sudhir Satpathy, Sanu Mathew, Jiangtao Li, Patrick Koeberl, Mark A. Anders, Himanshu Kaul, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
13fJ/bit probing-resilient 250K PUF array with soft darkbit masking for 1.94% bit-error in 22nm tri-gate CMOS. ESSCIRC 2014: 239-242 - [c18]Gregory K. Chen, Mark A. Anders, Himanshu Kaul, Sudhir Satpathy, Sanu K. Mathew, Steven K. Hsu, Amit Agarwal, Ram K. Krishnamurthy, Shekhar Borkar, Vivek De:
16.1 A 340mV-to-0.9V 20.2Tb/s source-synchronous hybrid packet/circuit-switched 16×16 network-on-chip in 22nm tri-gate CMOS. ISSCC 2014: 276-277 - [c17]Sanu K. Mathew, Sudhir Satpathy, Mark A. Anders, Himanshu Kaul, Steven K. Hsu, Amit Agarwal, Gregory K. Chen, Rachael J. Parker, Ram K. Krishnamurthy, Vivek De:
16.2 A 0.19pJ/b PVT-variation-tolerant hybrid physically unclonable function circuit for 100% stable secure key generation in 22nm CMOS. ISSCC 2014: 278-279 - [c16]Sanu Mathew, Sudhir Satpathy, Vikram B. Suresh, Himanshu Kaul, Mark A. Anders, Gregory K. Chen, Amit Agarwal, Steven Hsu, Ram Krishnamurthy:
340mV-1.1V, 289Gbps/W, 2090-gate NanoAES hardware accelerator with area-optimized encrypt/decrypt GF(24)2 polynomials in 22nm tri-gate CMOS. VLSIC 2014: 1-2 - 2013
- [j9]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Centip3De: a many-core prototype exploring 3D integration and near-threshold computing. Commun. ACM 56(11): 97-104 (2013) - [j8]David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester:
Centip3De: A Cluster-Based NTC Architecture With 64 ARM Cortex-M3 Cores in 3D Stacked 130 nm CMOS. IEEE J. Solid State Circuits 48(1): 104-117 (2013) - [j7]Matthew Fojtik, Daeyeon Kim, Gregory K. Chen, Yu-Shiang Lin, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, David T. Blaauw, Dennis Sylvester:
A Millimeter-Scale Energy-Autonomous Sensor System With Stacked Battery and Solar Cells. IEEE J. Solid State Circuits 48(3): 801-813 (2013) - [j6]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Centip3De: A 64-Core, 3D Stacked Near-Threshold System. IEEE Micro 33(2): 8-16 (2013) - [j5]Mohammad Hassan Ghaed, Gregory K. Chen, Razi-Ul Haque, Michael Wieckowski, Yejoong Kim, Gyouho Kim, Yoonmyung Lee, Inhee Lee, David Fick, Daeyeon Kim, Mingoo Seok, Kensall D. Wise, David T. Blaauw, Dennis Sylvester:
Circuits for a Cubic-Millimeter Energy-Autonomous Wireless Intraocular Pressure Monitor. IEEE Trans. Circuits Syst. I Regul. Pap. 60-I(12): 3152-3162 (2013) - 2012
- [j4]Andrew DeOrio, David Fick, Valeria Bertacco, Dennis Sylvester, David T. Blaauw, Jin Hu, Gregory K. Chen:
A Reliable Routing Architecture and Algorithm for NoCs. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 31(5): 726-739 (2012) - [c15]Ronald G. Dreslinski, David Fick, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Centip3De: A 64-core, 3D stacked, near-threshold system. Hot Chips Symposium 2012: 1-30 - [c14]David Fick, Ronald G. Dreslinski, Bharan Giridhar, Gyouho Kim, Sangwon Seo, Matthew Fojtik, Sudhir Satpathy, Yoonmyung Lee, Daeyeon Kim, Nurrachman Liu, Michael Wieckowski, Gregory K. Chen, Trevor N. Mudge, Dennis Sylvester, David T. Blaauw:
Centip3De: A 3930DMIPS/W configurable near-threshold 3D stacked system with 64 ARM Cortex-M3 cores. ISSCC 2012: 190-192 - [c13]Hassan Ghaed, Gregory K. Chen, David T. Blaauw, Dennis Sylvester:
Analysis and measurement of the stability of dual-resonator oscillators. RWS 2012: 219-222 - 2011
- [j3]Mingoo Seok, Gregory K. Chen, Scott Hanson, Michael Wieckowski, David T. Blaauw, Dennis Sylvester:
CAS-FEST 2010: Mitigating Variability in Near-Threshold Computing. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(1): 42-49 (2011) - [c12]Gregory K. Chen, Michael Wieckowski, Daeyeon Kim, David T. Blaauw, Dennis Sylvester:
A dense 45nm half-differential SRAM with lower minimum operating voltage. ISCAS 2011: 57-60 - [c11]Daeyeon Kim, Gregory K. Chen, Matthew Fojtik, Mingoo Seok, David T. Blaauw, Dennis Sylvester:
A 1.85fW/bit ultra low leakage 10T SRAM with speed compensation scheme. ISCAS 2011: 69-72 - [c10]Michael Wieckowski, Gregory K. Chen, Daeyeon Kim, David T. Blaauw, Dennis Sylvester:
A 128kb high density portless SRAM using hierarchical bitlines and thyristor sense amplifiers. ISQED 2011: 87-90 - [c9]Gregory K. Chen, Hassan Ghaed, Razi-Ul Haque, Michael Wieckowski, Yejoong Kim, Gyouho Kim, David Fick, Daeyeon Kim, Mingoo Seok, Kensall D. Wise, David T. Blaauw, Dennis Sylvester:
A cubic-millimeter energy-autonomous wireless intraocular pressure monitor. ISSCC 2011: 310-312 - 2010
- [j2]Gregory K. Chen, Scott Hanson, David T. Blaauw, Dennis Sylvester:
Circuit Design Advances for Wireless Sensing Applications. Proc. IEEE 98(11): 1808-1827 (2010) - [j1]Gregory K. Chen, Dennis Sylvester, David T. Blaauw, Trevor N. Mudge:
Yield-Driven Near-Threshold SRAM Design. IEEE Trans. Very Large Scale Integr. Syst. 18(11): 1590-1598 (2010) - [c8]Vivek Joshi, Michael Wieckowski, Gregory K. Chen, David T. Blaauw, Dennis Sylvester:
Analyzing the impact of Double Patterning Lithography on SRAM variability in 45nm CMOS. CICC 2010: 1-4 - [c7]Yoonmyung Lee, Gregory K. Chen, Scott Hanson, Dennis Sylvester, David T. Blaauw:
Ultra-low power circuit techniques for a new class of sub-mm3 sensor nodes. CICC 2010: 1-8 - [c6]Gregory K. Chen, Michael Wieckowski, David T. Blaauw, Dennis Sylvester:
Crosshairs SRAM - An adaptive memory for mitigating parametric failures. ESSCIRC 2010: 366-369 - [c5]Mingoo Seok, Scott Hanson, Michael Wieckowski, Gregory K. Chen, Yu-Shiang Lin, David T. Blaauw, Dennis Sylvester:
Circuit design advances to enable ubiquitous sensing environments. ISCAS 2010: 285-288 - [c4]Gregory K. Chen, Matthew Fojtik, Daeyeon Kim, David Fick, Junsun Park, Mingoo Seok, Mao-Ter Chen, Zhiyoong Foo, Dennis Sylvester, David T. Blaauw:
Millimeter-scale nearly perpetual sensor system with stacked battery and solar cells. ISSCC 2010: 288-289
2000 – 2009
- 2009
- [c3]David Fick, Andrew DeOrio, Gregory K. Chen, Valeria Bertacco, Dennis Sylvester, David T. Blaauw:
A highly resilient routing algorithm for fault-tolerant NoCs. DATE 2009: 21-26 - 2008
- [c2]Ronald G. Dreslinski, Gregory K. Chen, Trevor N. Mudge, David T. Blaauw, Dennis Sylvester, Krisztián Flautner:
Reconfigurable energy efficient near threshold cache architectures. MICRO 2008: 459-470 - 2007
- [c1]Gregory K. Chen, David T. Blaauw, Trevor N. Mudge, Dennis Sylvester, Nam Sung Kim:
Yield-driven near-threshold SRAM design. ICCAD 2007: 660-666
Coauthor Index
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