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ORCIDJames W. Tschanz
Jim Tschanz
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- affiliation: Intel
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2020 – today
- 2024
[c87]Suhwan Kim, Harish K. Krishnamurthy, Zakir Ahmed, Nachiket V. Desai, Sheldon Weng, Anne Augustine, Huong T. Do, Jingshu Yu, Phong D. Bach, Xiaosen Liu, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
14.9 A Monolithic 10.5W/mm2600 MHz Top-Metal and C4 Planar Spiral Inductor-Based Integrated Buck Voltage Regulator on 16nm-Class CMOS. ISSCC 2024: 270-272- [c86]Nicolas Butzen, Harish Krishnamurthy, Jingshu Yu, Khondker Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, James Waldemer, Chris Pelto, James W. Tschanz:
28.4 A Monolithic 12.7W/mm2 Pmax, 92% Peak-Efficiency CSCR-First Switched-Capacitor DC-DC Converter. ISSCC 2024: 462-464 - [c85]Sally Amin, Harish Krishnamurthy, Huong Do, Claudio Alvarez, Mike Hill, Kaladhar Radhakrishnan, Vivek De, Sheldon Weng, Krishnan Ravichandran, Jim Tschanz, Wilfred Gomes, Jonathan Douglas:
A 5.4V-Vin, 9.3A/mm2 10MHz Buck IVR Chiplet in 55nm BCD Featuring Self-Timed Bootstrap and Same-Cycle ZVS Control. VLSI Technology and Circuits 2024: 1-2 - [c84]Jingshu Yu, Xiaosen Liu, Minxiang Gong, Nicolas Butzen, Sheldon Weng, Harish K. Krishnamurthy, Krishnan Ravichandran, Ramez Hosseinian Ahangharnejhad, Waldemer Jim, Christopher Pelto, James W. Tschanz, Vivek De:
A Monolithic 5.7A/mm2 91% Peak Efficiency Scalable Multi-Stage Modular Switched Capacitor Voltage Regulator with Self-Timed Deadtime and Safe Startup for 3D-ICs. VLSI Technology and Circuits 2024: 1-2 - 2023
- [c83]Suhwan Kim, Harish K. Krishnamurthy, Sergey Sofer, Sheldon Weng, Shahar Wolf, Ashoke Ravi, Krishnan Ravichandran, Ofir Degani, James W. Tschanz, Vivek De:
A 1.8W High-Frequency SIMO Converter Featuring Digital Sensor-Less Computational Zero-Current Operation and Non-Linear Duty-Boost. ISSCC 2023: 186-187 - [c82]Nicolas Butzen, Harish Krishnamurthy, Zakir Ahmed, Sheldon Weng, Krishnan Ravichandran, Michael Zelikson, James W. Tschanz, Jonathan Douglas:
A Monolithic 26A/mm2Imax, 88.5% Peak-Efficiency Continuously Scalable Conversion-Ratio Switched-Capacitor DC-DC Converter. ISSCC 2023: 232-233 - [c81]Charles Augustine, Pascal Meinerzhagen, Wootaek Lim, A. Veerabathini, M. Bright, K. Mojjada, Jim Tschanz, Muhammad M. Khellah, Vivek De:
A 2.6 mV/b Resolution, 1.2 GHz Throughput, All-Digital Voltage Droop Monitor Using Coupled Ring Oscillators in Intel 4 CMOS. VLSI Technology and Circuits 2023: 1-2 - 2022
- [j43]Nachiket V. Desai
, Han Wui Then, Jingshu Yu, Harish K. Krishnamurthy, William J. Lambert, Nicolas Butzen, Sheldon Weng, Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 32-A, 5-V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN nMOS Power Transistors. IEEE J. Solid State Circuits 57(4): 1090-1099 (2022) - [c80]Vida Ilderem, Stefano Pellerano, Jim Tschanz, Tanay Karnik, Vivek De:
Innovations for Intelligent Edge. ESSCIRC 2022: 41-44 - [c79]Amit Agarwal, Steven Hsu, Mark A. Anders, Gunjan Pandya, Ram Krishnamurthy, James W. Tschanz, Vivek De:
On-Chip High-Resolution Timing Characterization Circuits for Memory IPs. ESSCIRC 2022: 377-380 - [c78]Xiaosen Liu, Harish Krishnamurthy, Renzhi Liu, Krishnan Ravichandran, Zakir Ahmed, Nachiket V. Desai, Nicolas Butzen, James W. Tschanz, Vivek De:
A 0.76V Vin Triode Region 4A Analog LDO with Distributed Gain Enhancement and Dynamic Load-Current Tracking in Intel 4 CMOS Featuring Active Feedforward Ripple Shaping and On-Chip Power Noise Analyzer. ISSCC 2022: 478-480 - [c77]Steven Hsu, Amit Agarwal, Mark A. Anders, Arnab Raha, Raymond Sung, Deepak Mathaikutty, Ram Krishnamurthy, James W. Tschanz, Vivek De:
2.4GHz, Double-Buffered, 4kb Standard-Cell-Based Register File with Low-Power Mixed-Frequency Clocking for Machine Learning Accelerators. VLSI Technology and Circuits 2022: 22-23 - [c76]Nachiket V. Desai, Harish K. Krishnamurthy, Suhwan Kim, Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Fully Integrated Voltage Regulators with Package-Embedded Inductors for Heterogeneous 3D-TSV-Stacked System-in-Package with 22nm CMOS Active Silicon Interposer Featuring Self-Trimmed, Digitally Controlled ON-Time Discontinuous Conduction Mode (DCM) Operation. VLSI Technology and Circuits 2022: 192-193 - 2021
- [j42]Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Z. Ahmed, Christopher Schaef, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Universal Modular Hybrid LDO With Fast Load Transient Response and Programmable PSRR in 14-nm CMOS Featuring Dynamic Clamp Strength Tuning. IEEE J. Solid State Circuits 56(8): 2402-2415 (2021) - [j41]Sriram R. Vangal, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim:
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 843-856 (2021) - [j40]Saurabh Kumar, Minki Cho, Luke R. Everson, Andres Malavasi, Dan Lake, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De, Chris H. Kim:
A Back-Sampling Chain Technique for Accelerated Detection, Characterization, and Reconstruction of Radiation-Induced Transient Pulses. IEEE Trans. Very Large Scale Integr. Syst. 29(12): 2086-2097 (2021) - [c75]Nachiket V. Desai, Harish K. Krishnamurthy, Khondker Zakir Ahmed, Sheldon Weng, Suhwan Kim, Xiaosen Liu, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Peak-Current-Controlled Ganged Integrated High-Frequency Buck Voltage Regulators in 22nm CMOS for Robust Cross-Tile Current Sharing. ISSCC 2021: 262-264 - [c74]Khondker Zakir Ahmed, Nachiket V. Desai, Harish K. Krishnamurthy, Sheldon Weng, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Dual-Input, Digital Hybrid Buck-LDO System Featuring Fast Load Transient Response, Zero-Wire Current Handover & Input PDN Resonance Reduction. VLSI Circuits 2021: 1-2 - [c73]Charles Augustine, A. Afzal, U. Misgar, Abdullah A. Owahid, A. Raman, K. Subramanian, Feroze Merchant, James W. Tschanz, Muhammad M. Khellah:
All-Digital Closed-Loop Unified Retention/Wake-Up Clamp in a 10nm 4-Core x86 IP. VLSI Circuits 2021: 1-2 - [c72]Nachiket V. Desai, Harish K. Krishnamurthy, William J. Lambert, Jingshu Yu, Han Wui Then, Nicolas Butzen, Sheldon Weng, Christopher Schaef, N. Nidhi, Marko Radosavljevic, Johann Rode, Justin Sandford, Kaladhar Radhakrishnan, Krishnan Ravichandran, Bernhard Sell, James W. Tschanz, Vivek De:
A 32A 5V-Input, 94.2% Peak Efficiency High-Frequency Power Converter Module Featuring Package-Integrated Low-Voltage GaN NMOS Power Transistors. VLSI Circuits 2021: 1-2 - [c71]Suhwan Kim, Harish Krishnamurthy, Sally Amin, Sheldon Weng, Jin Feng, Huong Do, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 1S Direct-Battery-Attach Integrated Buck Voltage Regulator with 5-Stack Thin-Gate 22nm FinFET CMOS Featuring Active Voltage Balancing and Cascaded Self-Turn-ON Drivers. VLSI Circuits 2021: 1-2 - 2020
- [j39]Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22-nm CMOS With Fast Transient Response. IEEE J. Solid State Circuits 55(4): 977-987 (2020) - [j38]Suyoung Bang, Minki Cho, Pascal Andreas Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An All-Digital, $V_{\mathrm{MAX}}$ -Compliant, Stable, and Scalable Distributed Charge Injection Scheme in 10-nm CMOS for Fast and Local Mitigation of Voltage Droop. IEEE J. Solid State Circuits 55(7): 1898-1908 (2020) - [c70]Harish K. Krishnamurthy, Khondker Zakir Ahmed, Xiaosen Liu, Nachiket V. Desai, Suhwan Kim, Nicolas Butzen, Sally Amin, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Digital Control of Switching and Linear Integrated Voltage Regulators. CICC 2020: 1-4 - [c69]Samantak Gangopadhyay, James W. Tschanz, Arijit Raychowdhury:
A Quad-Output Elastic Switched Capacitor Converter and Per-Core LDO with 87% Power Efficiency and 2.5× Core-Frequency Range Improvement. ISCAS 2020: 1-5 - [c68]Suyoung Bang, Wootaek Lim, Charles Augustine, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
25.1 A Fully Synthesizable Distributed and Scalable All-Digital LDO in 10nm CMOS. ISSCC 2020: 380-382 - [c67]Zakir Zakir Ahmed, Harish K. Krishnamurthy, Sheldon Weng, Xiaosen Liu, Christopher Schaef, Nachiket V. Desai, Krishnan Ravichandran, James W. Tschanz, Vivek De:
An Autonomous Reconfigurable Power Delivery Network (RPDN) for Many-Core SoCs Featuring Dynamic Current Steering. VLSI Circuits 2020: 1-2 - [c66]Charles Augustine, Somnath Paul, Turbo Majumder, James W. Tschanz, Muhammad M. Khellah, Vivek De:
2X-Bandwidth Burst 6T-SRAM for Memory Bandwidth Limited Workloads. VLSI Circuits 2020: 1-2 - [c65]Jaydeep P. Kulkarni, Andres Malavasi, Charles Augustine, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah, Vivek De:
Low Swing and Column Multiplexed Bitline Techniques for Low-Vmin, Noise-Tolerant, High-Density, 1R1W 8T-Bitcell SRAM in 10nm FinFET CMOS. VLSI Circuits 2020: 1-2 - [c64]Xiaosen Liu, Harish K. Krishnamurthy, Claudia P. Barrera, Jing Han, Rajasekhara M. Narayana Bhatla, Scott Chiu, Khondker Zakir Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Dual-Rail Hybrid Analog/Digital LDO with Dynamic Current Steering for Tunable High PSRR and High Efficiency. VLSI Circuits 2020: 1-2 - [c63]Somnath Paul, Turbo Majumder, Charles Augustine, Andres F. Malavasi, S. Usirikayala, Raghavan Kumar, Jisna Kollikunnel, S. Chhabra, Satish Yada, M. L. Barajas, Carlos Ornelas, Dan Lake, Muhammad M. Khellah, Jim Tschanz, Vivek De:
A 0.05pJ/Pixel 70fps FHD 1Meps Event-Driven Visual Data Processing Unit. VLSI Circuits 2020: 1-2
2010 – 2019
- 2019
- [j37]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - [j36]Christopher Schaef, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De, Nachiket V. Desai, Harish K. Krishnamurthy, Xiaosen Liu, Khondker Zakir Ahmed, Suhwan Kim, Sheldon Weng, Huong Do, William J. Lambert:
A Light-Load Efficient Fully Integrated Voltage Regulator in 14-nm CMOS With 2.5-nH Package-Embedded Air-Core Inductors. IEEE J. Solid State Circuits 54(12): 3316-3325 (2019) - [c62]Suyoung Bang, Minki Cho, Pascal Meinerzhagen, Andres Malavasi, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An All-Digital, VMAX-Compliant, and Stable Distributed Charge Injection Scheme for Fast Mitigation of Voltage Droop. ESSCIRC 2019: 1-4 - [c61]Pascal Andreas Meinerzhagen, Sandip Kundu, Andres Malavasi, Trang Nguyen, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Min-Delay Margin/Error Detection and Correction for Flip-Flops and Pulsed Latches in 10-nm CMOS. ESSCIRC 2019: 1-4 - [c60]Christopher Schaef, Sheldon Weng, Beomseok Choi, William J. Lambert, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A 93.8% Peak Efficiency, 5V-Input, 10A Max ILOAD Flying Capacitor Multilevel Converter in 22nm CMOS Featuring Wide Output Voltage Range and Flying Capacitor Precharging. ISSCC 2019: 146-148 - [c59]Christopher Schaef, Nachiket V. Desai, Harish Krishnamurthy, Sheldon Weng, Huong Do, William J. Lambert, Kaladhar Radhakrishnan, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Fully Integrated Voltage Regulator in 14nm CMOS with Package-Embedded Air-Core Inductor Featuring Self-Trimmed, Digitally Controlled Variable On-Time Discontinuous Conduction Mode Operation. ISSCC 2019: 154-156 - [c58]Xiaosen Liu, Harish K. Krishnamurthy, Taesik Na, Sheldon Weng, Khondker Z. Ahmed, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Modular Hybrid LDO with Fast Load-Transient Response and Programmable PSRR in 14nm CMOS Featuring Dynamic Clamp Tuning and Time-Constant Compensation. ISSCC 2019: 234-236 - [c57]Khondker Zakir Ahmed, Harish K. Krishnamurthy, Charles Augustine, Xiaosen Liu, Sheldon Weng, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Variation-Adaptive Integrated Computational Digital LDO in 22nm CMOS with Fast Transient Response. VLSI Circuits 2019: 124- - 2018
- [j35]Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Pavan Kumar, Rinkle Jain, Sheldon Weng, Stephen T. Kim, George E. Matthew, Nachiket V. Desai, Xiaosen Liu, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With On-Die Solenoid Inductor With Planar Magnetic Core in 14-nm Tri-Gate CMOS. IEEE J. Solid State Circuits 53(1): 8-19 (2018) - [j34]Harish Kumar Krishnamurthy, Sheldon Weng, George E. Matthew, Nachiket V. Desai, Ruchir Saraswat, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Digitally Controlled Fully Integrated Voltage Regulator With 3-D-TSV-Based On-Die Solenoid Inductor With a Planar Magnetic Core for 3-D-Stacked Die Applications in 14-nm Tri-Gate CMOS. IEEE J. Solid State Circuits 53(4): 1038-1048 (2018) - [c56]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - [c55]Suhwan Kim, Vaibhav A. Vaidya, Christopher Schaef, Andrew Lines, Harish Krishnamurthy, Sheldon Weng, Xiaosen Liu, Dileep Kurian, Tanay Karnik, Krishnan Ravichandran, James W. Tschanz, Vivek De:
A Single-Stage, Single-Inductor, 6-Input 9-Output Multi-Modal Energy Harvesting Power Management IC for 100µW-120MW Battery-Powered IoT Edge Nodes. VLSI Circuits 2018: 195-196 - 2017
- [j33]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Postsilicon Voltage Guard-Band Reduction in a 22 nm Graphics Execution Core Using Adaptive Voltage Scaling and Dynamic Power Gating. IEEE J. Solid State Circuits 52(1): 50-63 (2017) - [j32]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De:
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE J. Solid State Circuits 52(4): 961-971 (2017) - [c54]Harish Kumar Krishnamurthy, Vaibhav A. Vaidya, Sheldon Weng, Krishnan Ravichandran, Pavan Kumar, Stephen T. Kim, Rinkle Jain, George E. Matthew, Jim Tschanz, Vivek De:
20.1 A digitally controlled fully integrated voltage regulator with on-die solenoid inductor with planar magnetic core in 14nm tri-gate CMOS. ISSCC 2017: 336-337 - 2016
- [j31]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Enabling Wide Autonomous DVFS in a 22 nm Graphics Execution Core Using a Digitally Controlled Fully Integrated Voltage Regulator. IEEE J. Solid State Circuits 51(1): 18-30 (2016) - [j30]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
A 409 GOPS/W Adaptive and Resilient Domino Register File in 22 nm Tri-Gate CMOS Featuring In-Situ Timing Margin and Error Detection for Tolerance to Within-Die Variation, Voltage Droop, Temperature and Aging. IEEE J. Solid State Circuits 51(1): 117-129 (2016) - [c53]Minki Cho, Stephen T. Kim, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.4 Post-silicon voltage-guard-band reduction in a 22nm graphics execution core using adaptive voltage scaling and dynamic power gating. ISSCC 2016: 152-153 - [c52]Minki Cho, Carlos Tokunaga, Stephen T. Kim, James W. Tschanz, Muhammad M. Khellah, Vivek De:
Adaptive clocking with dynamic power gating for mitigating energy efficiency & performance impacts of fast voltage droop in a 22nm graphics execution core. VLSI Circuits 2016: 1-2 - [c51]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De:
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - 2015
- [j29]Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, Krishnan Ravichandran, James W. Tschanz, Vivek De:
Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 50(8): 1809-1819 (2015) - [c50]Minki Cho, Carlos Tokunaga, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Aging-aware Adaptive Voltage Scaling in 22nm high-K/metal-gate tri-gate CMOS. CICC 2015: 1-4 - [c49]Alicia Klinefelter, Joseph F. Ryan, James W. Tschanz, Benton H. Calhoun:
Error-energy analysis of hardware logarithmic approximation methods for low power applications. ISCAS 2015: 2361-2364 - [c48]Farah B. Yahya, Mohammad M. Mansour, James W. Tschanz, Muhammad M. Khellah:
Designing low-VTh STT-RAM for write energy reduction in scaled technologies. ISQED 2015: 5-9 - [c47]Stephen T. Kim, Yi-Chun Shih, Kaushik Mazumdar, Rinkle Jain, Joseph F. Ryan, Carlos Tokunaga, Charles Augustine, Jaydeep P. Kulkarni, Krishnan Ravichandran, James W. Tschanz, Muhammad M. Khellah, Vivek De:
8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation. ISSCC 2015: 1-3 - [c46]Jaydeep P. Kulkarni, Carlos Tokunaga, Paolo A. Aseron, Trang Nguyen, Charles Augustine, James W. Tschanz, Vivek De:
4.7 A 409GOPS/W adaptive and resilient domino register file in 22nm tri-gate CMOS featuring in-situ timing margin and error detection for tolerance to within-die variation, voltage droop, temperature and aging. ISSCC 2015: 1-3 - [c45]Ahmed M. Ammar, Rafik Guindi, Ethan Shih, Carlos Tokunaga, Jim Tschanz, Muhammad M. Khellah:
A fully integrated charge sharing active decap scheme for power supply noise suppression. SoCC 2015: 374-379 - 2014
- [j28]Rinkle Jain, Bibiche M. Geuskens, Stephen T. Kim, Muhammad M. Khellah, Jaydeep Kulkarni, James W. Tschanz, Vivek De:
A 0.45-1 V Fully-Integrated Distributed Switched Capacitor DC-DC Converter With High Density MIM Capacitor in 22 nm Tri-Gate CMOS. IEEE J. Solid State Circuits 49(4): 917-927 (2014) - [j27]Samantak Gangopadhyay, Dinesh Somasekhar, James W. Tschanz, Arijit Raychowdhury:
A 32 nm Embedded, Fully-Digital, Phase-Locked Low Dropout Regulator for Fine Grained Power Management in Digital Circuits. IEEE J. Solid State Circuits 49(11): 2684-2693 (2014) - [c44]Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. ASP-DAC 2014: 388-389 - [c43]Rinkle Jain, Stephen T. Kim, Vaibhav A. Vaidya, James W. Tschanz, Krishnan Ravichandran, Vivek De:
Conductance modulation techniques in switched-capacitor DC-DC converter for maximum-efficiency tracking and ripple mitigation in 22nm Tri-gate CMOS. CICC 2014: 1-4 - [c42]Robert Pawlowski, Joseph Crop, Minki Cho, James W. Tschanz, Vivek De, Thomas Fairbanks, Heather Quinn, Shekhar Borkar, Patrick Yin Chiang:
Characterization of radiation-induced SRAM and logic soft errors from 0.33V to 1.0V in 65nm CMOS. CICC 2014: 1-4 - [c41]Carlos Tokunaga, Joseph F. Ryan, Charles Augustine, Jaydeep P. Kulkarni, Yi-Chun Shih, Stephen T. Kim, Rinkle Jain, Keith A. Bowman, Arijit Raychowdhury, Muhammad M. Khellah, James W. Tschanz, Vivek De:
5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep. ISSCC 2014: 108-109 - 2013
- [j26]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Tanay Karnik, Vivek K. De:
Adaptive and Resilient Circuits for Dynamic Variation Tolerance. IEEE Des. Test 30(6): 8-17 (2013) - [j25]Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, James W. Tschanz:
A 22 nm All-Digital Dynamically Adaptive Clock Distribution for Supply Voltage Droop Tolerance. IEEE J. Solid State Circuits 48(4): 907-916 (2013) - [j24]Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De:
A 2.3 nJ/Frame Voice Activity Detector-Based Audio Front-End for Context-Aware System-On-Chip Applications in 32-nm CMOS. IEEE J. Solid State Circuits 48(8): 1963-1969 (2013) - [c40]Chia-Hsiang Chen, Keith A. Bowman, Charles Augustine, Zhengya Zhang, Jim Tschanz:
Minimum supply voltage for sequential logic circuits in a 22nm technology. ISLPED 2013: 181-186 - 2012
- [c39]Minki Cho, Muhammad M. Khellah, Kwanyeob Chae, Khondker Zakir Ahmed, James W. Tschanz, Saibal Mukhopadhyay:
Characterization of Inverse Temperature Dependence in logic circuits. CICC 2012: 1-4 - [c38]Arijit Raychowdhury, Carlos Tokunaga, Willem Marco Beltman, Michael Deisher, James W. Tschanz, Vivek De:
A 2.3nJ/frame Voice Activity Detector based audio front-end for context-aware System-on-Chip applications in 32nm CMOS. CICC 2012: 1-4 - [c37]Michael Nicolaidis, Lorena Anghel, Nacer-Eddine Zergainoh, Yervant Zorian, Tanay Karnik, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Carlos Tokunaga, Arijit Raychowdhury, Muhammad M. Khellah, Jaydeep Kulkarni, Vivek De, Dimiter Avresky:
Design for test and reliability in ultimate CMOS. DATE 2012: 677-682 - [c36]Jaydeep Kulkarni, Bibiche M. Geuskens, Tanay Karnik, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Capacitive-coupling wordline boosting with self-induced VCC collapse for write VMIN reduction in 22-nm 8T SRAM. ISSCC 2012: 234-236 - [c35]Keith A. Bowman, Carlos Tokunaga, Tanay Karnik, Vivek K. De, Jim Tschanz:
A 22nm dynamically adaptive clock distribution for voltage droop tolerance. VLSIC 2012: 94-95 - [c34]Arijit Raychowdhury, Dinesh Somasekhar, James W. Tschanz, Vivek De:
A fully-digital phase-locked low dropout regulator in 32nm CMOS. VLSIC 2012: 148-149 - 2011
- [j23]Arijit Raychowdhury, Jim Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Error Detection and Correction in Microprocessor Core and Memory Due to Fast Dynamic Voltage Droops. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(3): 208-217 (2011) - [j22]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46(1): 184-193 (2011) - [j21]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek K. De:
A 45 nm Resilient Microprocessor Core for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 46(1): 194-208 (2011) - [j20]Arijit Raychowdhury, Bibiche M. Geuskens, Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Tanay Karnik, Muhammad M. Khellah, Vivek K. De:
Tunable Replica Bits for Dynamic Variation Tolerance in 8T SRAM Arrays. IEEE J. Solid State Circuits 46(4): 797-805 (2011) - [j19]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek K. De:
All-Digital Circuit-Level Dynamic Variation Monitor for Silicon Debug and Adaptive Clock Control. IEEE Trans. Circuits Syst. I Regul. Pap. 58-I(9): 2017-2025 (2011) - 2010
- [c33]James W. Tschanz, Keith A. Bowman, Muhammad M. Khellah, Chris Wilkerson, Bibiche M. Geuskens, Dinesh Somasekhar, Arijit Raychowdhury, Jaydeep Kulkarni, Carlos Tokunaga, Shih-Lien Lu, Tanay Karnik, Vivek De:
Resilient design in scaled CMOS for energy efficiency. ASP-DAC 2010: 625 - [c32]Keith A. Bowman, Carlos Tokunaga, James W. Tschanz, Arijit Raychowdhury, Muhammad M. Khellah, Bibiche M. Geuskens, Shih-Lien Lu, Paolo A. Aseron, Tanay Karnik, Vivek De:
Dynamic variation monitor for measuring the impact of voltage droops on microprocessor clock frequency. CICC 2010: 1-4 - [c31]James W. Tschanz:
Energy-efficient processing through adaptation and resiliency. Green Computing Conference 2010: 533 - [c30]Keith A. Bowman, James W. Tschanz:
Resilient microprocessor design for improving performance and energy efficiency. ICCAD 2010: 85-88 - [c29]Keith A. Bowman, James W. Tschanz, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
Resilient microprocessor design for high performance & energy efficiency. ISLPED 2010: 355-356 - [c28]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175 - [c27]James W. Tschanz, Keith A. Bowman, Shih-Lien Lu, Paolo A. Aseron, Muhammad M. Khellah, Arijit Raychowdhury, Bibiche M. Geuskens, Carlos Tokunaga, Chris Wilkerson, Tanay Karnik, Vivek De:
A 45nm resilient and adaptive microprocessor core for dynamic variation tolerance. ISSCC 2010: 282-283 - [c26]Arijit Raychowdhury, Bibiche M. Geuskens, Jaydeep Kulkarni, James W. Tschanz, Keith A. Bowman, Tanay Karnik, Shih-Lien Lu, Vivek De, Muhammad M. Khellah:
PVT-and-aging adaptive wordline boosting for 8T SRAM power reduction. ISSCC 2010: 352-353
2000 – 2009
- 2009
- [j18]Yu Cao, Jim Tschanz, Pradip Bose:
Guest Editors' Introduction: Reliability Challenges in Nano-CMOS Design. IEEE Des. Test Comput. 26(6): 6-7 (2009) - [j17]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Resilient Circuits for Dynamic Variation Tolerance. IEEE J. Solid State Circuits 44(1): 49-63 (2009) - [j16]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Serial-Link Bus: A Low-Power On-Chip Bus Architecture. IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(9): 2020-2032 (2009) - [c25]Keith A. Bowman, James W. Tschanz, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek De, Shekhar Y. Borkar:
Circuit techniques for dynamic variation tolerance. DAC 2009: 4-7 - [c24]James W. Tschanz, Keith A. Bowman, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik:
Resilient circuits - Enabling energy-efficient performance and reliability. ICCAD 2009: 71-73 - 2008
- [j15]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar:
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits 43(1): 29-41 (2008) - [j14]Jianping Xu, Peter Hazucha, Zuoguo Wu, Paolo A. Aseron, Mingwei Huang, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Vivek De, Tanay Karnik, Greg Taylor:
A Band-Limited Active Damping Circuit With 13 dB Power Supply Resonance Reduction. IEEE J. Solid State Circuits 43(1): 61-68 (2008) - [j13]Jaume Abella, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González, James W. Tschanz:
Refueling: Preventing Wire Degradation due to Electromigration. IEEE Micro 28(6): 37-46 (2008) - [j12]Maged Ghoneima, Muhammad M. Khellah, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail, Vivek K. De:
Skewed Repeater Bus: A Low-Power Scheme for On-Chip Buses. IEEE Trans. Circuits Syst. I Regul. Pap. 55-I(7): 1904-1910 (2008) - [c23]Abhisek Pan, James W. Tschanz, Sandip Kundu:
A Low Cost Scheme for Reducing Silent Data Corruption in Large Arithmetic Circuit. DFT 2008: 343-351 - [c22]Subhasish Mitra, Ravishankar K. Iyer, Kishor S. Trivedi, James W. Tschanz:
Reliable system design: models, metrics and design techniques. ICCAD 2008: 3 - [c21]Keith A. Bowman, James W. Tschanz, Nam-Sung Kim, Janice C. Lee, Chris Wilkerson, Shih-Lien Lu, Tanay Karnik, Vivek K. De:
Energy-Efficient and Metastability-Immune Timing-Error Detection and Instruction-Replay-Based Recovery Circuits for Dynamic-Variation Tolerance. ISSCC 2008: 402-403 - 2007
- [j11]Muhammad M. Khellah, Dinesh Somasekhar, Yibin Ye, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Murad Sunna, James W. Tschanz, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 256-Kb Dual-VCC SRAM Building Block in 65-nm CMOS Process With Actively Clamped Sleep Transistor. IEEE J. Solid State Circuits 42(1): 233-242 (2007) - [c20]Steven M. Burns, Mahesh Ketkar, Noel Menezes, Keith A. Bowman, James W. Tschanz, Vivek De:
Comparative Analysis of Conventional and Statistical Design Techniques. DAC 2007: 238-243 - [c19]Ming Zhang, T. M. Mak, James W. Tschanz, Kee Sup Kim, Norbert Seifert, Davia Lu:
Design for Resilience to Soft Errors and Variations. IOLTS 2007: 23-28 - [c18]Gerhard Knoblinger, James W. Tschanz, Marcal Pol:
SUB-45nm Technology and Design Challenges. ISQED 2007: 3 - [c17]James W. Tschanz:
SUB 45nm Low Power Design Challenges. ISQED 2007: 4 - [c16]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar:
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. ISSCC 2007: 98-589 - [c15]Jianping Xu, Peter Hazucha, Mingwei Huang, Paolo A. Aseron, Fabrice Paillet, Gerhard Schrom, James W. Tschanz, Cangsang Zhao, Vivek De, Tanay Karnik, Greg Taylor:
On-Die Supply-Resonance Suppression Using Band-Limited Active Damping. ISSCC 2007: 286-603 - [c14]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - 2006
- [j10]Osman S. Unsal, James W. Tschanz, Keith A. Bowman, Vivek De, Xavier Vera, Antonio González, Oguz Ergin:
Impact of Parameter Variations on Circuits and Microarchitecture. IEEE Micro 26(6): 30-39 (2006) - [j9]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Formal derivation of optimal active shielding for low-power on-chip buses. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(5): 821-836 (2006) - [j8]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Reducing the Effective Coupling Capacitance in Buses Using Threshold Voltage Adjustment Techniques. IEEE Trans. Circuits Syst. I Regul. Pap. 53-I(9): 1928-1933 (2006) - [c13]Keith A. Bowman, James W. Tschanz, Muhammad M. Khellah, Maged Ghoneima, Yehea I. Ismail, Vivek De:
Time-borrowing multi-cycle on-chip interconnects for delay variation tolerance. ISLPED 2006: 79-84 - [c12]Muhammad M. Khellah, Nam-Sung Kim, Jason Howard, Gregory Ruhl, Yibin Ye, James W. Tschanz, Dinesh Somasekhar, Nitin Borkar, Fatih Hamzaoglu, Gunjan Pandya, Ali Farhang, Kevin Zhang, Vivek De:
A 4.2GHz 0.3mm2 256kb Dual-Vcc SRAM Building Block in 65nm CMOS. ISSCC 2006: 2572-2581 - [c11]James W. Tschanz:
Session Abstract. VTS 2006: 378-379 - 2005
- [c10]James W. Tschanz, Keith A. Bowman, Vivek De:
Variation-tolerant circuits: circuit solutions and techniques. DAC 2005: 762-763 - [c9]Maged Ghoneima, Yehea I. Ismail, Muhammad M. Khellah, James W. Tschanz, Vivek De:
Serial-link bus: a low-power on-chip bus architecture. ICCAD 2005: 541-546 - [c8]Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Nasser A. Kurd, Javed Barkatullah, Srikanth Nimmagadda, Yehea I. Ismail:
A Skewed Repeater Bus Architecture for On-Chip Energy Reduction in Microprocessors. ICCD 2005: 253-257 - [c7]James W. Tschanz, Siva G. Narendra, Ali Keshavarzi, Vivek De:
Adaptive circuit techniques to minimize variation impacts on microprocessor performance and power. ISCAS (1) 2005: 9-12 - [c6]Yehea I. Ismail, Muhammad M. Khellah, Maged Ghoneima, James W. Tschanz, Yibin Ye, Vivek De:
Skewing adjacent line repeaters to reduce the delay and energy dissipation of on-chip buses. ISCAS (1) 2005: 592-595 - 2004
- [j7]Peter Hazucha, Tanay Karnik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Gregory E. Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER-tolerant latch in a 90-nm dual-VT CMOS process. IEEE J. Solid State Circuits 39(9): 1536-1543 (2004) - [c5]Siva G. Narendra, Vasantha Erraguntla, James W. Tschanz, Nitin Borkar:
Design Challenges in Sub-100nm High Performance Microprocessors. VLSI Design 2004: 15-17 - 2003
- [j6]James W. Tschanz, Siva G. Narendra, Raj Nair, Vivek De:
Effectiveness of adaptive supply voltage and body bias for reducing impact of parameter variations in low power and high performance microprocessors. IEEE J. Solid State Circuits 38(5): 826-829 (2003) - [j5]James W. Tschanz, Siva G. Narendra, Yibin Ye, Bradley A. Bloechel, Shekhar Borkar, Vivek De:
Dynamic sleep transistor and body bias for active leakage power control of microprocessors. IEEE J. Solid State Circuits 38(11): 1838-1845 (2003) - [j4]Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar:
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. IEEE J. Solid State Circuits 38(11): 1866-1875 (2003) - [c4]Peter Hazucha, Tanay Kamik, Steven Walstra, Bradley A. Bloechel, James W. Tschanz, Jose Maiz, Krishnamurthy Soumyanath, Greg Dermer, Siva G. Narendra, Vivek De, Shekhar Borkar:
Measurements and analysis of SER tolerant latch in a 90 nm dual-Vt CMOS process. CICC 2003: 617-620 - [c3]Shekhar Borkar, Tanay Karnik, Siva G. Narendra, James W. Tschanz, Ali Keshavarzi, Vivek De:
Parameter variations and impact on circuits and microarchitecture. DAC 2003: 338-342 - 2002
- [j3]Ali Keshavarzi, James W. Tschanz, Siva G. Narendra, Vivek De, W. Robert Daasch, Kaushik Roy, Manoj Sachdev, Charles F. Hawkins:
Leakage and Process Variation Effects in Current Testing on Future CMOS Circuits. IEEE Des. Test Comput. 19(5): 36-43 (2002) - [j2]James W. Tschanz, James T. Kao, Siva G. Narendra, Raj Nair, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Vivek De:
Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage. IEEE J. Solid State Circuits 37(11): 1396-1402 (2002) - [j1]Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar:
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. IEEE J. Solid State Circuits 37(11): 1421-1432 (2002) - [c2]Tanay Karnik, Yibin Ye, James W. Tschanz, Liqiong Wei, Steven M. Burns, Venkatesh Govindarajulu, Vivek De, Shekhar Borkar:
Total power optimization by simultaneous dual-Vt allocation and device sizing in high performance microprocessors. DAC 2002: 486-491 - 2001
- [c1]James W. Tschanz, Siva G. Narendra, Zhanping Chen, Shekhar Borkar, Manoj Sachdev, Vivek De:
Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors. ISLPED 2001: 147-152
Coauthor Index
Khondker Zakir Ahmed
aka: Khondker Z. Ahmed
aka: Khondker Z. Ahmed
Shekhar Borkar
aka: Shekhar Y. Borkar
aka: Shekhar Y. Borkar
Vivek De
aka: Vivek K. De
aka: Vivek K. De
[c87] [c85] [c84] [c83] [c81] [j43] [c80] [c79] [c78] [c77] [c76] [j42] [j41] [j40] [c75] [c74] [c72] [c71] [j39] [j38] [c70] [c68] [c67] [c66] [c65] [c64] [c63] [j37] [j36] [c62] [c61] [c60] [c59] [c58] [c57] [j35] [j34] [c56] [c55] [j33] [j32] [c54] [j31] [j30] [c53] [c52] [c51] [j29] [c50] [c47] [c46] [j28] [c44] [c43] [c42] [c41] [j26] [j25] [j24] [c38] [c37] [c36] [c35] [c34] [j23] [j22] [j21] [j20] [j19] [c33] [c32] [c29] [c28] [c27] [c26] [j17] [j16] [c25] [j14] [j12] [c21] [j11] [c20] [c15] [c14] [j10] [j9] [j8] [c13] [c12] [c10] [c9] [c7] [c6] [j7] [j6] [j5] [c4] [c3] [j3] [j2] [j1] [c2] [c1]
Jaydeep P. Kulkarni
aka: Jaydeep Kulkarni
aka: Jaydeep Kulkarni
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