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ORCIDSriram R. Vangal
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2020 – today
- 2021
[j15]Sriram R. Vangal
, Somnath Paul, Steven Hsu, Amit Agarwal, Saurabh Kumar, Ram Krishnamurthy, Harish Krishnamurthy, James W. Tschanz, Vivek De, Chris H. Kim:
Wide-Range Many-Core SoC Design in Scaled CMOS: Challenges and Opportunities. IEEE Trans. Very Large Scale Integr. Syst. 29(5): 843-856 (2021)- [c15]Sriram R. Vangal, Long Yan, Frederic Gianesello:
Session 12 Overview: Innovations in Low-Power and Secure IoT Technology Directions Subcommittee. ISSCC 2021: 198-199
2010 – 2019
- 2019
- [j14]Pascal Andreas Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Xiang Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An Energy-Efficient Graphics Processor in 14-nm Tri-Gate CMOS Featuring Integrated Voltage Regulators for Fine-Grain DVFS, Retentive Sleep, and ${V}_{\text{MIN}}$ Optimization. IEEE J. Solid State Circuits 54(1): 144-157 (2019) - [j13]Pedram Mohseni, Sriram R. Vangal:
Introduction to the Special Section on the 2019 IEEE International Solid-State Circuits Conference (ISSCC). IEEE J. Solid State Circuits 54(11): 2919-2920 (2019) - 2018
- [c14]Pascal Meinerzhagen, Carlos Tokunaga, Andres Malavasi, Vaibhav A. Vaidya, Ashwin Mendon, Deepak Mathaikutty, Jaydeep Kulkarni, Charles Augustine, Minki Cho, Stephen T. Kim, George E. Matthew, Rinkle Jain, Joseph F. Ryan, Chung-Ching Peng, Somnath Paul, Sriram R. Vangal, Brando Perez Esparza, Luis Cuellar, Michael Woodman, Bala Iyer, Subramaniam Maiyuran, Gautham N. Chinya, Chris Zou, Yuyun Liao, Krishnan Ravichandran, Hong Wang, Muhammad M. Khellah, James W. Tschanz, Vivek De:
An energy-efficient graphics processor featuring fine-grain DVFS with integrated voltage regulators, execution-unit turbo, and retentive sleep in 14nm tri-gate CMOS. ISSCC 2018: 38-40 - [e1]Zhonghai Lu, Sriram R. Vangal, Jiang Xu, Paul Bogdan:
Twelfth IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2018, Torino, Italy, October 4-5, 2018. IEEE 2018, ISBN 978-1-5386-4893-3 [contents] - 2017
- [j12]Vivek De, Sriram R. Vangal, Ram Krishnamurthy:
Near Threshold Voltage (NTV) Computing: Computing in the Dark Silicon Era. IEEE Des. Test 34(2): 24-30 (2017) - [j11]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Tao Wang, Sriram R. Vangal, James W. Tschanz, Vivek De:
A Sub-cm3 Energy-Harvesting Stacked Wireless Sensor Node Featuring a Near-Threshold Voltage IA-32 Microcontroller in 14-nm Tri-Gate CMOS for Always-ON Always-Sensing Applications. IEEE J. Solid State Circuits 52(4): 961-971 (2017) - 2016
- [c13]Somnath Paul, Vinayak Honkote, Ryan Gary Kim, Turbo Majumder, Paolo A. Aseron, Vaughn Grossnickle, Robert Sankman, Debendra Mallik, Sandeep Jain, Sriram R. Vangal, James W. Tschanz, Vivek De:
An energy harvesting wireless sensor node for IoT systems featuring a near-threshold voltage IA-32 microcontroller in 14nm tri-gate CMOS. VLSI Circuits 2016: 1-2 - [c12]Mehdi Baradaran Tahoori, Rob Aitken, Sriram R. Vangal, Bal Sandhu:
Test implications and challenges in near threshold computing special session. VTS 2016: 1 - 2014
- [c11]Tanay Karnik, James W. Tschanz, Nitin Borkar, Jason Howard, Sriram R. Vangal, Vivek De, Shekhar Borkar:
Resiliency for many-core system on a chip. ASP-DAC 2014: 388-389 - [c10]Sriram R. Vangal, Shailendra Jain, Vivek De:
A solar-powered 280mV-to-1.2V wide-operating-range IA-32 processor. ICICDT 2014: 1-4 - 2013
- [j10]Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Sriram R. Vangal:
IA-32 Processor with a Wide-Voltage-Operating Range in 32-nm CMOS. IEEE Micro 33(2): 28-36 (2013) - 2012
- [c9]Gregory Ruhl, Saurabh Dighe, Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Paolo A. Aseron, Howard Wilson, Nitin Borkar:
An IA-32 processor with a wide voltage operating range in 32nm CMOS. Hot Chips Symposium 2012: 1-37 - [c8]Shailendra Jain, Surhud Khare, Satish Yada, V. Ambili, Praveen Salihundam, Shiva Ramani, Sriram Muthukumar, M. Srinivasan, Arun Kumar, Shasi Kumar, Rajaraman Ramanarayanan, Vasantha Erraguntla, Jason Howard, Sriram R. Vangal, Saurabh Dighe, Gregory Ruhl, Paolo A. Aseron, Howard Wilson, Nitin Borkar, Vivek De, Shekhar Borkar:
A 280mV-to-1.2V wide-operating-range IA-32 processor in 32nm CMOS. ISSCC 2012: 66-68 - [c7]Praveen Salihundam, Mohammed Asadullah Khan, Shailendra Jain, Yatin Vasant Hoskote, Satish Yada, Shasi Kumar, Vasantha Erraguntla, Sriram R. Vangal, Nitin Borkar:
A Reconfigurable On-die Traffic Generator in 45nm CMOS for a 48 iA-32 Core Network-on-Chip. VLSI Design 2012: 292-297 - 2011
- [j9]Jason Howard, Saurabh Dighe, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar, Shailendra Jain, Vasantha Erraguntla, Michael Konow, Michael Riepen, Matthias Gries, Guido Droege, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek K. De, Rob F. Van der Wijngaart:
A 48-Core IA-32 Processor in 45 nm CMOS Using On-Die Message-Passing and DVFS for Performance and Power Scaling. IEEE J. Solid State Circuits 46(1): 173-183 (2011) - [j8]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek K. De, Shekhar Borkar:
Within-Die Variation-Aware Dynamic-Voltage-Frequency-Scaling With Optimal Core Allocation and Thread Hopping for the 80-Core TeraFLOPS Processor. IEEE J. Solid State Circuits 46(1): 184-193 (2011) - [j7]Praveen Salihundam, Shailendra Jain, Tiju Jacob, Shasi Kumar, Vasantha Erraguntla, Yatin Vasant Hoskote, Sriram R. Vangal, Gregory Ruhl, Nitin Borkar:
A 2 Tb/s 6 , ˟, 4 Mesh Network for a Single-Chip Cloud Computer With DVFS in 45 nm CMOS. IEEE J. Solid State Circuits 46(4): 757-766 (2011) - 2010
- [j6]Partha Pratim Pande, Sriram R. Vangal:
Guest Editors' Introduction: Promises and Challenges of Novel Interconnect Technologies. IEEE Des. Test Comput. 27(4): 6-9 (2010) - [c6]Jason Howard, Saurabh Dighe, Yatin Vasant Hoskote, Sriram R. Vangal, David Finan, Gregory Ruhl, David Jenkins, Howard Wilson, Nitin Borkar, Gerhard Schrom, Fabric Pailet, Shailendra Jain, Tiju Jacob, Satish Yada, Sraven Marella, Praveen Salihundam, Vasantha Erraguntla, Michael Konow, Michael Riepen, Guido Droege, Joerg Lindemann, Matthias Gries, Thomas Apel, Kersten Henriss, Tor Lund-Larsen, Sebastian Steibl, Shekhar Borkar, Vivek De, Rob F. Van der Wijngaart, Timothy G. Mattson:
A 48-Core IA-32 message-passing processor with DVFS in 45nm CMOS. ISSCC 2010: 108-109 - [c5]Saurabh Dighe, Sriram R. Vangal, Paolo A. Aseron, Shasi Kumar, Tiju Jacob, Keith A. Bowman, Jason Howard, James W. Tschanz, Vasantha Erraguntla, Nitin Borkar, Vivek De, Shekhar Borkar:
Within-die variation-aware dynamic-voltage-frequency scaling core mapping and thread hopping for an 80-core processor. ISSCC 2010: 174-175 - [c4]Timothy G. Mattson, Michael Riepen, Thomas Lehnig, Paul Brett, Werner Haas, Patrick Kennedy, Jason Howard, Sriram R. Vangal, Nitin Borkar, Gregory Ruhl, Saurabh Dighe:
The 48-core SCC Processor: the Programmer's View. SC 2010: 1-11 - [c3]Shailendra Jain, Vasantha Erraguntla, Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Tulasi Mandepudi, V. P. Karthik:
A 90mW/GFlop 3.4GHz Reconfigurable Fused/Continuous Multiply-Accumulator for Floating-Point and Integer Operands in 65nm. VLSI Design 2010: 252-257
2000 – 2009
- 2009
- [p1]Li-Shiuan Peh, Stephen W. Keckler, Sriram R. Vangal:
On-Chip Networks for Multicore Systems. Multicore Processors and Systems 2009: 35-71 - 2008
- [j5]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Vasantha Erraguntla, Clark Roberts, Yatin Vasant Hoskote, Nitin Borkar, Shekhar Borkar:
An 80-Tile Sub-100-W TeraFLOPS Processor in 65-nm CMOS. IEEE J. Solid State Circuits 43(1): 29-41 (2008) - 2007
- [j4]Yatin Hoskote, Sriram R. Vangal, Arvind P. Singh, Nitin Borkar, Shekhar Borkar:
A 5-GHz Mesh Interconnect for a Teraflops Processor. IEEE Micro 27(5): 51-61 (2007) - [c2]Sriram R. Vangal, Jason Howard, Gregory Ruhl, Saurabh Dighe, Howard Wilson, James W. Tschanz, David Finan, Priya Iyer, Arvind P. Singh, Tiju Jacob, Shailendra Jain, Sriram Venkataraman, Yatin Hoskote, Nitin Borkar:
An 80-Tile 1.28TFLOPS Network-on-Chip in 65nm CMOS. ISSCC 2007: 98-589 - [c1]James W. Tschanz, Nam-Sung Kim, Saurabh Dighe, Jason Howard, Gregory Ruhl, Sriram R. Vangal, Siva G. Narendra, Yatin Hoskote, Howard Wilson, Carol Lam, Matthew Shuman, Carlos Tokunaga, Dinesh Somasekhar, Stephen Tang, David Finan, Tanay Karnik, Nitin Borkar, Nasser A. Kurd, Vivek De:
Adaptive Frequency and Biasing Techniques for Tolerance to Dynamic Temperature-Voltage Variations and Aging. ISSCC 2007: 292-604 - 2006
- [j3]Sriram R. Vangal, Yatin Vasant Hoskote, Nitin Borkar, Atila Alvandpour:
A 6.2-GFlops Floating-Point Multiply-Accumulator With Conditional Normalization. IEEE J. Solid State Circuits 41(10): 2314-2323 (2006) - 2003
- [j2]Yatin Vasant Hoskote, Bradley A. Bloechel, Gregory E. Dermer, Vasantha Erraguntla, David Finan, Jason Howard, Dan Klowden, Siva G. Narendra, Greg Ruhl, James W. Tschanz, Sriram R. Vangal, Venkat Veeramachaneni, Howard Wilson, Jianping Xu, Nitin Borkar:
A TCP offload accelerator for 10 Gb/s Ethernet in 90-nm CMOS. IEEE J. Solid State Circuits 38(11): 1866-1875 (2003) - 2002
- [j1]Sriram R. Vangal, Mark A. Anders, Nitin Borkar, Erik Seligman, Venkatesh Govindarajulu, Vasantha Erraguntla, Howard Wilson, Amaresh Pangal, Venkat Veeramachaneni, James W. Tschanz, Yibin Ye, Dinesh Somasekhar, Bradley A. Bloechel, Gregory E. Dermer, Ram K. Krishnamurthy, Krishnamurthy Soumyanath, Sanu Mathew, Siva G. Narendra, Mircea R. Stan, Scott Thompson, Vivek De, Shekhar Borkar:
5-GHz 32-bit integer execution core in 130-nm dual-VT CMOS. IEEE J. Solid State Circuits 37(11): 1421-1432 (2002)
Coauthor Index
aka: Vivek K. De
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