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1/* SPDX-License-Identifier: GPL-2.0 */
2/*
3 * Copyright (c) 2012, The Linux Foundation. All rights reserved.
4 */
5
6#ifndef _LINUX_CORESIGHT_H
7#define _LINUX_CORESIGHT_H
8
9#include <linux/amba/bus.h>
10#include <linux/clk.h>
11#include <linux/device.h>
12#include <linux/io.h>
13#include <linux/perf_event.h>
14#include <linux/sched.h>
15#include <linux/platform_device.h>
16
17/* Peripheral id registers (0xFD0-0xFEC) */
18#define CORESIGHT_PERIPHIDR4 0xfd0
19#define CORESIGHT_PERIPHIDR5 0xfd4
20#define CORESIGHT_PERIPHIDR6 0xfd8
21#define CORESIGHT_PERIPHIDR7 0xfdC
22#define CORESIGHT_PERIPHIDR0 0xfe0
23#define CORESIGHT_PERIPHIDR1 0xfe4
24#define CORESIGHT_PERIPHIDR2 0xfe8
25#define CORESIGHT_PERIPHIDR3 0xfeC
26/* Component id registers (0xFF0-0xFFC) */
27#define CORESIGHT_COMPIDR0 0xff0
28#define CORESIGHT_COMPIDR1 0xff4
29#define CORESIGHT_COMPIDR2 0xff8
30#define CORESIGHT_COMPIDR3 0xffC
31
32#define ETM_ARCH_V3_3 0x23
33#define ETM_ARCH_V3_5 0x25
34#define PFT_ARCH_V1_0 0x30
35#define PFT_ARCH_V1_1 0x31
36
37#define CORESIGHT_UNLOCK 0xc5acce55
38
39extern const struct bus_type coresight_bustype;
40
41enum coresight_dev_type {
42 CORESIGHT_DEV_TYPE_SINK,
43 CORESIGHT_DEV_TYPE_LINK,
44 CORESIGHT_DEV_TYPE_LINKSINK,
45 CORESIGHT_DEV_TYPE_SOURCE,
46 CORESIGHT_DEV_TYPE_HELPER,
47 CORESIGHT_DEV_TYPE_MAX
48};
49
50enum coresight_dev_subtype_sink {
51 CORESIGHT_DEV_SUBTYPE_SINK_DUMMY,
52 CORESIGHT_DEV_SUBTYPE_SINK_PORT,
53 CORESIGHT_DEV_SUBTYPE_SINK_BUFFER,
54 CORESIGHT_DEV_SUBTYPE_SINK_SYSMEM,
55 CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM,
56};
57
58enum coresight_dev_subtype_link {
59 CORESIGHT_DEV_SUBTYPE_LINK_MERG,
60 CORESIGHT_DEV_SUBTYPE_LINK_SPLIT,
61 CORESIGHT_DEV_SUBTYPE_LINK_FIFO,
62};
63
64enum coresight_dev_subtype_source {
65 CORESIGHT_DEV_SUBTYPE_SOURCE_PROC,
66 CORESIGHT_DEV_SUBTYPE_SOURCE_BUS,
67 CORESIGHT_DEV_SUBTYPE_SOURCE_SOFTWARE,
68 CORESIGHT_DEV_SUBTYPE_SOURCE_TPDM,
69 CORESIGHT_DEV_SUBTYPE_SOURCE_OTHERS,
70};
71
72enum coresight_dev_subtype_helper {
73 CORESIGHT_DEV_SUBTYPE_HELPER_CATU,
74 CORESIGHT_DEV_SUBTYPE_HELPER_ECT_CTI,
75 CORESIGHT_DEV_SUBTYPE_HELPER_CTCU,
76};
77
78/**
79 * union coresight_dev_subtype - further characterisation of a type
80 * @sink_subtype: type of sink this component is, as defined
81 * by @coresight_dev_subtype_sink.
82 * @link_subtype: type of link this component is, as defined
83 * by @coresight_dev_subtype_link.
84 * @source_subtype: type of source this component is, as defined
85 * by @coresight_dev_subtype_source.
86 * @helper_subtype: type of helper this component is, as defined
87 * by @coresight_dev_subtype_helper.
88 */
89union coresight_dev_subtype {
90 /* We have some devices which acts as LINK and SINK */
91 struct {
92 enum coresight_dev_subtype_sink sink_subtype;
93 enum coresight_dev_subtype_link link_subtype;
94 };
95 enum coresight_dev_subtype_source source_subtype;
96 enum coresight_dev_subtype_helper helper_subtype;
97};
98
99/**
100 * struct coresight_platform_data - data harvested from the firmware
101 * specification.
102 *
103 * @nr_inconns: Number of elements for the input connections.
104 * @nr_outconns: Number of elements for the output connections.
105 * @out_conns: Array of nr_outconns pointers to connections from this
106 * component.
107 * @in_conns: Sparse array of pointers to input connections. Sparse
108 * because the source device owns the connection so when it's
109 * unloaded the connection leaves an empty slot.
110 */
111struct coresight_platform_data {
112 int nr_inconns;
113 int nr_outconns;
114 struct coresight_connection **out_conns;
115 struct coresight_connection **in_conns;
116};
117
118/**
119 * struct csdev_access - Abstraction of a CoreSight device access.
120 *
121 * @io_mem : True if the device has memory mapped I/O
122 * @base : When io_mem == true, base address of the component
123 * @read : Read from the given "offset" of the given instance.
124 * @write : Write "val" to the given "offset".
125 */
126struct csdev_access {
127 bool io_mem;
128 union {
129 void __iomem *base;
130 struct {
131 u64 (*read)(u32 offset, bool relaxed, bool _64bit);
132 void (*write)(u64 val, u32 offset, bool relaxed,
133 bool _64bit);
134 };
135 };
136};
137
138#define CSDEV_ACCESS_IOMEM(_addr) \
139 ((struct csdev_access) { \
140 .io_mem = true, \
141 .base = (_addr), \
142 })
143
144/**
145 * struct coresight_desc - description of a component required from drivers
146 * @type: as defined by @coresight_dev_type.
147 * @subtype: as defined by @coresight_dev_subtype.
148 * @ops: generic operations for this component, as defined
149 * by @coresight_ops.
150 * @pdata: platform data collected from DT.
151 * @dev: The device entity associated to this component.
152 * @groups: operations specific to this component. These will end up
153 * in the component's sysfs sub-directory.
154 * @name: name for the coresight device, also shown under sysfs.
155 * @access: Describe access to the device
156 */
157struct coresight_desc {
158 enum coresight_dev_type type;
159 union coresight_dev_subtype subtype;
160 const struct coresight_ops *ops;
161 struct coresight_platform_data *pdata;
162 struct device *dev;
163 const struct attribute_group **groups;
164 const char *name;
165 struct csdev_access access;
166};
167
168/**
169 * struct coresight_connection - representation of a single connection
170 * @src_port: a connection's output port number.
171 * @dest_port: destination's input port number @src_port is connected to.
172 * @dest_fwnode: destination component's fwnode handle.
173 * @dest_dev: a @coresight_device representation of the component
174 connected to @src_port. NULL until the device is created
175 * @link: Representation of the connection as a sysfs link.
176 * @filter_src_fwnode: filter source component's fwnode handle.
177 * @filter_src_dev: a @coresight_device representation of the component that
178 needs to be filtered.
179 *
180 * The full connection structure looks like this, where in_conns store
181 * references to same connection as the source device's out_conns.
182 *
183 * +-----------------------------+ +-----------------------------+
184 * |coresight_device | |coresight_connection |
185 * |-----------------------------| |-----------------------------|
186 * | | | |
187 * | | | dest_dev*|<--
188 * |pdata->out_conns[nr_outconns]|<->|src_dev* | |
189 * | | | | |
190 * +-----------------------------+ +-----------------------------+ |
191 * |
192 * +-----------------------------+ |
193 * |coresight_device | |
194 * |------------------------------ |
195 * | | |
196 * | pdata->in_conns[nr_inconns]|<--
197 * | |
198 * +-----------------------------+
199 */
200struct coresight_connection {
201 int src_port;
202 int dest_port;
203 struct fwnode_handle *dest_fwnode;
204 struct coresight_device *dest_dev;
205 struct coresight_sysfs_link *link;
206 struct coresight_device *src_dev;
207 struct fwnode_handle *filter_src_fwnode;
208 struct coresight_device *filter_src_dev;
209 int src_refcnt;
210 int dest_refcnt;
211};
212
213/**
214 * struct coresight_sysfs_link - representation of a connection in sysfs.
215 * @orig: Originating (master) coresight device for the link.
216 * @orig_name: Name to use for the link orig->target.
217 * @target: Target (slave) coresight device for the link.
218 * @target_name: Name to use for the link target->orig.
219 */
220struct coresight_sysfs_link {
221 struct coresight_device *orig;
222 const char *orig_name;
223 struct coresight_device *target;
224 const char *target_name;
225};
226
227/* architecturally we have 128 IDs some of which are reserved */
228#define CORESIGHT_TRACE_IDS_MAX 128
229
230/**
231 * Trace ID map.
232 *
233 * @used_ids: Bitmap to register available (bit = 0) and in use (bit = 1) IDs.
234 * Initialised so that the reserved IDs are permanently marked as
235 * in use.
236 * @perf_cs_etm_session_active: Number of Perf sessions using this ID map.
237 */
238struct coresight_trace_id_map {
239 DECLARE_BITMAP(used_ids, CORESIGHT_TRACE_IDS_MAX);
240 atomic_t __percpu *cpu_map;
241 atomic_t perf_cs_etm_session_active;
242 raw_spinlock_t lock;
243};
244
245/**
246 * struct coresight_device - representation of a device as used by the framework
247 * @pdata: Platform data with device connections associated to this device.
248 * @type: as defined by @coresight_dev_type.
249 * @subtype: as defined by @coresight_dev_subtype.
250 * @ops: generic operations for this component, as defined
251 * by @coresight_ops.
252 * @access: Device i/o access abstraction for this device.
253 * @dev: The device entity associated to this component.
254 * @mode: The device mode, i.e sysFS, Perf or disabled. This is actually
255 * an 'enum cs_mode' but stored in an atomic type. Access is always
256 * through atomic APIs, ensuring SMP-safe synchronisation between
257 * racing from sysFS and Perf mode. A compare-and-exchange
258 * operation is done to atomically claim one mode or the other.
259 * @refcnt: keep track of what is in use. Only access this outside of the
260 * device's spinlock when the coresight_mutex held and mode ==
261 * CS_MODE_SYSFS. Otherwise it must be accessed from inside the
262 * spinlock.
263 * @orphan: true if the component has connections that haven't been linked.
264 * @sysfs_sink_activated: 'true' when a sink has been selected for use via sysfs
265 * by writing a 1 to the 'enable_sink' file. A sink can be
266 * activated but not yet enabled. Enabling for a _sink_ happens
267 * when a source has been selected and a path is enabled from
268 * source to that sink. A sink can also become enabled but not
269 * activated if it's used via Perf.
270 * @ea: Device attribute for sink representation under PMU directory.
271 * @def_sink: cached reference to default sink found for this device.
272 * @nr_links: number of sysfs links created to other components from this
273 * device. These will appear in the "connections" group.
274 * @has_conns_grp: Have added a "connections" group for sysfs links.
275 * @feature_csdev_list: List of complex feature programming added to the device.
276 * @config_csdev_list: List of system configurations added to the device.
277 * @cscfg_csdev_lock: Protect the lists of configurations and features.
278 * @active_cscfg_ctxt: Context information for current active system configuration.
279 */
280struct coresight_device {
281 struct coresight_platform_data *pdata;
282 enum coresight_dev_type type;
283 union coresight_dev_subtype subtype;
284 const struct coresight_ops *ops;
285 struct csdev_access access;
286 struct device dev;
287 atomic_t mode;
288 int refcnt;
289 bool orphan;
290 /* sink specific fields */
291 bool sysfs_sink_activated;
292 struct dev_ext_attribute *ea;
293 struct coresight_device *def_sink;
294 struct coresight_trace_id_map perf_sink_id_map;
295 /* sysfs links between components */
296 int nr_links;
297 bool has_conns_grp;
298 /* system configuration and feature lists */
299 struct list_head feature_csdev_list;
300 struct list_head config_csdev_list;
301 raw_spinlock_t cscfg_csdev_lock;
302 void *active_cscfg_ctxt;
303};
304
305/*
306 * coresight_dev_list - Mapping for devices to "name" index for device
307 * names.
308 *
309 * @nr_idx: Number of entries already allocated.
310 * @pfx: Prefix pattern for device name.
311 * @fwnode_list: Array of fwnode_handles associated with each allocated
312 * index, upto nr_idx entries.
313 */
314struct coresight_dev_list {
315 int nr_idx;
316 const char *pfx;
317 struct fwnode_handle **fwnode_list;
318};
319
320#define DEFINE_CORESIGHT_DEVLIST(var, dev_pfx) \
321static struct coresight_dev_list (var) = { \
322 .pfx = dev_pfx, \
323 .nr_idx = 0, \
324 .fwnode_list = NULL, \
325}
326
327#define to_coresight_device(d) container_of(d, struct coresight_device, dev)
328
329/**
330 * struct coresight_path - data needed by enable/disable path
331 * @path_list: path from source to sink.
332 * @trace_id: trace_id of the whole path.
333 * @handle: handle of the aux_event.
334 */
335struct coresight_path {
336 struct list_head path_list;
337 u8 trace_id;
338 struct perf_output_handle *handle;
339};
340
341enum cs_mode {
342 CS_MODE_DISABLED,
343 CS_MODE_SYSFS,
344 CS_MODE_PERF,
345};
346
347#define coresight_ops(csdev) csdev->ops
348#define source_ops(csdev) csdev->ops->source_ops
349#define sink_ops(csdev) csdev->ops->sink_ops
350#define link_ops(csdev) csdev->ops->link_ops
351#define helper_ops(csdev) csdev->ops->helper_ops
352#define ect_ops(csdev) csdev->ops->ect_ops
353#define panic_ops(csdev) csdev->ops->panic_ops
354
355/**
356 * struct coresight_ops_sink - basic operations for a sink
357 * Operations available for sinks
358 * @enable: enables the sink.
359 * @disable: disables the sink.
360 * @alloc_buffer: initialises perf's ring buffer for trace collection.
361 * @free_buffer: release memory allocated in @get_config.
362 * @update_buffer: update buffer pointers after a trace session.
363 */
364struct coresight_ops_sink {
365 int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
366 struct coresight_path *path);
367 int (*disable)(struct coresight_device *csdev);
368 void *(*alloc_buffer)(struct coresight_device *csdev,
369 struct perf_event *event, void **pages,
370 int nr_pages, bool overwrite);
371 void (*free_buffer)(void *config);
372 unsigned long (*update_buffer)(struct coresight_device *csdev,
373 struct perf_output_handle *handle,
374 void *sink_config);
375};
376
377/**
378 * struct coresight_ops_link - basic operations for a link
379 * Operations available for links.
380 * @enable: enables flow between iport and oport.
381 * @disable: disables flow between iport and oport.
382 */
383struct coresight_ops_link {
384 int (*enable)(struct coresight_device *csdev,
385 struct coresight_connection *in,
386 struct coresight_connection *out);
387 void (*disable)(struct coresight_device *csdev,
388 struct coresight_connection *in,
389 struct coresight_connection *out);
390};
391
392/**
393 * struct coresight_ops_source - basic operations for a source
394 * Operations available for sources.
395 * @cpu_id: returns the value of the CPU number this component
396 * is associated to.
397 * @enable: enables tracing for a source.
398 * @disable: disables tracing for a source.
399 * @resume_perf: resumes tracing for a source in perf session.
400 * @pause_perf: pauses tracing for a source in perf session.
401 */
402struct coresight_ops_source {
403 int (*cpu_id)(struct coresight_device *csdev);
404 int (*enable)(struct coresight_device *csdev, struct perf_event *event,
405 enum cs_mode mode, struct coresight_path *path);
406 void (*disable)(struct coresight_device *csdev,
407 struct perf_event *event);
408 int (*resume_perf)(struct coresight_device *csdev);
409 void (*pause_perf)(struct coresight_device *csdev);
410};
411
412/**
413 * struct coresight_ops_helper - Operations for a helper device.
414 *
415 * All operations could pass in a device specific data, which could
416 * help the helper device to determine what to do.
417 *
418 * @enable : Enable the device
419 * @disable : Disable the device
420 */
421struct coresight_ops_helper {
422 int (*enable)(struct coresight_device *csdev, enum cs_mode mode,
423 struct coresight_path *path);
424 int (*disable)(struct coresight_device *csdev,
425 struct coresight_path *path);
426};
427
428
429/**
430 * struct coresight_ops_panic - Generic device ops for panic handing
431 *
432 * @sync : Sync the device register state/trace data
433 */
434struct coresight_ops_panic {
435 int (*sync)(struct coresight_device *csdev);
436};
437
438struct coresight_ops {
439 int (*trace_id)(struct coresight_device *csdev, enum cs_mode mode,
440 struct coresight_device *sink);
441 const struct coresight_ops_sink *sink_ops;
442 const struct coresight_ops_link *link_ops;
443 const struct coresight_ops_source *source_ops;
444 const struct coresight_ops_helper *helper_ops;
445 const struct coresight_ops_panic *panic_ops;
446};
447
448static inline u32 csdev_access_relaxed_read32(struct csdev_access *csa,
449 u32 offset)
450{
451 if (likely(csa->io_mem))
452 return readl_relaxed(csa->base + offset);
453
454 return csa->read(offset, true, false);
455}
456
457#define CORESIGHT_CIDRn(i) (0xFF0 + ((i) * 4))
458
459static inline u32 coresight_get_cid(void __iomem *base)
460{
461 u32 i, cid = 0;
462
463 for (i = 0; i < 4; i++)
464 cid |= readl(addr: base + CORESIGHT_CIDRn(i)) << (i * 8);
465
466 return cid;
467}
468
469static inline bool is_coresight_device(void __iomem *base)
470{
471 u32 cid = coresight_get_cid(base);
472
473 return cid == CORESIGHT_CID;
474}
475
476#define CORESIGHT_PIDRn(i) (0xFE0 + ((i) * 4))
477
478static inline u32 coresight_get_pid(struct csdev_access *csa)
479{
480 u32 i, pid = 0;
481
482 for (i = 0; i < 4; i++)
483 pid |= csdev_access_relaxed_read32(csa, CORESIGHT_PIDRn(i)) << (i * 8);
484
485 return pid;
486}
487
488static inline u64 csdev_access_relaxed_read_pair(struct csdev_access *csa,
489 u32 lo_offset, u32 hi_offset)
490{
491 if (likely(csa->io_mem)) {
492 return readl_relaxed(csa->base + lo_offset) |
493 ((u64)readl_relaxed(csa->base + hi_offset) << 32);
494 }
495
496 return csa->read(lo_offset, true, false) | (csa->read(hi_offset, true, false) << 32);
497}
498
499static inline void csdev_access_relaxed_write_pair(struct csdev_access *csa, u64 val,
500 u32 lo_offset, u32 hi_offset)
501{
502 if (likely(csa->io_mem)) {
503 writel_relaxed((u32)val, csa->base + lo_offset);
504 writel_relaxed((u32)(val >> 32), csa->base + hi_offset);
505 } else {
506 csa->write((u32)val, lo_offset, true, false);
507 csa->write((u32)(val >> 32), hi_offset, true, false);
508 }
509}
510
511static inline u32 csdev_access_read32(struct csdev_access *csa, u32 offset)
512{
513 if (likely(csa->io_mem))
514 return readl(addr: csa->base + offset);
515
516 return csa->read(offset, false, false);
517}
518
519static inline void csdev_access_relaxed_write32(struct csdev_access *csa,
520 u32 val, u32 offset)
521{
522 if (likely(csa->io_mem))
523 writel_relaxed(val, csa->base + offset);
524 else
525 csa->write(val, offset, true, false);
526}
527
528static inline void csdev_access_write32(struct csdev_access *csa, u32 val, u32 offset)
529{
530 if (likely(csa->io_mem))
531 writel(val, addr: csa->base + offset);
532 else
533 csa->write(val, offset, false, false);
534}
535
536#ifdef CONFIG_64BIT
537
538static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
539 u32 offset)
540{
541 if (likely(csa->io_mem))
542 return readq_relaxed(csa->base + offset);
543
544 return csa->read(offset, true, true);
545}
546
547static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
548{
549 if (likely(csa->io_mem))
550 return readq(addr: csa->base + offset);
551
552 return csa->read(offset, false, true);
553}
554
555static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
556 u64 val, u32 offset)
557{
558 if (likely(csa->io_mem))
559 writeq_relaxed(val, csa->base + offset);
560 else
561 csa->write(val, offset, true, true);
562}
563
564static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
565{
566 if (likely(csa->io_mem))
567 writeq(val, addr: csa->base + offset);
568 else
569 csa->write(val, offset, false, true);
570}
571
572#else /* !CONFIG_64BIT */
573
574static inline u64 csdev_access_relaxed_read64(struct csdev_access *csa,
575 u32 offset)
576{
577 WARN_ON(1);
578 return 0;
579}
580
581static inline u64 csdev_access_read64(struct csdev_access *csa, u32 offset)
582{
583 WARN_ON(1);
584 return 0;
585}
586
587static inline void csdev_access_relaxed_write64(struct csdev_access *csa,
588 u64 val, u32 offset)
589{
590 WARN_ON(1);
591}
592
593static inline void csdev_access_write64(struct csdev_access *csa, u64 val, u32 offset)
594{
595 WARN_ON(1);
596}
597#endif /* CONFIG_64BIT */
598
599static inline bool coresight_is_device_source(struct coresight_device *csdev)
600{
601 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SOURCE);
602}
603
604static inline bool coresight_is_percpu_source(struct coresight_device *csdev)
605{
606 return csdev && coresight_is_device_source(csdev) &&
607 (csdev->subtype.source_subtype == CORESIGHT_DEV_SUBTYPE_SOURCE_PROC);
608}
609
610static inline bool coresight_is_percpu_sink(struct coresight_device *csdev)
611{
612 return csdev && (csdev->type == CORESIGHT_DEV_TYPE_SINK) &&
613 (csdev->subtype.sink_subtype == CORESIGHT_DEV_SUBTYPE_SINK_PERCPU_SYSMEM);
614}
615
616/*
617 * Atomically try to take the device and set a new mode. Returns true on
618 * success, false if the device is already taken by someone else.
619 */
620static inline bool coresight_take_mode(struct coresight_device *csdev,
621 enum cs_mode new_mode)
622{
623 int curr = CS_MODE_DISABLED;
624
625 return atomic_try_cmpxchg_acquire(v: &csdev->mode, old: &curr, new: new_mode);
626}
627
628static inline enum cs_mode coresight_get_mode(struct coresight_device *csdev)
629{
630 return atomic_read_acquire(v: &csdev->mode);
631}
632
633static inline void coresight_set_mode(struct coresight_device *csdev,
634 enum cs_mode new_mode)
635{
636 enum cs_mode current_mode = coresight_get_mode(csdev);
637
638 /*
639 * Changing to a new mode must be done from an already disabled state
640 * unless it's synchronized with coresight_take_mode(). Otherwise the
641 * device is already in use and signifies a locking issue.
642 */
643 WARN(new_mode != CS_MODE_DISABLED && current_mode != CS_MODE_DISABLED &&
644 current_mode != new_mode, "Device already in use\n");
645
646 atomic_set_release(v: &csdev->mode, i: new_mode);
647}
648
649struct coresight_device *coresight_register(struct coresight_desc *desc);
650void coresight_unregister(struct coresight_device *csdev);
651int coresight_enable_sysfs(struct coresight_device *csdev);
652void coresight_disable_sysfs(struct coresight_device *csdev);
653int coresight_timeout(struct csdev_access *csa, u32 offset, int position, int value);
654typedef void (*coresight_timeout_cb_t) (struct csdev_access *, u32, int, int);
655int coresight_timeout_action(struct csdev_access *csa, u32 offset, int position, int value,
656 coresight_timeout_cb_t cb);
657int coresight_claim_device(struct coresight_device *csdev);
658int coresight_claim_device_unlocked(struct coresight_device *csdev);
659
660int coresight_claim_device(struct coresight_device *csdev);
661int coresight_claim_device_unlocked(struct coresight_device *csdev);
662void coresight_clear_self_claim_tag(struct csdev_access *csa);
663void coresight_clear_self_claim_tag_unlocked(struct csdev_access *csa);
664void coresight_disclaim_device(struct coresight_device *csdev);
665void coresight_disclaim_device_unlocked(struct coresight_device *csdev);
666char *coresight_alloc_device_name(struct coresight_dev_list *devs,
667 struct device *dev);
668
669bool coresight_loses_context_with_cpu(struct device *dev);
670
671u32 coresight_relaxed_read32(struct coresight_device *csdev, u32 offset);
672u32 coresight_read32(struct coresight_device *csdev, u32 offset);
673void coresight_write32(struct coresight_device *csdev, u32 val, u32 offset);
674void coresight_relaxed_write32(struct coresight_device *csdev,
675 u32 val, u32 offset);
676u64 coresight_relaxed_read64(struct coresight_device *csdev, u32 offset);
677u64 coresight_read64(struct coresight_device *csdev, u32 offset);
678void coresight_relaxed_write64(struct coresight_device *csdev,
679 u64 val, u32 offset);
680void coresight_write64(struct coresight_device *csdev, u64 val, u32 offset);
681
682int coresight_get_cpu(struct device *dev);
683int coresight_get_static_trace_id(struct device *dev, u32 *id);
684
685struct coresight_platform_data *coresight_get_platform_data(struct device *dev);
686struct coresight_connection *
687coresight_add_out_conn(struct device *dev,
688 struct coresight_platform_data *pdata,
689 const struct coresight_connection *new_conn);
690int coresight_add_in_conn(struct coresight_connection *conn);
691struct coresight_device *
692coresight_find_input_type(struct coresight_platform_data *pdata,
693 enum coresight_dev_type type,
694 union coresight_dev_subtype subtype);
695struct coresight_device *
696coresight_find_output_type(struct coresight_platform_data *pdata,
697 enum coresight_dev_type type,
698 union coresight_dev_subtype subtype);
699
700int coresight_init_driver(const char *drv, struct amba_driver *amba_drv,
701 struct platform_driver *pdev_drv, struct module *owner);
702
703void coresight_remove_driver(struct amba_driver *amba_drv,
704 struct platform_driver *pdev_drv);
705int coresight_etm_get_trace_id(struct coresight_device *csdev, enum cs_mode mode,
706 struct coresight_device *sink);
707int coresight_get_enable_clocks(struct device *dev, struct clk **pclk,
708 struct clk **atclk);
709#endif /* _LINUX_COREISGHT_H */
710

source code of linux/include/linux/coresight.h