PRAVIN ROHIDAS PATIL COLLEGE OF DEGREE ENGG.

& TECHNOLOGY

THE INTEL MICROPROCESSORS 8086

ARCHITECTURE &
INSTRUCTION SET AND PROGRAMMING

CHAPTER 1 – THE INTEL MICROPROCESSORS 8086 ARCHITECTURE

CHAPTER 2 – INSTRUCTION SET AND PROGRAMMING
SUBJECT – MICROPROCESSOR (CSC405)
SEMESTER – FOURTH
BY– MRS PRACHI KALPANDE

1
8086 MICROPROCESSOR
 THE 8086 MICROPROCESSORS
• A microprocessor is an electronic component that is used by a
computer to do its work.
• It is a central processing unit on a single integrated circuit chip
containing millions of very small components including
transistors, resistors, and diodes that work together.
Evolution of Microprocessor
 THE 8086 MICROPROCESSORS
FEATURES OF 8086
• The 8086 is a 16 bit processor.
• The 8086 has a 16 bit Data bus.
• The 8086 has a 20 bit Address bus.
• Direct addressing capability 1 M Byte of Memory (220)
• It provides fourteen 16-bit register.
• 24 Operand addressing modes.
• Four general-purpose 16-bit registers: AX, BX, CX, DX
• Available in 40pin Plastic Package and Lead Chip.
ARCHITECTURE
8086 Microprocessor
ARCHITECTURE

Execution Unit (EU) Bus Interface Unit (BIU)

EU executes instructions that have BIU fetches instructions, reads data

already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
8
8086 ARCHITECTURE
 8086 ARCHITECTURE
8086 PROCESSOR ARE PARTITIONED LOGICALLY
INTO TWO PROCESSING UNITS
• Bus Interface Unit (BIU)
The BIU fetches instructions, reads data from
memory and ports, and writes data to memory
and I/O ports.
• Execution Unit (EU)
EU receives program instruction codes and data
from the BIU, executes these instructions and stores
the results either in the general registers or output
them through the BIU. EU has no connections to the
system buses.
 8086 ARCHITECTURE
The BIU contains
• Segment registers
• Instruction pointer
• Instruction queue
The EU contains
• ALU
• General purpose registers
• Index registers
• Pointers
• Flag register
 8086 ARCHITECTURE
General Purpose Registers
All general registers of the 8086 microprocessor can be used for arithmetic and
logic operations.
• Accumulator register (AX)

Accumulator can be used for I/O operations and string manipulation.

• Base register (BX)

BX register usually contains a data pointer used for based, based indexed or
register indirect addressing.
• Count register (CX)

Count register can be used as a counter in string manipulation and

shift/rotate instructions.
• Data register (DX)

Data register can be used as a port number in I/O operations.

 8086 ARCHITECTURE
Segment Registers:
Most of the registers contain data/instruction offsets within 64
KB memory segment. There are four different 64 KB segments
for instructions, stack, data and extra data.
• Code segment (CS)
The CS register is automatically updated during FAR JUMP,
FAR CALL and FAR RET instructions.
• Stack segment (SS)
SS register can be changed directly using POP instruction.
• Data segment (DS)
DS register can be changed directly using POP and LDS
instructions.
• Extra segment (ES)
ES register can be changed directly using POP and LES
instructions.
 8086 ARCHITECTURE
POINTER REGISTERS
Stack Pointer (SP)
It is a 16-bit register pointing to program stack.
Base Pointer (BP)
It is a 16-bit register pointing to data in the stack segment. BP
register is usually used for based, based indexed or register
indirect addressing.
Index Registers
Source Index (SI)
It is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in
string manipulation instructions.
Destination Index (DI)
It is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data
address in string manipulation instructions.
 8086 ARCHITECTURE
INSTRUCTION POINTER (IP)
It is a 16-bit register. The operation is same as the
program counter. The IP register is updated by the
BIU to point to the address of the next instruction.
Programs do not have direct access to the IP, but
during execution of a program the IP can be
modified or saved and restored from the stack.
FLAG REGISTER
It is a 16-bit register containing nine 1-bit flags:
• Six status or condition flags (OF, SF, ZF, AF, PF, CF)
• Three control flags ( TF, DF, IF)
 8086 ARCHITECTURE
FLAG REGISTER
It is a 16-bit register containing nine 1-bit flags:
• Six status or condition flags (OF, SF, ZF, AF, PF, CF)
• Three control flags ( TF, DF, IF)
 FLAG REGISTER
• Overflow Flag (OF) - set if the result is too large positive
number,
or is too small negative number to fit into destination
operand.
• Sign Flag (SF) - set if the most significant bit of the
result is set.
• Zero Flag (ZF) - set if the result is zero.
• Auxiliary carry Flag (AF) - set if there was a carry from
or borrow
to bits 0-3 in the AL register.
• Parity Flag (PF) - set if parity (the number of “1” bits) in
the low- order byte of the result is even.
 FLAG REGISTER
• Carry Flag (CF) - set if there was a carry from or borrow
to the
most significant bit during last result calculation.
• Trap or Single-step Flag (TF) - if set then single-step
interrupt will occur after the next instruction.
• Direction Flag (DF) - if set then string manipulation
instructions will auto-decrement index registers. If
cleared then the index registers will be auto-
incremented.
• Interrupt-enable Flag (IF) - setting this bit enables
maskable
interrupts.
INSTRUCTION STREAM BYTE QUEUE
Instruction Queue
The instruction queue is a First-In-First-out
(FIFO) group of registers where 6 bytes of
instruction code is pre-fetched from
memory ahead of time.
It is being done to speed-up program
execution by overlapping instruction fetch
and execution.
This mechanism is known as PIPELINING.
 THE QUEUE (Q)
• The BIU uses a mechanism known as an
instruction stream queue to implement a pipeline
architecture.
• This queue permits pre-fetch of up to 6 bytes of
instruction code.
• Whenever the queue of the BIU is not full, it has
room for at least two more bytes and at the same
time the EU is not requesting it to read or write
operands from memory, the BIU is free to look
ahead in the program by pre-fetching the next
sequential instruction.
• These pre-fetching instructions are held in its FIFO
queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.

• After a byte is loaded at the input end of the queue,

it automatically shifts up through the FIFO to the
empty location nearest the output.

• The EU accesses the queue from the output

end. It reads one instruction byte after the other
from the output of the queue.

• The intervals of no bus activity, which may occur

between bus cycles are known as Idle state.
 Fig a) Non-pipelined execution of 3 instructions

F D E F D E F D E

I1 I1 I1 I2 I2 I2 I3 I3 I3
Clock 1 2 3 4 5 6 7 8 9
cycle

Fig b) Pipelined execution of 3 instructions

F I1 I2 I3 I4 I5 F - Fetch

I1 I2 I3 I4 D - Decode
D

E I1 I2 I3 E - Execute

Clock 1 2 3 4 5
cycle
 ALU AND CONTROL UNIT
ALU
It is a 16 bit register. It can add, subtract,
increment, decrement, complement, shift
numbers and performs AND, OR, XOR
operations.
Control unit
The control unit in the EU directs the
internal operations like RD , WR , M/IO.
 INTERRUPTS
Interrupts
Hardware interrupts
Maskable and non-maskable interrupts
Software interrupts
 INTERRUPTS
❑ An interrupt is an event that occurs while the processor is executing a program
❑The interrupt temporarily suspends execution of the program and switch the
processor to executing a special routine (interrupt service routine)
❑When the execution of interrupt service routine is complete, the processor
resumes the execution of the original program
❑ Interrupt classification.

Hardware Interrupts Software Interrupts

⎯ Caused by activating the processor’s ⎯ Caused by the execution of an INT
interrupt control signals (NMI, instruction
INTR) ⎯ Caused by an event which is generated
by the execution of a program, such
as division by zero

❑ 8088 can have 256

interrupts
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Dedicated Adder to
generate 20 bit address

Four 16-bit segment

registers

Code Segment (CS)

Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)

Segment Registers >> 27

 8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Segment
Registers

• 8086’s 1-megabyte memory • The 8086 can directly address four • Programs obtain access to code
is divided into segments of segments (256 K bytes within the 1 and data in the segments by
up to 64K bytes each. M byte of memory) at a particular changing the segment register
time. content to point to the desired
segments.

28
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Segment Code Segment Register
Registers
• 16-bit

• CS contains the base or start of the current code segment; IP contains the
distance or offset from this address to the next instruction byte to be fetched.

• BIU computes the 20-bit physical address by logically shifting the contents of CS
4-bits to the left and then adding the 16-bit contents of IP.

• That is, all instructions of a program are relative to the contents of the CS
register multiplied by 16 and then offset is added provided by the IP.

29
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Segment Data Segment Register
Registers
• 16-bit

• Points to the current data segment; operands for most instructions are fetched
from this segment.

• The 16-bit contents of the Source Index (SI) or Destination Index (DI) or a 16-bit
displacement are used as offset for computing the 20-bit physical address.

30
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Segment Stack Segment Register
Registers
• 16-bit

• Points to the current stack.

• The 20-bit physical stack address is calculated from the Stack Segment (SS) and
the Stack Pointer (SP) for stack instructions such as PUSH and POP.

• In based addressing mode, the 20-bit physical stack address is calculated from
the Stack segment (SS) and the Base Pointer (BP).

31
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Segment Extra Segment Register
Registers
• 16-bit

• Points to the extra segment in which data (in excess of 64K pointed to by the
DS) is stored.

• String instructions use the ES and DI to determine the 20-bit physical address
for the destination.

32
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Segment Instruction Pointer
Registers
• 16-bit

• Always points to the next instruction to be executed

within the currently executing code segment.

• So, this register contains the 16-bit offset address

pointing to the next instruction code within the 64Kb of
the code segment area.

• Its content is automatically incremented as the execution

of the next instruction takes place.

33
8086 Microprocessor
ARCHITECTURE
Bus Interface Unit (BIU)
Instruction queue

• A group of First-In-First-Out (FIFO)

in which up to 6 bytes of
instruction code are pre fetched
from the memory ahead of time.

• This is done in order to speed up

the execution by overlapping
instruction fetch with execution.

• This mechanism is known as

pipelining.

34
8086 Microprocessor
ARCHITECTURE
Execution Unit (EU)
EU decodes and
executes instructions.

A decoder in the EU
control system
translates instructions.

16-bit ALU for

performing arithmetic
and logic operation

Four general purpose

registers(AX, BX, CX, DX);

Pointer registers (Stack

Pointer, Base Pointer);

and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL 35
DX can be used as DH and DL
8086 Microprocessor
ARCHITECTURE
Execution Unit (EU)
EU Accumulator Register (AX)
Registers
• Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.

• AL in this case contains the low order byte of the word,

and AH contains the high-order byte.

• The I/O instructions use the AX or AL for inputting /

outputting 16 or 8 bit data to or from an I/O port.

• Multiplication and Division instructions also use the AX or

AL.

36
8086 Microprocessor
ARCHITECTURE
Execution Unit (EU)
EU Base Register (BX)
Registers
• Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.

• BL in this case contains the low-order byte of the word,

and BH contains the high-order byte.

• This is the only general purpose register whose contents

can be used for addressing the 8086 memory.

• All memory references utilizing this register content for

addressing use DS as the default segment register.

37
8086 Microprocessor
Execution Unit (EU)

EU Counter Register (CX)

Registers
• Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.

• When combined, CL register contains the low order byte

of the word, and CH contains the high-order byte.

• Instructions such as SHIFT, ROTATE and LOOP use the

contents of CX as a counter.

Example:

The instruction LOOP START automatically decrements

CX by 1 without affecting flags and will check if [CX] =
0.

If it is zero, 8086 executes the next instruction;

otherwise the 8086 branches to the label START.

38
8086 Microprocessor
ARCHITECTURE
Execution Unit (EU)
EU
Registers

39
8086 Microprocessor

Execution Unit (EU)

EU Stack Pointer (SP) and Base Pointer (BP)
Registers
• SP and BP are used to access data in the stack segment.

• SP is used as an offset from the current SS during

execution of instructions that involve the stack segment
in the external memory.

• SP contents are automatically updated (incremented/

decremented) due to execution of a POP or PUSH
instruction.

• BP contains an offset address in the current SS, which is

used by instructions utilizing the based addressing mode.

40
8086 Microprocessor
ARCHITECTURE
Execution Unit (EU)
EU Source Index (SI) and Destination Index (DI)
Registers
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

41
8086 Microprocessor
ARCHITECTURE
Execution Unit (EU)
EU Source Index (SI) and Destination Index (DI)
Registers
• Used in indexed addressing.

• Instructions that process data strings use the SI and DI

registers together with DS and ES respectively in order to
distinguish between the source and destination
addresses.

42
MEMORY ADDRESS GENERATION
Offset Value (16 bits)

Segment Register (16 bits) 0000

Adder

Physical Address (20 Bits)

43
MEMORY ADDRESS GENERATION

44
• The following examples shows the CS:IP scheme
of address formation:
CS 34BA IP 8AB4 Code segment
34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D654

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F

45
8086 Microprocessor
FLAG REGISTER
Architecture Auxiliary Carry Flag

This is set, if there is a carry from the

Carry Flag

lowest nibble, i.e, bit three during This flag is set, when there is
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case of
subtraction. subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

× × × × OF DF IF TF SF ZF × AF × PF
× CF

Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 46
8086 Microprocessor
8086 REGISTERS
8086 registers
categorized
into 4 groups 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

47
8086 Microprocessor
REGISTERS AND SPECIAL FUNCTIONS

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic operations

BX Base register Used to hold base value in base addressing mode to

access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE and LOOP
instructions

DX Data Register Used to hold data for multiplication and division operations

SP Stack Pointer Used to hold the offset address of top stack memory

BP Base Pointer Used to hold the base value in base addressing using SS
register to access data from stack memory

SI Source Index Used to hold index value of source operand (data) for string
instructions

DI Data Index Used to hold the index value of destination operand (data)
for string operations 48
 MEMORY
8086 Microprocessor

Processor Memory
▪ Registers inside a microcomputer
▪ Store data and results temporarily
▪ No speed disparity
▪ Cost ↑

Primary or Main Memory

▪ Storage area which can be directly accessed by
Memory microprocessor
▪ Store programs and data prior to execution
Store Programs
▪ Should not have speed disparity with processor ⇒
and Data
Semi Conductor memories using CMOS technology
▪ ROM, EPROM, Static RAM, DRAM

Secondary Memory
▪ Storage media comprising of slow devices such as
magnetic tapes and disks
▪ Hold large data files and programs: Operating
system, compilers, databases, permanent
programs etc.
49
8086 Microprocessor
MEMORY ORGANIZATION IN 8086

50
8086 Microprocessor
MEMORY ORGANIZATION IN 8086

Operation BHE A0 Data Lines Used

1 Read/ Write byte at an even address 1 0 D7 – D0

2 Read/ Write byte at an odd address 0 1 D15 – D8

3 Read/ Write word at an even address 0 0 D15 – D0

4 Read/ Write word at an odd address 0 1 D15 – D0 in first operation byte

from odd bank is transferred

1 0 D7 – D0 in first operation byte

from odd bank is transferred
51
 BUS INTERFACE UNIT (BIU)

• The function of BIU is to:

• Fetch the instruction or data from memory
• Write the data to memory
• Write the data to the port
• Read data from the port
 EXECUTION UNIT (EU)

• The functions of execution unit are:

• To tell BIU where to fetch the instructions or data from.
• To decode the instructions.
• To execute the instructions.
The EU contains the control circuitry to perform various
internal operations.
Pins and signals
8086 Microprocessor
Pins and Signals
Common signals

AD0-AD15 (Bidirectional)

Address/Data bus

Low order address bus; these are

multiplexed with data.

When AD lines are used to transmit

memory address the symbol A is used
instead of AD, for example A0-A15.

When data are transmitted over AD lines

the symbol D is used in place of AD, for
example D0-D7, D8-D15 or D0-D15.

A16/S3, A17/S4, A18/S5, A19/S6

High order address bus. These are

multiplexed with status signals

55
8086 Microprocessor
Pins and Signals
Common signals BHE (Active Low)/S7 (Output)

Bus High Enable/Status

It is used to enable data onto the most

significant half of data bus, D8-D15. 8-bit
device connected to upper half of the
data bus use BHE (Active Low) signal. It
is multiplexed with status signal S7.

MN/ MX

MINIMUM / MAXIMUM

This pin signal indicates what mode the

processor is to operate in.

RD (Read) (Active Low)

The signal is used for read operation.

It is an output signal.
It is active when low.
56
8086 Microprocessor
Pins and Signals
Common signals

READY

This is the acknowledgement from the

slow device or memory that they have
completed the data transfer.

The signal made available by the devices

is synchronized by the 8284A clock
generator to provide ready input to the
8086.

The signal is active high. 57

8086 Microprocessor
Pins and Signals
Common signals RESET (Input)

Causes the processor to immediately

terminate its present activity.

The signal must be active HIGH for at

least four clock cycles.

CLK

The clock input provides the basic timing

for processor operation and bus control
activity. Its an asymmetric square wave
with 33% duty cycle.

INTR Interrupt Request

This is a triggered input. This is sampled

during the last clock cycles of each
instruction to determine the availability
of the request. If any interrupt request
is pending, the processor enters the
interrupt acknowledge cycle.

This signal is active high and internally

synchronized. 58
8086 Microprocessor
Pins and Signals
Min/ Max Pins The 8086 microprocessor can work in two
modes of operations : Minimum mode and
Maximum mode.

In the minimum mode of operation the

microprocessor do not associate with any
co-processors and can not be used for
multiprocessor systems.

In the maximum mode the 8086 can work

in multi-processor or co-processor
configuration.

Minimum or maximum mode operations

are decided by the pin MN/ MX(Active low).

When this pin is high 8086 operates in

minimum mode otherwise it operates in
Maximum mode.

59
8086 Microprocessor
Pins and Signals

Minimum mode signals

(Data Transmit/ Receive) Output signal from the

processor to control the direction of data flow
through the data transceivers

(Data Enable) Output signal from the processor

used as out put enable for the transceivers

ALE (Address Latch Enable) Used to demultiplex the

address and data lines using external latches

Used to differentiate memory access and I/O

access. For memory reference instructions, it is
high. For IN and OUT instructions, it is low.

Write control signal; asserted low Whenever

processor writes data to memory or I/O port

(Interrupt Acknowledge) When the interrupt

request is accepted by the processor, the output is
low on this line.
60
8086 Microprocessor
Pins and Signals
Minimum mode signals

HOLD Input signal to the processor form the bus masters

as a request to grant the control of the bus.

Usually used by the DMA controller to get the

control of the bus.

HLDA (Hold Acknowledge) Acknowledge signal by the

processor to the bus master requesting the
control of the bus through HOLD.

The acknowledge is asserted high, when the

processor accepts HOLD.

61
8086 Microprocessor
Pins and Signals

Maximum mode signals

Status signals; used by the 8086 bus controller to

generate bus timing and control signals. These are
decoded as shown.

62
8086 Microprocessor
Pins and Signals

Maximum mode signals

(Queue Status) The processor provides the status

of queue in these lines.

The queue status can be used by external device

to track the internal status of the queue in 8086.

The output on QS0 and QS1 can be interpreted as

shown in the table.

63
8086 Microprocessor
Pins and Signals

Maximum mode signals

 OPERATING MODES OF 8086 MICROPROCESSOR
• 8086 can be operated in two modes-
Minimum Mode
Maximum Mode
• In minimum mode all control signals are generated by
8086 itself, so it is used in single processor system
• In maximum mode all control signals are generated by
bus controller 8288 and not by the processor 8086, so it
is used in multiprocessor system.
• The pin 33 MN/MX is used to set minimum mode or
maximum mode of 8086 and also the function of pin no
24 to 31 will change as per the selected mode.
8284 Pin Diagram:
 8284 BLOCK DIAGRAM:
F/C CSYNC

x1 Clock
x2 Clock Logic OSC
EF1 PCLK

RDY1

AEN1
Ready Logic
RDY2 READY

AEN2

RES Reset Logic RESET

 8284 Connected to 8086 Mp
X1
Ready
X2
AEN1 CLK

8086 Microprocessor
AEN2
F/C 8284
Reset
RDY1
RDY2
RES
R
+5V
RESET KEY C
 8288 BUS CONTROLLER

• The 8288 is a 20-pin Vcc

IOB 1 20
chip specially designed
CLK 2 19 S0
to provide all the 8
S2
control signals when S1 3
2
18
MCE/PDEN
the 8088/86 is in DT/R 4 17
8
maximum mode. ALE 5 16 DEN

• The input and output 8 CEN

AEN 6 15
signals are described MRDC 7 14 INTA
below. AMWC 8 13 IORC

MWTC 9 12 AIOWC

GND 10 11 IOWC
 MRDC
S0
MWTC
S1
Bus AMWC
S2
Command IORC
Logic AIOWC
INTA

AEN DT/ R
CEN Control DEN
CLK Signals ALE
IOB Logic MCE / PDEN
INPUT SIGNALS
Pin Diagram of 74LS245:
Pin Diagram of 74LS245:
Function of 74LS245:
8086 System Minimum mode

(74LS373)

(74LS245)
Processor Timing Diagram of 8086 (Minimum Mode)
for Memory or I/O Read
T1 T2 T3 T4

CLOCK
__
DT/R

ALE

AD15 - AD0 A15 - A0 D0 – D15 (from memory)

A19/S6 - A16/S3 A19 - A16 S6 - S3

__
IO/M if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW

____
RD
______
DEN
 Processor Timing Diagram of 8086 (Minimum Mode)
for Memory or I/O Write
T1 T2 T3 T4

CLOCK
__
DT/R

ALE

AD15 - AD0 A15 - A0 D15 - D0 (from memory)

A19/S6 - A16/S3 A19 - A16 S6 - S3

__
IO/M if I/O ACCESS this is HIGH, if MEMORY ACCESS this is LOW

____
WR
______
DEN
8086 System Maximum Mode
 Processor Timing Diagram of 8086(Maximum Mode)
for Memory or I/O Read
T1 T2 T3 T4

CLOCK
__
DT/R

ALE

AD15- AD0 A15 - A0 D0-D15

S2-S0 S2-S0 Active S2-S0 Inacive

A19/S6 - A16/S3 A19 - A16 S6 - S3

MDRC/IORC
______
DEN
 Processor Timing Diagram of 8086(Maximum Mode)
for Memory or I/O Write
T1 T2 T3 T4

CLOCK
__
DT/R

ALE

AD15- AD0 A15 - A0 D0-D15

S2-S0 S2-S0 Active S2-S0 Inacive

A19/S6 - A16/S3 A19 - A16 S6 - S3

MWTC &IOWC

AMWC/AIOWC
______
DEN

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 INSTRUCTION SET
• Data moving instructions.
• Arithmetic instructions - add, subtract, increment,
decrement, convert byte/word and compare.
• Logic instructions - AND, OR, exclusive OR,
shift/rotate and test.
• String manipulation instructions - load, store,
move, compare and scan for byte/ word.
• Control transfer instructions - conditional,
unconditional, call subroutine and return from
subroutine.
• Input/Output instructions.
• Other instructions - setting/clearing flag bits, stack
operations, software interrupts, etc.
 ADDRESSING MODES
• Implied - the data value/data address is implicitly
associated with the instruction.
• Register - references the data in a register or in a
register pair.
• Immediate - the data is provided in the instruction.
• Direct - the instruction operand specifies the memory
address where data is
located.
• Register indirect - instruction specifies a register
containing an address, where data is located. This
addressing mode works with SI, DI, BX and BP
registers.
 ADDRESSING MODES
• Based - 8-bit or 16-bit instruction operand is added to
the contents of a base register (BX or BP), the
resulting value is a pointer to location where data
resides.
• Indexed - 8-bit or 16-bit instruction operand is added
to the contents of an index register (SI or DI), the
resulting value is a pointer to location where data
resides.
• Based Indexed - the contents of a base register (BX or
BP) is added to the contents of an index register (SI or
DI), the resulting value is a pointer to location where
data resides.
• Based Indexed with displacement - 8-bit or 16-bit
instruction operand is added to the contents of a base
register (BX or BP) and index register (SI or DI), the
resulting value is a pointer to location where data
 ADDRESSING MODES
• An addressing mode is the way the 8086 identifies the operands for the
instruction.
• All instructions that access the data use one or more of the addressing
modes.
• The memory address of an operand consists of two components
1. BASE ADDRESS OR STARTING ADDRESS OF THE MEMORY SEGMENT
2. EFFECTIVE ADDRESS OR BASE ADDRESS.
• When an operand is stored in a memory location, how for the
operand’s memory location is within a memory segment from the
starting address of the segment, is called Offset or Effective Address
(EA).
• The 8086 uses 20 bit memory address. The segment register gives 16
MSBs of the starting address of the memory segment. The BIU
generates 20 bit starting address of the memory segment by shifting
the content of the segment register left by 4 bits. In other words it
puts 4 zeros in 4 LSB positions.
• Memory Address = Starting address of the memory segment +
Offset
 ADDRESSING MODES
The 8086 has the following addressing modes:
• Register Addressing Mode
• Immediate Addressing Mode
• Direct Addressing Mode
• Register Indirect Addressing Mode
• Base Addressing Mode
• Indexed Addressing Mode
• Based Indexed Addressing Mode
• String Addressing Mode
• I/O Port Addressing Mode
• Relative Addressing Mode
• Implied Addressing Mode
 ADDRESSING MODES
Register Addressing Mode
• Both source and destination operands are registers.
The operand sizes must match. MOV destination,
source
• Examples:
• MOV AL, AH
• MOV AX, BX
Immediate Addressing Mode
• The data operand is supplied as part of the instruction.
The immediate operand can only be a source.
• Examples:
• MOV CH, 3A H
• MOV DX, 0C1A5 H
 ADDRESSING MODES
Direct Addressing Mode
• One of the operands is a memory location, given by a constant
offset.
• In this mode the 16 bit effective address (EA) is taken directly from
the displacement field of the instruction.
• Examples:
• MOV AX,[1234 H]
• MOV DL, [3BD2 H],
Register Indirect Addressing Mode
• One of the operands is a memory location, with the offset given
by one of the BP, BX, SI, or DI registers.
• Example:
• MOV [BX], CL
 ADDRESSING MODES
Base Addressing Mode
• In this mode EA is obtained by adding a displacement
(signed 8 bit or unsigned 16 bit) value to the contents
of BX or BP. The segment registers used are DS and SS.
• Example:
• MOV AX, [BP + 200]
Indexed Addressing Mode
• The operand’s offset is the sum of the content of an
index register SI or DI and an 8-bit or 16-bit
displacement.
• Example:
• MOV AH, [DI]
 ADDRESSING MODES
Based Indexed Addressing Mode
• In this mode, the EA is computed by adding a base
register (BX or BP), an index register (SI or DI) and a
displacement (unsigned 16 bit or sign extended 8 bit)
• Example:
• MOV AX, [BX + SI + 1234 H]
• MOV CX, [BP][SI] + 4
String Addressing Mode
• The instruction is a string instruction, which uses
index registers implicitly to access memory.
• Example:
• MOVS B
• MOVS W
 ADDRESSING MODES
I/O Port Addressing Mode
• The destination or source of the data is an I/O port.
Either direct port addressing (including an 8-bit port
address) or indirect addressing (DX must contain the port
address) may be used.
• Examples:
• IN AX, 50H ; Direct
• OUT DX, AL ; Indirect
Relative Addressing Mode
• In this mode, the operand is specified as a signed 8 bit
displacement, relative to PC(Program Counter).
• Examples:
• JMP 0200 H
• JNC START
 ADDRESSING MODES
Implied Addressing Mode
• Instructions using this mode have no operands.
• Examples:
• CLC, STC, CMC
 INSTRUCTION SET
• Intel 8086 has approximately 117 instructions. These
instructions are used to transfer data between registers,
register to memory, memory to register or register to I/O
ports and other instructions are used for data
manipulation.
• But in Intel 8086 operations between memory to
memory is not permitted. These instructions are
classified in to six-groups as follows.
1.Data Transfer Instructions
2.Arithmetic Instructions
3.Bit Manipulation Instructions
4.String Instructions
5.Program Execution Transfer Instructions
6.Processor Control Instructions
 Data Transfer Instructions
1.MOV
• MOV destination, source
• This (Move) instruction transfers a byte or a word from
the source operand to the destination operand.
• (DEST) (SRC)
• DEST = Destination
• SRC = Source
• Example :
• MOV AX, BX
• MOV AX, 2150H
• MOV AL, [1135]
2.PUSH
• PUSHSource
• This instruction decrements SP (stack pointer)
by 2 and then transfers a word from the
source operand to the top of the stack now
pointed to by stack pointer.
• (SP) (SP) 2
• ((SP)+1 : (SP)) (SRC)
• Example :
• PUSH SI
• PUSH BX
3.POP
• POP destination
• This instruction transfers the word at the
current top of stack (pointed to by SP) to the
destination operand and then increments SP
by 2, pointing to the new top of the stack.
• (DEST) ((SP)+1:(SP))
• (SP) (SP) + 2
• Example :
• POP DX
• POP DS
LAHF
• Load Register AH from Flags
• This instruction copies Sign flag(S), Zero flag (Z),
Auxiliary flag (AC), Parity flag (P) and Carry flag
(C) of 8086 into bits 7, 6, 4, 2 and 0 respectively,
of register AH

SAHF
• Store Register AH into Flags
• This instruction transfers bits 7, 6, 4, 2 and 0 from
register AH into S, Z, AC, P and C flags respectively,
thereby replacing the previous values.
 Data Transfer Instructions
XCHG
• XCHG destination, source
• This (Exchange) instruction switches the contentsof
the source and destination operands.

XLAT
• XLAT table
• This (Translate) instruction replaces a byte in the AL register with a byte from
a 256-byte, user-coded translation table. XLAT is useful for translating
characters from one code to another.
• AL ((BX) + (AL))
• Example :
• XLAT ASCII_TAB
• XLAT Table_3
LEA
• LEA destination, source
• This (Load Effective Address) instruction transfers the offset of the
source operand (memory) to the destination operand (16-bit general
register).
• (REG) EA
• Example :
• LEA BX, [BP] [DI]
• LEA SI, [BX + 02AF H]
LDS
• LDS destination, source
• This (Load pointer using DS) instruction transfers a 32-bit pointer
variable from the source operand (memory operand) to the
destination operand and register DS.
• (REG) (EA)
• (DS) (EA+2)
• Example :
• LDS SI, [6AC1H]
LES
• LES destination, source
• This (Load pointer using ES) instruction transfers a 32-bit pointer variable from the source
operand (memory operand) to the destination operand and register ES.
• (REG) (EA)
• (ES) (EA+2)
• Example :
• LES DI, [BX]
IN
• IN accumulator, port
• This (Input) instruction transfers a byte or a word from an input port to the accumulator (AL
or AX).
• (DEST) (SRC)
• Example :
• IN AX, DX
• IN AL, 062H
OUT
• OUT port, accumulator
• This (Output) instruction transfers a byte or a word from the accumulator (AL or AX)
to an output port.
• (DEST) (SRC)
• Example :
• OUT DX, AL
• OUT 31, AX
 ARITHMETIC INSTRUCTIONS
ADD
• ADD destination, source
• This (Add) instruction adds the two operands (byte or word) and stores the
result in destination operand.
• (DEST) (DEST) + (SRC)
• Example :
• ADD CX, DX
• ADD AX, 1257 H
• ADD BX, [CX]
ADC
• ADC destination, source
• This (Add with carry) instruction adds the two operands and adds one if carry
flag (CF) is set and stores the result in destination operand.
• (DEST) (DEST) + (SRC) + 1
• Example :
• ADC AX, BX
• ADC AL, 8
• ADC CX, [BX]
 ARITHMETIC INSTRUCTIONS
SUB
• SUB destination, source
• This (Subtract) instruction subtracts the source operand from the
destination operand and the result is stored in destination operand.
• (DEST) (DEST) – (SRC)
• Example :
• SUB AX, 6541 H
• SUB BX, AX
• SUB SI, 5780 H
SBB
• SBB destination, source
• This (Subtract with Borrow) instruction subtracts the source from the
destination and subtracts 1 if carry flag (CF) is set. The result is stored in
destination operand.
• (DEST) (DEST) – (SRC) –1
• Example :
• SBB BX, CX
• SBB AX, 2
 ARITHMETIC INSTRUCTIONS
CMP
• CMP destination, source
• This (Compare) instruction subtracts the source from the
destination, but does not store the result.
• (DEST) – (SRC)
• Example :
• CMP AX, 18
• CMP BX, CX
INC
• INC destination
• This (Increment) instruction adds 1 to the destination operand
(byte or word).
• (DEST) (DEST) + 1
• Example :
• INC BL
• INC CX
DEC
• DEC destination
• This (Decrement) instruction subtracts 1 from the destination
operand. (DEST) (DEST) –1
• Example :
• DEC BL
• DEC AX
NEG
• NEG destination
• This (Negate) instruction subtracts the destination operand from 0
and stores the result in destination. This forms the 2’s complement
of the number.
• (DEST) 0 – (DEST)
• Example :
• NEG AX
• NEG CL
DAA
• This (Decimal Adjust for Addition) instruction converts the
binary result of an ADD or ADC instruction in AL to packed
BCD format.
DAS
• This (Decimal Adjust for Subtraction) instruction converts
the binary result of a SUB or SBB instruction in AL to packed
BCD format.
AAA
• This (ASCII Adjust for Addition) instruction adjusts the
binary result of ADD or ADC instruction.
• If bits 0-3 of AL contain a value greater than 9, or if the
auxiliary carry flag (AF) is set, the CPU adds 06 to AL and
adds 1 to AH. The bits 4-7 of AL are set to zero.
• (AL) (AL) + 6
• (AH) (AH) + 1
• (AF) 1
AAS
• This (ASCII Adjust for Subtraction) instruction adjusts the binary result
of a SUB or SBB instruction.
• If D3–D0 of AL > 9,
• (AL) (AL) – 6
• (AH) (AH) – 1
• (AF) 1
MUL
• MUL source
• This (Multiply) instruction multiply AL or AX register by register or
memory location contents. Both operands are unsigned numbers. If
the source is a byte (8 bit), then it is multiplied by register AL and
the result is stored in AH and AL.
• If the source operand is a word (16 bit), then it is multiplied by
register AX and the result is stored in AX and DX registers.
• If 8 bit data, (AL) x (SRC)
If 16 bit data,(AX), (DX) (AX) x (SRC)
(AX)
Example :
• MUL 25
• MUL CX
• IMUL
• IMUL Source
• This (Integer Multiply) instruction performs a signed multiplication of the source
operand and the accumulator.
• If 8 bit data, (AX) (AL) x (SRC)
• If 16 bit data, (AX), (DX) (AX) x (SRC)
• Example :
• IMUL 250
• IMUL BL
AAM
• This (ASCII Adjust for Multiplication) instruction adjusts the
binary result of a MUL instruction. AL is divided by 10(0AH) and
quotient is stored in AH. The remainder is stored in AL.
• (AH) (AL/0AH)
• (AL) Remainder
DIV
• DIV Source
• This (Division) instruction performs an unsigned
division of the accumulator by the source operand. It
allows a 16 bit unsigned number to be divided by an 8
bit unsigned number, or a 32 bit unsigned number to
be divided by a 16 bit unsigned number.
• For 8 bit data, AX / source
(AL) Quotient
(AH) Remainder
• For 16 bit data, AX, DX /
Source (AX) Quotient
(DX) Remainder
• Example :
• DIV CX
• DIV 321
IDIV
• IDIV source
• This (Integer Division) instruction performs a signed division of the accumulator by
the source operand.
• For 8 bit data, AX / Source
(AL) Quotient
(AH) Remainder
• For 16 bit data, AX- DX / Source
(AX) Quotient
(DX) Remainder
• Example :
• IDIV CL
• IDIV AX

AAD
• This (ASCII Adjust for Division) instruction adjusts the unpacked BCD dividend in
AX before a division operation. AH is multiplied by 10(0AH) and added to AL. AH is
set to zero.
• (AL) (AH x 0AH) + (AL)
• (AH) 0
CBW
• This (Convert Byte to Word) instruction converts
a byte to a word. It extends the sign of the byte in
register AL through register AH. This instruction
can be used for 16 bit IMUL or IDIV instruction.
• IF AL < 80 H, then AH = 00 H
• IF AL > 80 H, then AH = FFH
CWD :
• This (Convert Word to Double word) instruction
converts a word to a double word.
• It extends the sign of the word in register AX
through register DX.
• If AX < 8000 H, then DX = 0000 H
• If AX > 8000 H, then DX = FFFFH
Bit Manipulation Instructions
(i)Logical Instructions: AND, OR, XOR, NOT, TEST
(ii)Shift Instructions: SHL, SAL, SHR, SAR
(iii)Rotate Instructions: ROL, ROR, RCL, RCR
AND
• AND destination, source
• This (AND) instruction performs the logical “AND” of the source
operand with the destination operand and the result is stored in
destination.
• (DEST) ¬ (DEST) “AND” (SRC)
• Example :
• AND BL, CL
• AND AL, 0011 1100 B
OR
• OR destination, source
• This (OR) instruction performs the logical “OR” of the source
operand with the destination operand and the result is stored in
destination.
• (DEST) ¬ (DEST) “OR” (SRC)
• Example :
• OR AX, BX
• OR AL, 0000 1111B
XOR
• XOR destination, source
• This (Exclusive OR) instruction performs the logical
“XOR” of the two operands and the result is stored in
destination operand.
• (DEST) ¬ (DEST) “XOR” (SRC)
• Example :
• XOR BX, AX
• XOR AL, 1111 1111B
NOT
• NOT destination
• This (NOT) instruction inverts the bits (forms the 1’s
complement) of the byte or word.
• (DEST) ¬ 1’s complement of (DEST)
• Example :
• NOT AX
TEST
• TEST destination, source
• This (TEST) instruction performs the logical “AND” of the two operands and
updates the flags but does not store the result.
• (DEST) “AND” (SRC)
• Example :
• TEST AL, 15 H
• TEST SI, DI
SHL
• SHL destination, count
• This (Shift Logical Left) instruction performs the shift operation. The number
of bits to be shifted is represented by a variable count, either 1 or the number
contained in the CL register.
• Example
• SHL AL, 1
• Before execution :
SAL
• SAL destination, count
• SAL (Shift Arithmetric Left) and SHL (Shift Logical Left) instructions perform the same
operation and are physically the same instruction.
• Example
• SAL AL, CL
• SAL AL, 1
SHR
• SHR destination, count
• This (Shift Logical Right) instruction shifts the bits in the destination operand to the
right by the number of bits specified by the count operend, either 1 or the number
contained in the CL register.
• Example
• SHR BL, 1
• SHR BL, CL
SAR
• SAR destination, count
• This (Shift Arithmetic Right) instruction shifts the bits in the
destination operand to the right by the number of bits specified in
the count operand. Bits equal to the original high-order (sign) bits are
shifted in on the left, thereby preserving the sign of the original value.

ROL
ROL destination, count
This (Rotate Left) instruction rotates the bits in the byte/word destination operand to the
left by the number of bits specified in the count operand.
ROR
• ROR destination, count
• This (Rotate Right) instruction rotates the bits in the byte/word
destination operand to the right by the number of bits specified in the
count operand.

RCL
RCL destination, count
This (Rotate through Carry Left) instruction rotates the contents left through
carry by the specified number of bits in count operand.
RCR
• RCR destination, count
• This (Rotate through Carry Right) instruction rotates the contents right
through carry by the specified number of bits in the count operand.
 STRING INSTRUCTIONS
REP
• REP MOVS destination, Source
• This (Repeat) instruction converts any string primitive
instruction into a re-executing loop. It specifies a termination
condition which causes the string primitive instruction to
continue executing until the termination condition is met.
• Example :
• REP MOVS CL, AL
• The other Repeat instructions are :
• REPE - Repeat while Equal
• REPZ - Repeat while zero
• REPNE - Repeat while Not Equal
• REPNZ - Repeat while Not Zero
• The above instructions are used with the CMPS and SCAS
instructions.
MOVS
• MOVS destination - string, source-string
• This (Move String) instruction transfers a byte/word
from the source string (addressed by SI) to the
destination string (addressed by DI) and updates SI and
DI to point to the next string element.
• (DEST)(SRC)
• Example :
• MOVS Buffer 1, Buffer 2
CMPS
• CMPS destination-string, source-string
• This (Compare String) instruction subtracts the destination
byte/word (addressed by DI) from the source byte/word
(addressed by SI). It affects the flags but does not affect the
operands.
• Example :
• CMPS Buffer 1, Buffer 2
 STRING INSTRUCTIONS
SCAS
• SCAS destination-string
• This (Scan String) instruction subtracts the destination string element (addressed by DI)
from the contents of AL or AX and updates the flags.
• Example :
• SCAS Buffer
LODS
• LODS source-string
• This (Load String) instruction transfers the byte/word string element addressed by SI to
register AL or AX and updates SI to point to the next element in the string.
• (DEST) (SRC)
• Example :
• LODSB name
• LODSW name
STOS
• STOS destination - string
• This (Store String) instruction transfers a byte/word from register AL or AX to the string
element addressed by DI and updates DI to point to the next location in the string.
• (DEST) (SRC)
• Example :
• STOS display
 PROGRAM TRANSFER INSTRUCTIONS
• (i)Unconditional instructions: CALL, RET, JMP
• (ii)Conditional instructions: JC, JZ, JA.....
• (iii)Iteration control instructions :LOOP, JCXZ
• (iv)Interrupt instructions: INT, INTO, IRET
CALL
• CALL procedure - name
• This (CALL) instruction is used to transfer execution to
a subprogram or procedure. RET (return) instruction
is used to go back to the main program. There are
two basic types of CALL : NEAR and FAR
• Example :
• CALL NEAR
• CALL AX
RET
• This (Return) instruction will return execution from a
procedure to the next instruction after the CALL
instruction in the main program.
• Example :
• RET
• RET 6
JMP
• JMP target
• This (Jump) instruction unconditionally transfers control
to the target location. The target operand may be
obtained from the instruction itself (direct JMP) or from
memory or a register referenced by the instruction
(indirect JMP).
• Example :
LOOP
• LOOP label
• This (Loop if CX not zero) instruction
decrements CX by 1 and transfers control to
the target operand if CX is not zero. Otherwise
the instruction following LOOP is executed.
• If CX=0, CX = CX–1
• IP = IP+displacement
• If CX=0, then the next sequential instruction is
executed.
• Example :
• LOOP again
 PROCESSOR CONTROL INSTRUCTIONS
HLT
• This (Halt) instruction will cause the 8086 to stop fetching
and executing instructions. The 8086 will enter a halt state.
WAIT
• This (Wait) instruction causes the 8086 to enter the wait
state while its test line is not active.
ESC
• This (Escape) instruction provides a mechanism by which
other coprocessors may receive their instructions from the
8086 instruction stream and make use of the 8086
addressing modes. The 8086 does a no operation (NOP) for
the ESC instruction other than to access a memory
operand and place it on the bus.
NOP
• This (No operation) instruction causes the
CPU to do nothing. NOP does not affect any
flags.
 ASSEMBLER DIRECTIVES
• An assembler is a program which translates an
assembly language program into machine language
program.
• An assembler directive is a statement to give
direction to the assembler to perform the task of
assembly process.
• The assembler directives control organization of the
program and provide necessary information to the
assembler to understand assembly language
programs to generate machine codes.
• An assembler supports directives to define data, to
organize segments, to control procedures, to define
macros etc.
• An assembly language program consists of two
Some assembler directives are,
• Borland Turbo Assembler (TASM)
• IBM Macro Assembler (MASM)
• Intel 8086 Macro Assembler (ASM)
• Microsoft Macro Assembler
ASSUME
• The ASSUME directive enables error-checking
for register values.
• It is used to inform the assembler the names
of the logical segments, which are to be
assigned to the different segments used in an
assembly language program
• Format:
• ASSUME segregister:name [ [, segregister:name]]...
• ASSUME dataregister:type [[, dataregister:type]]...
• ASSUME register:ERROR [[, register:ERROR]]...
• ASSUME [[register:]] NOTHING [[, register:NOTHING]]...
DB (Define Byte)
• It can be used to define data like BYTE.
• Format:
• Name of the Variable DB Initial values
• Example:
• WEIGHTS DB 18, 68, 45
DW (Define Word)
• It can be used to define data like WORD (2 bytes).
• Format:
• Name of the Variable DW Initial values
• Example:
• SUM DW 4589
DD (Define Double Word)
• It can be used to define data like DWORD
(4 bytes).
• Format:
• Name of the Variable DD Initial values
• Example:
• NUMBER DD 12345678
DQ (Define Quad Word)
• It can be used to define data like QWORD
(8 bytes).
• Format:
• Name of the Variable DQ Initial values
• Example:
• TABLE DQ 1234567812345678
DT (Define Ten Bytes)
• It can be used to define data like TBYTE (10 bytes).
• Format:
• Name of the Variable DT Initial values
• Example:
• AMOUNT DT 12345678123456781234
END (End of program)
• It marks the end of a program module and, optionally,
sets the program entry point to address.
• Format:
• END [ [address] ]
• Example:
• END label
ENDP (End Procedure)
• It marks the end of procedure.
• name previously begun with PROC.
• Format:
• nameENDP
• Example:
CONTROL PROC FAR
.
.
.
CONTROL ENDP
• ENDM (End Macro)
• It terminates a macro or repeat block.
• Format:
• ENDM
• Example:
CODE MACRO
.
.
.
ENDM
• ENDS (End of Segment)
• It marks the end of segment, structure, or union name previously begun
with SEGMENT, STRUCT, UNION, or a simplified segment directive.
• Format:
• name ENDS
• Example:
CODE SEGMENT
.
.
CODE ENDS
• EQU (Equate)
• It assigns numeric value of expression or text to name. The name
cannot be redefined later.
• Format:
• name EQU expression
• name EQU <text>
• Example:
• CLEAR_CARRY EQU CLC
• EVEN (Align on Even memory Address)
• Format:
• EVEN
• Example:
• SALES DB 9
• EVEN
• DATA_ARRAY DW 100 DUP (?)
INCLUDE
• This directive inserts source code from the source file given by filename
into the current source file during assembly. The filename must be
enclosed in angle brackets if it includes a backslash, semicolon, greater-
than symbol, less-than symbol, single quotation mark, or double
quotation mark.
• Format: filename
• INCLUDE
• Example: C: \ MICRO \ ASSEM.LEV
• INCLUDE
• The above directive informs assembler to include all statements
mentioned in the file, ASSEM.LEV from the directory C: \ MICRO.
MACRO
• A sequence of instructions to which a name is
assigned is called a macro. The name of a macro
is used in assembly language programming.
Macros and subroutines are similar. Macros are
used for short sequences of instructions, where
as subroutines for longer ones. Macros execute
faster than subroutines. A subroutine requires
CALL and RET instructions whereas macros do
not.
• Format:
• name MACRO [ optional arguments ]
• statements ENDM
 ASSEMBLY LANGUAGE PROGRAMMING
Program
A computer can only do what the programmer asks to do.
To perform a particular task the programmer prepares a
sequence of instructions, called a program.
Programming languages
• Microcomputer programming languages can
typically be divided into three main types:
1.Machine language
2.Assembly language
3.High-level language
Machine language
• A program written in the form of 0s and 1s is
called a machine language program. In the
machine language program there is a specific
binary code for each instruction.
• A microprocessor has a unique set of machine
language instructions defined by its
manufacturer.
• For example, the Intel 8085 uses the code
1000 11102 for its addition instruction while
the Motorola 6800 uses the code 1011 10012.
The machine language program has the following
demerits:
• It is very difficult to understand or debug a
program.
• Program writing is difficult.
• Programs are long.
• More errors occur in writing the program.
• Since each bit has to be entered individually
the entry of a program is very slow.
Assembly language
• Assembly language programming is writing machine
instructions in mnemonic form, using an assembler
to convert these mnemonics into actual processor
instructions and associated data.
The advantages of assembly language programming
1.The computation time is less.
2.It is faster to produce result.
The disadvantages of assembly language programming
• many instructions are required to achieve small tasks
• source programs tend to be large and difficult to
follow
High-level language
• High level language programs composed of English-
language-type statements rectify all deficiencies of
machine and assembly language programming. The
high level languages are FORTRON, COBAL, BASIC, C,
C++, Pascal, Visual Basic etc.
The high level language program has the following
demerits:
• One has to learn the special rules for writing
programs in a particular high level language.
• Low speed.
• A compiler has to be provided to convert a high level
language program into a machine language
Assembly language program
• Assembly language statements are written one
per line.
• A machine code program thus consists of a
sequence of assembly language statements,
where each statement contains a mnemonic.
• Each line of an assembly language program is split
into four fields, as below:
1.Label field
2.Mnemonic or Opcode field
3.Operand field
4.Comment field
As an example, a typical program for block transfer
of data written in 8086 assembly language is
given here.
LABEL
• The label field is optional. A label is an identifier.
• A label can be used to refer to a memory location
the value of a piece of data the address of a
program, sub-routine, code portion etc.
START: LDAA #24H
JMP START
• Here, the label START is equal to the address of the
instruction LDAA #24H. The label is used in the
program as a reference. This would result in the
processor jumping to the location (address)
associated with the label START, thus executing the
instruction LDAA #24H immediately after the JMP
instruction.
OPCODE
• Each instruction consists of an opcode
(Mnemonic) and possible one or more operands.
In the above instruction
JMP START
• The opcode is JMP and the operand is the
address of the label START.
Mnemonics are used because they
• are more meaningful than hex or binary values
• reduce the chances of making an error
• are easier to remember than bit values
OPERAND
• The operand field consists of additional information or data that the
opcode requires. In certain types of addressing modes, the operand is
used to specify
• constants or labels
• immediate data
• data contained in another accumulator or register
• an address
Examples of operands are
• JNZ STEP1
• MOV AX, 5000 H
• MOV AX, BX
• MOV AX, [3000 H]
COMMENTS
• The comment field is optional, and is used by the programmer to
explain how the coded program works. Comments are preceded by a
semi-colon. The assembler, when generating instructions from the
source file, ignores all comments.
Assembly Language Program - Development Tools
• Editor
• Assembler
• Linker
• Locator
• Loader
• Debugger
• Emulator
Editor:
• An editor is a program which allows creating a file containing the assembly
language statements for the program.
Assembler:
• An assembler is a program which translates an assembly language program into
machine language program.
Linker:
• A linker is a program which links smaller programs together to form a large
program. It is used to join several object files into one large object file. It also
links the subroutines with the main program.
Locator:
• A locator is a program which assigns specific memory addresses for the machine
codes of the program, which is to be loaded into the memory.
Loader:
• A loader is a program which loads object code into system memory. It can
accept programs in absolute or relocatable format.
Debugger:
• A debugger is a program which allows user to test and debug programs.
Emulator:
• An emulator is a mixture of software and hardware. It is usually used to test and
debug the software and hardware of an external system.
 MODULAR PROGRAMMING
• Modular programming is subdividing the complex
program into separate subprograms such as
functions and subroutines.
• Similar functions are grouped in the same unit of
programming code and separate functions are
developed as separate units of code so that the code
can be reused by other applications.
• For example, if a program needs initial and boundary
conditions, use subroutines to set them.
• Then if someone else wants to compute a different
solution using the program, only these subroutines
need to be changed. This is very easier than having
to read through a program line by line, trying to
figure out what each line is supposed to do and
• Subprograms make the actual program shorter,
hence easier to read and understand. Further, the
arguments show exactly what information a
subprogram is using. That makes it easier to
figure out whether it needs to be changed when
modifying the program.
 ALPs are developed by essentially the same
procedure as high-level language programs by,
• Exactly stating what the program is to do.
• Splitting the overall problem into tasks.
• Defining exactly what each task must do and how
it is to communicate with the other tasks.
• Putting the tasks into assembler language
modules and connecting the modules together to
form the program.
• Debugging and testing the program.
• Documenting the program.
The benefits of using modular programming are,
• Modular programming allows many
programmers to collaborate on the same
application.
• Same code can be used in many applications.
• Code is short, simple and easy to understand.
• Code is stored across multiple files.
• A single procedure can be developed for reuse,
eliminating the need to retype the code many
times.
• Errors can easily be identified, as they are
localized to a subroutine or function.
LINKING AND RELLOCATION
The process combines the following.
• Find the object modules to be linked.
• Construct the load module by assigning the
positions of all of all the segments in all of the
object modules being linked.
• Fill in all offset that could not be determined by
the assembler.
• Fill in all segment address.
• Load the program for execution.
Segment combination
• In addition to the linker commands, the
assembler provides a means of regulating the way
segments in different object modules are
organized by the linker. Segments with same
name are joined together by using the modifiers
attached to the SEGMENT directives. SEGMENT
directive may have the form:
• Segment name SEGMENT Combination-type
 PROCEDURES & MACROS
• A single instruction that expands automatically
into a set of instructions to perform a particular
task.
• A macro (which stands for "macroinstruction") is
a programmable pattern which translates a
certain sequence of input into a preset sequence
of output. Macros can be used to make tasks less
repetitive by representing a complicated
sequence of keystrokes, mouse movements,
commands, or other types of input.
Macro definition:
name MACRO [parameters,...]
statements >
ENDM
Advantages of macros
• Repeated small groups of instructions replaced by one macro
• Errors in macros are fixed only once, in the definition
• Duplication of effort is reduced
• In effect, new higher level instructions can be created
• Programming is made easier, less error prone
• Generally quicker in execution than subroutines
Disadvantages of macros
• In large programs, produce greater code size than procedures
When to use Macros
• To replace small groups of instructions not worthy of
subroutines
• To create a higher instruction set for specific applications
• To create compatibility with other computers
• To replace code portions which are repeated often throughout
the program
Procedure (PROC)
• This directive marks the start and end of a
procedure block called label. The statements in
the block can be called with the CALL instruction.
PROC definition:
label PROC [ [near / far] ]
<Procedure instructions>
label ENDP
Overlapping Proc Nested Proc
Differences between Macros and
Procedures
 INTERRUPTS AND INTERRUPT SERVICE
ROUTINES
Interrupts
• A signal to the processor to halt its current
operation and immediately transfer control to an
interrupt service routine is called as interrupt.
Interrupts are triggered either by hardware, as
when the keyboard detects a key press, or by
software, as when a program executes the INT
instruction.
• Interrupts can be seen as a number of functions.
These functions make the programming much
easier, instead of writing a code to print a character,
simply call the interrupt and it will do everything.
• There are also interrupt functions that work with
disk drive and other hardware. They are called as
software interrupts.
• Interrupts are also triggered by different hardware,
these are called hardware interrupts.
• To make a software interrupt there is an INT
instruction, it has very simple syntax: INT value.
• Where value can be a number between 0 to 255 (or
INTERRUPT SERVICE ROUTINES (ISRS)
• ISR is a routine that receives processor control
when a specific interrupt occurs.
• The 8086 will directly call the service routine for
256 vectored interrupts without any software
processing. This is in contrast to non vectored
interrupts that transfer control directly to a
single interrupt service routine, regardless of the
interrupt source.
Interrupt vector table:
 When an interrupt occurs, regardless of source, the
8086 does the following:
• The CPU pushes the flags register onto the stack.
• The CPU pushes a far return address (segment:offset)
onto the stack, segment value first.
• The CPU determines the cause of the interrupt (i.e., the
interrupt number) and fetches the four byte interrupt
vector from address 0 : vector x 4 (0:0, 0:4, 0:8 etc)
• The CPU transfers control to the routine specified by the
interrupt vector table entry.
After the completion of these steps, the interrupt service
routine takes control. When the interrupt service routine
wants to return control, it must execute an IRET
(interrupt return) instruction. The interrupt return pops
Types of Interrupts
• Hardware Interrupt - External uses INTR and NMI
• Software Interrupt - Internal - from INT or INTO
• Processor Interrupt - Traps and 10 Software
Interrupts
• External - generated outside the CPU by other
hardware (INTR, NMI)
• Internal - generated within CPU as a result of an
instruction or operation (INT, INTO,
Divide Error and Single Step)
Dedicated Interrupts
• Divide Error Interrupt (Type 0)
This interrupt occurs automatically following the
execution of DIV or IDIV instructions when the
quotient exceeds the maximum value that the
division instructions allow.
• Single Step Interrupt (Type 1)
This interrupt occurs automatically after execution
of each instruction when the Trap Flag (TF) is set
to
1. It is used to execute programs one instruction at
a time, after which an interrupt is requested.
Following the ISR, the next instruction is executed
• Non Maskable Interrupt (Type 2)
It is the highest priority hardware interrupt that
triggers on the positive edge.
This interrupt occurs automatically when it
receives a low-to-high transition on its NMI input
pin.
This interrupt cannot be disabled or masked. It is
used to save program data or processor status in
case of system power failure.
• Breakpoint Interrupt (Type 3)
This interrupt is used to set break points in
software debugging programs.
Software Interrupts (INT n)
• The software interrupts are non maskable
interrupts. They are higher priority than
hardware interrupts.
Hardware Interrupts
• INTR and NMI are called hardware interrupts.
INTR is maskable and NMI is non-maskable
interrupts.
Interrupt Priority
 BYTE AND STRING MANIPULATION
• The 8086 microprocessor is equipped with
special instructions to handle string
operations.
• By string we mean a series of data words or bytes
that reside in consecutive memory locations.
• The string instructions of the 8086 permit a
programmer to implement operations such as to
move data from one block of memory to a block
elsewhere in memory.
• A second type of operation that is easily
performed is to scan a string and data
elements stored in memory looking for a
specific value.
• Other examples are to compare the elements
and two strings together in order to
determine whether they are the same or
different.
• Move String : MOV SB, MOV SW: An
element of the string specified by the source
index (SI) register with respect to the current
data segment (DS) register is moved to the
location specified by the destination index (DI)
• The move can be performed on a byte (MOV SB)
or a word (MOV SW) of data. After the move is
complete, the contents of both SI & DI are
automatically incremented or decremented by 1
for a byte move and by 2 for a word move.
• Address pointers SI and DI increment or
decrement depends on how the direction flag DF
is set.
• Load and store strings : (LOD SB/LOD SW and STO
SB/STO SW) LOD SB: Loads a byte from a string in
memory into AL. The address in SI is used relative to
DS to determine the address of the memory location
of the string element. (AL) <= [(DS) + (SI)] (SI) <= (SI)
+1
• LOD SW : The word string element at the physical
address derived from DS and SI is to be loaded into
AX. SI is automatically incremented by 2. (AX) <=
[(DS) + (SI)] (SI) <= (SI) + 2
• STO SB : Stores a byte from AL into a string
location in memory. This time the contents of ES
and DI are used to form the address of the storage
location in memory [(ES) + (DI)] <= (AL) (DI) <=(DI)
+1
• STO SW : [(ES) + (DI)] <= (AX) (DI) <= (DI) + 2
 8086 program to determine largest number in an array
of n numbers
Algorithm –
• Load data from offset 500 to register CL and set register CH to 00
(for count).
• Load first number(value) from next offset (i.e 501) to
register AL and decrease count by 1.
• Now compare value of register AL from data(value) at next offset,
if that data is greater than value of register AL then update value
of register AL to that data else no change, and increase offset
value for next comparison and decrease count by 1 and continue
this till count (value of register CX) becomes 0.
• Store the result (value of register AL ) to memory address 2000
: 600.
Explanation –
• MOV SI, 500 : set the value of SI to 500
• MOV CL, [SI] : load data from offset SI to register CL
• MOV CH, 00 : set value of register CH to 00
• INC SI : increase value of SI by 1.
• MOV AL, [SI] : load value from offset SI to register AL
• DEC CL : decrease value of register CL by 1
• INC SI : increase value of SI by 1
• CMP AL, [SI] : compares value of register AL and [SI] (AL-[SI])
• JNC 413 : jump to address 413 if carry not generated
• MOV AL, [SI] : transfer data at offset SI to register AL
• INC SI : increase value of SI by 1
• LOOP 40C : decrease value of register CX by 1 and jump to address
40D if value of register CX is not zero
• MOV [600], AL : store the value of register AL to offset 600
• HLT : stop
 8086 program to find the min value in a
Algorithm – given array
• Assign value 500 in SI and 600 in DI
• Move the contents of [SI] in CL and increment SI by 1
• Assign the value 00 H to CH
• Move the content of [SI] in AL
• Decrease the value of CX by 1
• Increase the value of SI by 1
• Move the contents of [SI] in BL
• Compare the value of BL with AL
• Jump to step 11 if carry flag is set
• Move the contents of BL in AL
• Jump to step 6 until the value of CX becomes 0, and decrease CX by 1
• Move the contents of AL in [DI]
• Halt the program