Intel 8086

Intel 8086
MICROPROCESSOR
MICROPROCESSOR

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Features
 It is a 16-bit μp.
 8086 has a 20 bit address bus can access
up to 220 memory locations (1 MB).
 It can support up to 64K I/O ports.
 It provides 14 registers (16-bit ).
 Word size is 16 bits.
 It has multiplexed address and data bus
AD0- AD15 and A16 – A19.

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 8086 is designed to operate in two modes,
Minimum and Maximum.
 It can prefetche up to 6 instruction bytes from
memory and queues them in order to speed
up instruction execution.
 It requires +5V power supply.
 A 40 pin dual in line package.
 Address ranges from 00000H to FFFFFH
 Memory is byte addressable - Every byte has
a separate address.
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Intel 8086 Internal Architecture

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Internal architecture of 8086

• 8086 has two blocks BIU and EU.

• The BIU handles all transactions of data and
addresses on the buses for EU.
• BIU performs all bus operations such as
instruction fetching, reading and writing
operands for memory and calculating addresses
of the memory operands. The instruction bytes
are transferred to the instruction queue.
• EU executes instructions from the instruction
system byte queue.

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• Both units operate asynchronously to
give the 8086 an overlapping instruction
fetch and execution mechanism which is
called as Pipelining. This results in
efficient use of the system bus and
system performance.
• BIU contains Instruction queue, Segment
registers, Instruction pointer, Address
adder.
• EU contains Control circuitry, Instruction
decoder, ALU, Pointer and Index register,
Flag register.
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EXECUTION UNIT
• Decodes instructions fetched by the BIU
• Generate control signals,
• Executes instructions.

The main parts are:

• Control Circuitry
• Instruction decoder
• ALU

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EXECUTION
EXECUTION UNIT
UNIT –– General
General Purpose
Purpose Registers
Registers
16 bits

8 bits 8 bits

AH AL
AX Accumulator

BH BL Base
BX
CH CL Count
CX

DX DH DL
Data
SP
Stack Pointer
Pointer
BP Base Pointer

SI
Source Index
Index
DI Destination Index
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EXECUTION UNIT – General Purpose Registers

Register Purpose
AX Word multiply, word divide, word I /O
AL Byte multiply, byte divide, byte I/O, decimal
arithmetic

AH Byte multiply, byte divide

BX Store address information

CX String operation, loops

CL Variable shift and rotate

DX Word multiply, word divide, indirect I/O

(Used to hold I/O address during I/O instructions. If the result is more than
16-bits, the lower order 16-bits are stored in accumulator and higher order
16-bits are stored in DX register) 11
Pointer And Index Registers
• used to keep offset addresses.
• Used in various forms of memory addressing.
• In the case of SP and BP the default reference to form a
physical address is the Stack Segment.
• The index registers (SI & DI) and the BX generally default
to the Data segment register (DS).
SP: Stack pointer
– Used with SS to access the stack segment
BP: Base Pointer
– Primarily used to access data on the stack
– Can be used to access data in other segments
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• SI: Source Index register
– is required for some string operations
–SI is associated with the data segment (DS) reg. in
string operations.

• DI: Destination Index register

– is also required for some string operations.
– DI is associated with ES register in string operations.

• The SI and the DI registers may also be used to access data

stored in arrays.

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 EXECUTION UNIT – Flag Register
• A flag is a flip flop which indicates some conditions produced by
the execution of an instruction or
• controls certain operations of the EU .
• In 8086, EU contains
 a 16 bit flag register
9 of the 16 are active flags and remaining 7 are undefined.
6 flags - status flags
3 flags –control flags

U U U U O D IF T S Z U A U P U C
F F F F F F F F
Sign Auxiliary Carry
Interrupt Trap Zero Parity
Overflow Direction

U - Unused 14
EXECUTION UNIT – Flag Register

Flag Purpose
Carry (CF) Holds the carry after addition or the borrow after subtraction.
Also indicates some error conditions, as dictated by some
programs and procedures .
Parity (PF) PF=0;odd parity, PF=1;even parity.

Auxiliary (AF) Holds the carry (half – carry) after addition or borrow after
subtraction between bit positions 3 and 4 of the result
Zero (ZF) Shows the result of arithmetic or logic operation.
Z=1; result is zero. Z=0; The result is not 0.
Sign (SF) Holds the sign of the result after an arithmetic/logic
instruction
execution. S=1; negative, S=0
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 Flag Purpose
A control flag.
Trap (TF) Enables the trapping through an on-chip debugging
feature.
A control flag.
Interrupt (IF) Controls the operation of the INTR (interrupt request)
I=0; INTR pin disabled. I=1; INTR pin enabled.
A control flag.
Direction (DF) It selects either the increment or decrement mode for DI
and /or SI registers during the string instructions.
Overflow occurs when signed numbers are added or
Overflow (OF) subtracted. An overflow indicates the result has exceeded
the capacity of the Machine

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Execution unit – Flag Register
• Six of the flags are status indicators reflecting
properties of the last arithmetic or logical instruction.
• For example, if register AL = 7Fh and the instruction
ADD AL,1 is executed then the following happen
AL = 80h
CF = 0; there is no carry out of bit 7
PF = 0; 80h has an odd number of ones
AF = 1; there is a carry out of bit 3 into bit 4
ZF = 0; the result is not zero
SF = 1; bit seven is one
OF = 0;
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BUS INTERFACE UNIT (BIU)
Contains
• 6-byte Instruction Queue (Q)
• The Segment Registers (CS, DS, ES, SS).
• The Instruction Pointer (IP).
• The Address Summing block (Σ)

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 THE QUEUE (Q)

• The BIU uses a mechanism known as an

instruction stream queue to implement a
pipeline architecture.
• This queue permits pre-fetch of up to 6 bytes of
instruction code.
• BIU is free to look ahead in the program by pre-
fetching the next sequential instruction.

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• These pre-fetching instructions are held in its FIFO
queue. With its 16 bit data bus, the BIU fetches two
instruction bytes in a single memory cycle.
• The EU accesses the queue from the output
end. It reads one instruction byte after the other
from the output of the queue.
• The intervals of no bus activity, which may occur
between bus cycles are known as Idle state.

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 Physical Memory
Segmented Memory
00000
 The memory in an 8086/88
based system is organized as
segmented memory. Code segment (64KB)

 8086 addresses 1MB of memory Data segment (64KB)

1 MB
 The physical memory may be Extra segment (64KB)
divided into logical segments.
Stack segment (64KB)
 The 4 segments are Code, Data,
Extra and Stack segments.
FFFFF

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• The size of each segment is 64 KB
• A segment begins at a location which is divisible by 16
• Each of these segments can be used for a specific function.
– Code segment is used for storing the instructions.
– stack segment is used as a stack and used to store the return
address
– data and extra segments are used for storing data bytes.

* In the assembly language programming, more than one data/

code/ stack segments can be defined. But only one segment of
each type can be accessed at any time.

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• The 16 bit contents of the segment registers in the BIU
actually point to the starting location of a particular segment.
• Segments may be overlapped or non-overlapped

Advantages of Segmented memory Scheme

• Allows the memory capacity to be 1Mb although the actual addresses
are of 16 bit size.
• Allows the placing of code, data and stack portions of the same program
in different parts (segments) of the m/y, for data and code protection.

• Permits a program / data to be put into different areas of memory each

time program is executed, i.e. provision for relocation may be done .
• segment registers are used to allow the instruction, data or stack portion
of a program to be more than 64Kb long by using more than one code,
data or stack segments.

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 MEMORY
00000

BIU
Segment Registers 34BA0
CODE (64k)
44B9F
CSR 34BA
44EB0
DATA (64K)

MB
1
44EB 54EAF
DSR
54EB0
ESR 54EB EXTRA (64K)
64EAF
695E 695E0
SSR
STACK (64K)
795DF

Each segment register store the

upper 16 bit of the starting address
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of the segments
Instruction pointer & summing block
• Instruction pointer register contains a 16-bit offset
address of instruction that is to be executed next.
• IP always references the Code segment register (CS).
• The value contained in the IP is called as an offset as
this value must be added to the base address of the code
segment to find the 20-bit physical address.
• IP is incremented after executing every instruction.
• To form a 20bit address of the next instruction, the 16 bit
address of the IP is added (by the address summing
block) to the address contained in the CS , which has
been shifted four bits to the left.

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• The following examples shows the CS:IP scheme of
address formation:

CS 34BA IP 8AB4 Code segment

34BA0
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR 8AB4 (offset)
four binary digits left
3D645

34BA0(CS)+
8AB4(IP)
3 D 6 5 4 (next address)
44B9F

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 • Example For Address Calculation (segment: offset)

• If the data segment starts at location 1000h and a data

reference contains the address 29h where is the actual
data?

Offset 0000 0000 0010 1001

Segment Address
0001 0000 0000 0000 0000

Required Address 0001 0000 0000 0010 1001

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Segment and Address register combination

• CS:IP

• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string operations)

• ES:DI (for string operations)

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Summary of Registers & Pipeline of 8086 µP

EU BIU

AX AH AL
IP
BX BH BL
Fetch &
CX CH CL D
store code CS DS ES SS
DH DL E bytes in
DX C
C
O PIPELINE C
O D PIPELINE O IP BX DI SP
SP D E (or) D DI BP
E E
BP O QUEUE
SI
U I
SI R N
T
DI
Default Assignment
Timing
FLAGS ALU control

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