Architecture
Page 1
8086 Microprocessor
Execution Unit (EU) Bus Interface Unit (BIU)
EU executes instructions that have BIU fetches instructions, reads data
already been fetched by the BIU. from memory and I/O ports, writes
data to memory and I/ O ports.
BIU and EU functions separately.
Page 2
Execution Unit (EU)
Execution Unit (EU)
• Main function
• Control operations on data using the instruction decoder &
ALU
• Gives instructions to BIU
• From where to fetch the data
• Decode and execute those instructions
• EU has no direct connection with system buses
• Shown in the figure
• Performs operations over data through BIU
• Components
• ALU
• It handles all arithmetic and logical operations
• Example: +, −, ×, /, OR, AND, NOT
• Flag Register
• A 16-bit register that behaves like a flip-flop
• It changes its status according to the result stored in
the accumulator
• There are 9 flags, divided into 2 groups − Conditional
Flags and Control Flags.
Page 3
17
Execution Unit (EU)
Conditional Flags
• Carry flag − This flag indicates an overflow condition for arithmetic operations
• Auxiliary flag − When an operation is performed at ALU, it results in a carry/borrow from lower
nibble (i.e., D0 D3) to upper nibble (i.e. D4 D7), then this flag is set, i.e. carry given by D3 bit to
D4 is AF flag. The processor uses this flag to perform binary to BCD conversion
• Parity flag − This flag is used to indicate the parity of the result, i.e. when the lower order 8-
bits of the result contains even number of 1s, then the Parity Flag is set. For odd number of 1s,
the Parity Flag is reset
• Zero flag − This flag is set to 1 when the result of arithmetic or logical operation is zero else it
is set to 0
• Sign flag − This flag holds the sign of the result, i.e. when the result of the operation is
negative, then the sign flag is set to 1 else set to 0
• Overflow flag − This flag represents the result when the system capacity is exceeded
Control Flags
• Trap flag − It is used for single step control and allows the user to execute one instruction at a
time for debugging. If it is set, then the program can be run in a single step mode
• Interrupt flag − It is an interrupt enable/disable flag, i.e. used to allow/prohibit the
interruption of a program. It is set to 1 for interrupt enabled condition and set to 0 for interrupt
disabled condition
• Direction flag − It is used in string operation. As the name suggests when it is set then string
bytes are accessed from the higher memory address to the lower memory address and vice-a-
versa
Page 4
18
Execution Unit (EU)
General purpose register
• AX register − It is also known as accumulator register. It is used to store operands for
arithmetic operations.
• BX register − It is used as a base register. It is used to store the starting base address of the
memory area within the data segment.
• CX register − It is referred to as counter. It is used in loop instruction to store the loop counter.
• DX register − This register is used to hold I/O port address for I/O instruction.
• Stack pointer register - It is a 16-bit register, which holds the address from the start of the
segment to the memory location, where a word was most recently stored on the stack.
• Base Pointer(BP) - It is used to store the base address of the memory.
• Source Index(SI) - It is a memory pointer which is used to store the offset address of the
source.
• Destination Index(DI) - It is a memory pointer which is used to store the offset address of the
destination.
Page 5
19
8086 Microprocessor
Bus Interface Unit (BIU)
Dedicated Adder to generate
20 bit address
Four 16-bit segment
registers
Code Segment (CS)
Data Segment (DS)
Stack Segment (SS)
Extra Segment (ES)
Page 6
8086 Microprocessor
Bus Interface Unit (BIU)
Segment
Registers
8086’s 1-megabyte The 8086 can directly Programs obtain access
memory is divided address four segments to code and data in the
into segments of up (256 K bytes within the 1 segments by changing
to 64K bytes each. M byte of memory) at a the segment register
particular time. content to point to the
desired segments.
Page 7
8086 Microprocessor
Bus Interface Unit (BIU)
Segment Code Segment Register
Registers
16-bit
CS contains the base or start of the current code segment;
IP contains the distance or offset from this address to the
next instruction byte to be fetched.
BIU computes the 20-bit physical address by logically
shifting the contents of CS 4-bits to the left and then
adding the 16-bit contents of IP.
That is, all instructions of a program are relative to the
contents of the CS register multiplied by 16 and then offset
is added provided by the IP.
Page 8
8086 Microprocessor
Bus Interface Unit (BIU)
Segment Data Segment Register
Registers
16-bit
Points to the current data segment; operands for most
instructions are fetched from this segment.
The 16-bit contents of the Source Index (SI) or
Destination Index (DI) or a 16-bit displacement are used
as offset for computing the 20-bit physical address.
Page 9
8086 Microprocessor
Bus Interface Unit (BIU)
Segment Stack Segment Register
Registers
16-bit
Points to the current stack.
The 20-bit physical stack address is calculated from the
Stack Segment (SS) and the Stack Pointer (SP) for stack
instructions such as PUSH and POP.
In based addressing mode, the 20-bit physical stack
address is calculated from the Stack segment (SS) and the
Base Pointer (BP).
Page 10
8086 Microprocessor
Bus Interface Unit (BIU)
Segment Extra Segment Register
Registers
16-bit
Points to the extra segment in which data (in excess of
64K pointed to by the DS) is stored.
String instructions use the ES and DI to determine the 20-
bit physical address for the destination.
Page 11
8086 Microprocessor
Bus Interface Unit (BIU)
Segment Instruction Pointer
Registers
16-bit
Always points to the next instruction to be executed within
the currently executing code segment.
So, this register contains the 16-bit offset address pointing
to the next instruction code within the 64Kb of the code
segment area.
Its content is automatically incremented as the execution
of the next instruction takes place.
Page 12
8086 Microprocessor
Bus Interface Unit (BIU)
Instruction queue
A group of First-In-First-
Out (FIFO) in which up to
6 bytes of instruction
code are pre fetched
from the memory ahead
of time.
This is done in order to
speed up the execution
by overlapping
instruction fetch with
execution.
This mechanism is known
as pipelining.
Page 13
8086 Microprocessor
EU decodes and
executes instructions.
A decoder in the EU
control system
translates instructions.
16-bit ALU for
performing arithmetic
and logic operation
Four general purpose
registers(AX, BX, CX, DX);
Pointer registers (Stack
Pointer, Base Pointer);
and
Some of the 16 bit registers can be
Index registers (Source used as two 8 bit registers as :
Index, Destination Index)
each of 16-bits AX can be used as AH and AL
BX can be used as BH and BL
CX can be used as CH and CL Page 14
DX can be used as DH and DL
8086 Microprocessor
EU Accumulator Register (AX)
Registers
Consists of two 8-bit registers AL and AH, which can be
combined together and used as a 16-bit register AX.
AL in this case contains the low order byte of the word,
and AH contains the high-order byte.
The I/O instructions use the AX or AL for inputting /
outputting 16 or 8 bit data to or from an I/O port.
Multiplication and Division instructions also use the AX or
AL.
Page 15
8086 Microprocessor
EU Base Register (BX)
Registers
Consists of two 8-bit registers BL and BH, which can be
combined together and used as a 16-bit register BX.
BL in this case contains the low-order byte of the word,
and BH contains the high-order byte.
This is the only general purpose register whose contents
can be used for addressing the 8086 memory.
All memory references utilizing this register content for
addressing use DS as the default segment register.
Page 16
8086 Microprocessor
EU Counter Register (CX)
Registers
Consists of two 8-bit registers CL and CH, which can be
combined together and used as a 16-bit register CX.
When combined, CL register contains the low order byte of
the word, and CH contains the high-order byte.
Instructions such as SHIFT, ROTATE and LOOP use the
contents of CX as a counter.
Example:
The instruction LOOP START automatically decrements
CX by 1 without affecting flags and will check if [CX] =
0.
If it is zero, 8086 executes the next instruction;
otherwise the 8086 branches to the label START.
Page 17
8086 Microprocessor
EU Data Register (DX)
Registers
Consists of two 8-bit registers DL and DH, which can be
combined together and used as a 16-bit register DX.
When combined, DL register contains the low order byte of
the word, and DH contains the high-order byte.
Used to hold the high 16-bit result (data) in 16 X 16
multiplication or the high 16-bit dividend (data) before a
32 ÷ 16 division and the 16-bit reminder after division.
Page 18
8086 Microprocessor
EU Stack Pointer (SP) and Base Pointer (BP)
Registers
SP and BP are used to access data in the stack segment.
SP is used as an offset from the current SS during
execution of instructions that involve the stack segment in
the external memory.
SP contents are automatically updated (incremented/
decremented) due to execution of a POP or PUSH
instruction.
BP contains an offset address in the current SS, which is
used by instructions utilizing the based addressing mode.
Page 19
8086 Microprocessor
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
Page 20
8086 Microprocessor
EU Source Index (SI) and Destination Index (DI)
Registers
Used in indexed addressing.
Instructions that process data strings use the SI and DI
registers together with DS and ES respectively in order to
distinguish between the source and destination addresses.
Page 21
8086 Microprocessor
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.
Sign Flag Zero Flag Parity Flag
This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OF DF IF TF SF ZF AF PF CF
Tarp Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction
Direction Flag Interrupt Flag
This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address Page 22
disables these interrupts.
towards the lowest address, i.e., auto incrementing mode.
Architecture
8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
into 4 groups OF DF IF TF SF ZF AF PF CF
Sl.No. Type Register width Name of register
1 General purpose register 16 bit AX, BX, CX, DX
8 bit AL, AH, BL, BH, CL, CH, DL, DH
2 Pointer register 16 bit SP, BP
3 Index register 16 bit SI, DI
4 Instruction Pointer 16 bit IP
5 Segment register 16 bit CS, DS, SS, ES
Flag (PSW) Flag register
Page 23
Architecture Registers and Special Functions
Register Name of the Register Special Function
AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic
operations
AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic
operations
BX Base register Used to hold base value in base addressing mode
to access memory data
CX Count Register Used to hold the count value in SHIFT, ROTATE
and LOOP instructions
DX Data Register Used to hold data for multiplication and division
operations
SP Stack Pointer Used to hold the offset address of top stack
memory
BP Base Pointer Used to hold the base value in base addressing
using SS register to access data from stack
memory
SI Source Index Used to hold index value of source operand (data)
for string instructions
Data Index
Page 24
