Digital Design Using

Verilog HDL
22ECE42

Digital Design Using Verilog HDL- 22ECE42

PART A : Design and Verification

Expt 6:
Sequence Detector

Digital Design Using Verilog HDL- 22ECE42

 AIM
Write a Verilog to detect sequence “1010” in a bit stream with and
without overlap. Verify the design using Verilog Test Bench Code.

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Digital Design Using Verilog HDL- 22ECE42
 Sequence Detector
● A sequence detector is a sequential state machine that takes an
input string of bits and generates an output 1 whenever the target
sequence has been detected.
● Sequence detector is of two types:
Overlapping
Non-Overlapping din

clk sequence dout

detector

rst

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Digital Design Using Verilog HDL- 22ECE42
 Sequence Detector

din - 1 0 1 0 1 0 1 0 1 1 0 0

Non-Overlapping
din - 101010101100
dout - 000100010000

Overlapping
din - 101010101100
dout - 000101010000
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Digital Design Using Verilog HDL- 22ECE42
Sequence Detector
without overlap

Digital Design Using Verilog HDL- 22ECE42 6

STATE ASSIGNMENT
State Assignment
S0 = 00
S1 = 01
S2 = 10
S3 = 11
State Received Bit
S0 -

S1 1

S2 10

S3 101
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Digital Design Using Verilog HDL- 22ECE42
STATE TRANSITION DIAGRAM

Received
State
Bit
S0 -
S1 1
S2 10
S3 101

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Digital Design Using Verilog HDL- 22ECE42
 STATE TABLE

Next State Output

Current State
din=0 din=1 din=0 din=1

S0 S0 S1 0 0
S1 S2 S1 0 0
S2 S0 S3 0 0
S3 S0 S1 1 0
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Digital Design Using Verilog HDL- 22ECE42
 Verilog Code in Behaviour model
● always and initial block
● All other behavioral statements can appear only inside these structured
procedure statements
● Behavioural statements
○ If
○ Switch
○ For
○ While
○ repeat
○ Task
○ Function
● No need to know full circuit diagram or boolean expression
Digital Design Using Verilog HDL- 22ECE42
 Conditional Statement
if (<expression>)
true_statement ;
else
false_statement;

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Digital Design Using Verilog HDL- 22ECE42
 Multiway Branching: case Statement
● The keywords case, endcase, and default are used in the case statement.
● Syntax:
case (expression)
case_item1: statement1;
case_item2: statement2;
case_item3: statement 3;
…
…
default: default_statement;
endcase
Digital Design Using Verilog HDL- 22ECE42
 Verilog Code
module sequence_detector_wo(output dout, input clk,rst, din);
parameter [1:0] s0 = 2'b00, s1 = 2'b01,s2 = 2'b10, s3 =2'b11;
reg [1:0] current_state, next_state;

always @(posedge clk or posedge rst or din)

begin
if(rst)
begin
current_state <= s0;
end
else current_state <= next_state;
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Digital Design Using Verilog HDL- 22ECE42
always @(current_state or din)
1010
begin
case(current_state)
s0: begin
if(din)
next_state <= s1;
Next State Output
Current
end State din=0 din=1 din=0 din=1
s1: begin
S0 S0 S1 0 0
if(~din) S1 S2 S1 0 0
next_state <= s2; S2 S0 S3 0 0
S3 S0 S1 1 0
end Digital Design Using Verilog HDL- 22ECE42
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 s2: begin 1010
if(din)
next_state <= s3;
else
next_state <= s0;
end
s3: begin
if(din)
next_state <= s1;
else Next State Output
Curre
next_state <= s0; nt
end State din=0 din=1 din=0 din=1
default: next_state = s0;
endcase S0 S0 S1 0 0
end S1 S2 S1 0 0
assign dout = (current_state == s3) && (din S2 S0 S3 0 0
== 0)? 1:0; 15
S3 S0
Digital Design Using Verilog HDL- 22ECE42
S1 1 0
 Testbench
module sequence_detector_wo_tb;
reg clk, rst,din;
wire dout;
sequence_detector_wo sd(dout, clk, rst, din);
initial
clk = 0;
always
#5
clk = ~clk;
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Digital Design Using Verilog HDL- 22ECE42
initial #10 din = 1; #10 din = 0;
begin #10 din =0; #10 din = 1;
din = 0; #10 din = 0; #10 din = 0;
#5 rst = 1; #10 din = 1; #30;
#5 rst = 0; #10 din = 1; $finish;
#5 din = 1; #10 din = 1; end
#10 din = 0; #10 din = 0; endmodule
#10 din = 1; #10 din = 1;
#10 din = 0;
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Digital Design Using Verilog HDL- 22ECE42
Sequence Detector
with overlap

Digital Design Using Verilog HDL- 22ECE42 18

STATE ASSIGNMENT
State Assignment
S0 = 00
S1 = 01
S2 = 10
S3 = 11
State Received Bit
S0 -

S1 1

S2 10

S3 101
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Digital Design Using Verilog HDL- 22ECE42
STATE TRANSITION DIAGRAM

Received
State
Bit
S0 -
S1 1
S2 10
S3 101

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Digital Design Using Verilog HDL- 22ECE42
 STATE TABLE

Next State Output

Current State
din=0 din=1 din=0 din=1

S0 S0 S1 0 0
S1 S2 S1 0 0
S2 S0 S3 0 0
S3 S2 S1 1 0
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Digital Design Using Verilog HDL- 22ECE42
 Verilog Code
module sequence_detector_o(output dout, input clk,rst, din);
parameter [1:0] s0 = 2'b00, s1 = 2'b01,s2 = 2'b10, s3 =2'b11;
reg [1:0] current_state, next_state;

always @(posedge clk or posedge rst or din)

begin
if(rst)
begin
current_state <= s0;
end
else current_state <= next_state;
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Digital Design Using Verilog HDL- 22ECE42
always @(current_state or din)
begin 1010
case(current_state)
s0: begin
if(din)
next_state <= s1;
end
Next State Output
s1: begin Curren
t State
if(~din) din=0 din=1 din=0 din=1

next_state <= s2; S0 S0 S1 0 0

end S1 S2 S1 0 0
S2 S0 S3 0 0
S3 S2 S1 1 0
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Digital Design Using Verilog HDL- 22ECE42
 s2: begin
if(din) 1010
next_state <= s3;
else
next_state <= s0;
end
s3: begin
if(din)
next_state <= s1;
else Next State Output
Curre
next_state <= s2;
nt
end State din=0 din=1 din=0 din=1
default: next_state = s0;
endcase
S0 S0 S1 0 0
end S1 S2 S1 0 0

assign dout = (current_state == s3) && (din == S2 S0 S3 0 0

0)? 1:0; Digital Design Using Verilog HDL- S3
22ECE42 S2 S1 1 0 24
 Testbench
module sequence_detector_o_tb;
reg clk, rst,din;
wire dout;
sequence_detector_o sd(dout, clk, rst, din);
initial
clk = 0;
always
#5
clk = ~clk;
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Digital Design Using Verilog HDL- 22ECE42
initial #10 din = 1; #10 din = 0;
begin #10 din =0; #10 din = 1;
din = 0; #10 din = 0; #10 din = 0;
#5 rst = 1; #10 din = 1; #30;
#5 rst = 0; #10 din = 1; $finish;
#5 din = 1; #10 din = 1; end
#10 din = 0; #10 din = 0; endmodule
#10 din = 1; #10 din = 1;
#10 din = 0;
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Digital Design Using Verilog HDL- 22ECE42
 Task
Consider a 3-bit ripple carry adder circuit with two 3-bit binary numbers (A =
011, B = 101, Cin =1) as inputs.

Draw the output waveform for the sum (S) and carry-out (Cout) signals.
Assume that all gate delays are negligible.

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Digital Design Using Verilog HDL- 22ECE42
THANK YOU

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Digital Design Using Verilog HDL- 22ECE42