The document describes designing a sequence detector circuit to detect the bit pattern "11011" in an overlapping manner. It includes the aim, theory, state diagrams, state tables using K-maps, and Verilog code with and without flip-flops. The sequence detector detects the pattern and outputs a 1 when detected, and 0 otherwise. It was implemented on an FPGA to verify the codes work as intended. The project helps learn how to design sequence detectors for applications like remote controls.
The document describes designing a sequence detector circuit to detect the bit pattern "11011" in an overlapping manner. It includes the aim, theory, state diagrams, state tables using K-maps, and Verilog code with and without flip-flops. The sequence detector detects the pattern and outputs a 1 when detected, and 0 otherwise. It was implemented on an FPGA to verify the codes work as intended. The project helps learn how to design sequence detectors for applications like remote controls.
The document describes designing a sequence detector circuit to detect the bit pattern "11011" in an overlapping manner. It includes the aim, theory, state diagrams, state tables using K-maps, and Verilog code with and without flip-flops. The sequence detector detects the pattern and outputs a 1 when detected, and 0 otherwise. It was implemented on an FPGA to verify the codes work as intended. The project helps learn how to design sequence detectors for applications like remote controls.
The document describes designing a sequence detector circuit to detect the bit pattern "11011" in an overlapping manner. It includes the aim, theory, state diagrams, state tables using K-maps, and Verilog code with and without flip-flops. The sequence detector detects the pattern and outputs a 1 when detected, and 0 otherwise. It was implemented on an FPGA to verify the codes work as intended. The project helps learn how to design sequence detectors for applications like remote controls.
To design a sequence detector that detects a bit stream pattern of
'11011' in an overlapping manner.
❖ Theory
The sequence detector is a clocked sequential circuit which is used
to detect the desired binary sequence.
Input Sequence Detector Output
Sequence Sequence
Fig (a) : Block diagram of Sequence Detector
Once we know the sequence which is to be detected we can draw
a State diagram for it. From the state diagram we can design the circuit. Generally it produces an output = ‘1’ whenever it detects the desired sequence and = ‘0’ in other cases.
An overlapping sequence detector means say for example, if a bit
sequence of '1111011011111' is given as the input, the designed system should be able to detect the sequence '11011' twice. ❖ State Diagrams: 0/0
S0
S1 S4
S3 0/0 S2
Explanation:
Initially when the input is ‘1’ the machine moves to next state S1. If the input is ‘0’ the machine remains in the same state i.e S0. The output in these two cases is zero. Now according to the sequence the next input should be ‘1’. The machine moves to the next state S2 only if the next input is ‘1’ otherwise if input is ‘0’ it goes back to S0 . Similarly, if next I/P is 0 then it moves to next state S3 else stays in its state only. If next I/P is 1 then it moves to S4 else moves to S0. If next I/P is 1 then it moves to S2 and the output here is 1 and sequence is detected once else moves to S0. ❖ State Tables & use of K-Maps
S0 / A=000
S1 / B=001
S2 / C=011
S3 / D=100
S4 / E=101
Transition Table With Output
Output Table
Separate the Transition Table into Three Tables, One for Each Flip-Flop K Maps For D2 : Y2\Y1Y0 Y2\Y1Y0 00 01 11 10 00 01 11 10 0 1 X 0 X 1 X X 1 1 X X X=0 X=1
D2= X’ Y1 + X Y2 Y0’
For D1 : Y2\Y1Y0 Y2\Y1Y0 00 01 11 10 00 01 11 10 0 X 0 1 1 X 1 X X 1 1 X X X=0 X=1
D1= X Y0 For D0: Y2\Y1Y0 Y2\Y1Y0 00 01 11 10 00 01 11 10 0 X 0 1 1 1 X 1 X X 1 1 1 X X X=0 X=1
module dff( input d, input reset, input clk, output reg q, output reg qbar); always @(posedge clk or posedge reset) if(reset)begin q<=1'b0; qbar<=1'b1; end else begin q<=d; qbar<=~d; end endmodule
Code – 2 without using flipflops
module seq_det( input clk, input rst, input bit, output reg c); reg [2:0] state; parameter s0=3'b000, s1=3'b001, s2=3'b010, s3=3'b011, s4=3'b100; always@(posedge clk or posedge rst) if(rst==1) begin state<=s0; end else case(state) s0:begin if(bit==1) begin state<=s1; c<=0; end else begin state<=s0; c<=0; end end s1:begin if(bit==1) begin state<=s2; c<=0; end else begin state<=s0; c<=0; end end s2:begin if(bit==0) begin state<=s3; c<=0; end else begin state<=s2; c<=0; end end s3:begin if(bit==1) begin state<=s4; c<=0; end else begin state<=s0; c<=0; end end s4:begin if(bit==1) begin state<=s2; c<=1; end else begin state<=s0; c<=0; end end endcase endmodule ❖ Conclusion
This project helps us to learn how to implement Sequence Detector.
We can implement the sequence detector with or without using Flipflops on FGPA. The Verilog codes for both the cases were verified and implemented on FGPA. Sequence detector finds its application as remote control for TV or garage door openers etc also to detect a flag in bitstream.
