The 8051 Microcontroller: (Please Ignore Repeated Slides If Any. Also, Refer Text Too While Studying All The Slides)
The 8051 Microcontroller: (Please Ignore Repeated Slides If Any. Also, Refer Text Too While Studying All The Slides)
The 8051 Microcontroller: (Please Ignore Repeated Slides If Any. Also, Refer Text Too While Studying All The Slides)
Microcontroller Microprocessor
1) Microcontroller has a CPU,RAM, ROM , 1) an IC that has only CPU inside it.
other peripherals all embedded in it, No RAM,ROM,other peripherals inside it.
on a single chip.
2) Cheaper 2)expensive
4) few op- codes, more bit handling Instructions 4)more op-codes, few bit handling instructions
2) Cheaper
3) Space effective since it does not require extra RAM,ROM,peripherals
CPU
OSC Bus
4 I/O Ports Serial
Control
P0 P2 P1 P3 TXD RXD
Addr/Data
Important 8051 Features
• 4K bytes ROM
• 128 bytes RAM
• Four 8-bit I/O ports
• Two 16-bit timers
• Serial interface
• 64K external code memory space
• 64K data memory space
Feature 8051
ROM (program space in bytes) 4K
RAM (bytes) 128
Timers 2
8 pin Ports 4
I/O pins 32
Serial port 1
Interrupt sources 6
8051
Architecture /
Internal Block Diagram
8051 Internal Block Diagr am
Architectural Features- (Refer A.K Ray for details)
• ACC or A register operand reg
• B reg operand for MUL ,DIV
• PSW (Program Status Word) –set of 7 flags
contains status bits which indicates the current state of the cpu.
PSW.7 CarrY(CY)
PSW.6 Aux Carry (AC)
PSW.5 Flag 0 (F0)
PSW.4 Register Bank Select 1
PSW.3 Register Bank Select 0
PSW.2 Overflow(OV)
PSW.1 reserved
PSW.0 Even Parity Flag (P)
• SP (Stack Pointer) 8-bit reg-incremented b4 data is stored using push
• DTPR (Data Pointer)
– 16-bit reg-has DPH (higher byte) & DPL(lower byte)
– Of 16-bit external data RAM addrss.
• Port 0-3 Latches & Drivers- alloted to 4 ports.
• Serial data Buffer –
– contains 2 independent registers.
– Transmit buffer & receive buffer.
• Timer Registers-T0 , T1
two 16-bit registers accessed as lower and higher bytes.
TH0 &TL0, TH1 & TL1
Control Registers- status & control Registers
TCON
TMOD
PCON
SCON
IP (Interrupt Priority)
IE (Interrupt Enable)
Timing & Control Unit
all timing& controlling operations of internal ckt & controls external bus.
Instruction Register
PC(Program Counter)
RAM & RAM Address Register (128 bytes of internal RAM m/m)
ALU performs arith. & logic operns over operands held by temporary reg TMP1,TMP2
P1.0 1 40 Vcc
P1.1 2 39 P0.0(AD0
P1.2 3 38 )P0.1(AD1)
P1.3
P1.4
4
5
8051 37
36
P0.2(AD2
P
) 0.3(AD3)
P1.5 6 35 P0.4(AD4)
P1.6 7 34 P0.5(AD5)
P1.7 8 33 P0.6(AD6)
RST 9 32 P0.7(AD7)
(RXD)P3.0 10 31 EA/VPP
(TXD)P3.1 11 30 ALE/PROG
(INT0)P3.2 12 29 PSEN
(INT1)P3.3 13 28 P2.7(A15)
(T0)P3.4 14 27 P2.6(A14
(T1)P3.5 15 26 )P2.5(A13
(WR)P3.6 16 25 P
) 2.4(A12
(RD)P3.7 17 24 )P2.3(A11)
XTAL2 18 23 P2.2(A10)
XTAL1 19 22 P2.1(A9)
GND 20 21 P2.0(A8)
Pin Layout
• The 8051 is a 40 pin device, but out of
these 40 pins, 32 are used for I/O.
• 24 of these are dual purpose, i.e. they can
operate as I/O or a control line or as part of
address or date bus.
Pins of 8051 ( 1/4 )
• Vcc ( pin 40 ):
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND ( pin 20 ): ground
• XTAL1 and XTAL2 ( pins 19,18 ):
– These 2 pins provide external clock.
– Way 1 : using a quartz crystal oscillator
– Way 2 : using a TTL oscillator
– Example 4-1 shows the relationship between XTAL
and the machine cycle.
Pins of 8051 ( 2/4 )
• Vcc ( pin 40 ):
– Vcc provides supply voltage to the chip.
– The voltage source is +5V.
• GND ( pin 20 ): ground
• XTAL1 and XTAL2 ( pins 19,18 ):
– These 2 pins provide external clock.
– Way 1 : using a quartz crystal oscillator
– Way 2 : using a TTL oscillator
– Example 4-1 shows the relationship between XTAL
and the machine cycle.
Pins of I/O Port
P0
While accessing external memory provides lower
order byte of address (A0-A7)
Otherwise acts as normal port line
Ports of 8051 - Port1
P1:
Port 1 has no dual function. It is simply used as
programmable bi-directional I/O Port.
Ports of 8051– Port2
P2:
While accessing external memory provides higher order
byte of address (A8-A15)
Otherwise acts as normal port line
ADDR CO NTRO L
V C C IN T E R N A L
P U L L -U P
READ *
LATC H
P 2 .X
M UX
P IN
IN T .B U S D Q
P 2 .X
W R IT E LATC H
Q
TO CL Q 1
LATCH
READ
P IN
Ports of 8051- Port3
P 3 .X P3.4 T0 Timer 0
P IN external input
IN T .B U S D Q
P3.5 T1 Timer 1
P 3 .X Q1 external input
W R IT E LATCH
P3.6 WR External Data
TO CL Q memory write
LATCH store
JB Jump if bit=1
SJMP
ACALL,AJMP
LCALL,LJMP
LJMP(long jump)
LJMP is an unconditional jump. It is a 3-byte instruction. It
allows a jump to any memory location from 0000 to FFFFH.
AJMP(absolute jump)
In this 2-byte instruction, It allows a jump to any memory
location within the 2k block of program memory.
SJMP(short jump)
In this 2-byte instruction. The relative address range of 00-
FFH is divided into forward and backward jumps, that is ,
within -128 to +127 bytes of memory relative to the address of
the current PC.
CALL Instructions
Another control transfer instruction is the CALL instruction,
which is used to call a subroutine.
• LCALL(long call)
This 3-byte instruction can be used to call subroutines
located anywhere within the 64K byte address space
of the 8051.
• ACALL (absolute call)
ACALL is 2-byte instruction. the target
address of the subroutine must be within 2K
byte range.
ACALL: Absolute Call
8051 Instruction Set
JC: Jump if Carry Set PUSH: Push Value Onto Stack
ADD, ADDC: Add Acc. (With Carry) JMP: Jump to Address RET: Return From Subroutine
AJMP: Absolute Jump JNB: Jump if Bit Not Set RETI: Return From Interrupt
ANL: Bitwise AND JNC: Jump if Carry Not Set RL: Rotate Accumulator Left
CJNE: Compare & Jump if Not Equal JNZ: Jump if Acc. Not Zero RLC: Rotate Acc. Left Through Carry
CLR: Clear Register JZ: Jump if Accumulator Zero RR: Rotate Accumulator Right
CPL: Complement Register LCALL: Long Call RRC: Rotate Acc. Right Through Carry
DIV: Divide Accumulator by B MOVC: Move Code Memory SUBB: Sub. From Acc. With Borrow
DJNZ: Dec. Reg. & Jump if Not Zero MOVX: Move Extended Memory SWAP: Swap Accumulator Nibbles
JBC: Jump if Bit Set and Clear Bit ORL: Bitwise OR XRL: Bitwise Exclusive OR