Digital Circuits Test 4

Number of Questions: 25 Time: 60 min.

Directions for questions 1 to 25: Select the correct alterna- If the counter starts from reset, the above configuration
tive from the given choices. works as
1. The ripple counter shown in figure works as a (A) Modulo – 2n twisted ring counter
(B) Modulo – n ring counter
(C) Modulo – 2n Johnson counter
(D) Modulo – 2n ring counter
J A J B J C 6. Consider the following circuit with initial state Qo= Q1
clk = 0. The D flipflops are positive edge triggered.
K A K B K C X
1 1 1 D Q D Q Y
preset preset
preset clk Q

(A) Mod-6 up counter (B) Mod-5 up counter

(C) Mod-5 Down counter (D) Mod-6 Down counter Consider the following timing diagrams of X and clk.
2. Consider the given circuit Which one is the correct wave form of Y?
A clk

X X

clk (A)
Y (B)
In this circuit, the race around condition (C)
(A) does not occur (D)
(B) occurs when clk = 0 7. Six JK Flip flops are cascaded to form the circuit shown
(C) occurs when clk = 0, A = 1 and X = Y = 1 in figure. Clock pulses at a frequency of 128 kHz are
(D) occurs when clk = 1, A = 1 applied as shown, The frequency (in kHz) of the wave
3. Three, modulo-4 counters are cascaded together then form at Q4 is ___________.
the resultant counter modulus is
(A) 3 × 4 (B) 34
(C) 4 × 4 × 4 (D) 3 + 4
1 T Q T Q 1 T Q 1 T Q 1 T Q
4. Which of the following flipflop configuration works as 1
1 T Q
T flip flop?
J Q clk
T
D Q (A) 32 kHz (B) 16 kHz
(A) Q
(B) T
K
clk Q (C) 8 kHz (D) 4 kHz
clk
8. The following truth table has to be realized with D flip
J Q
flop.
T D Q
(C) T (D) XY Qn+1
K Q
clk Q 00 Qn
clk 01 1
5. ‘n’ bit Binary UP counter is connected to n × 2n 10 0
Demultiplxer with input I = 1, as shown in the figure.
11 Qn
reset
Q0 S0 X Combin D Q
Q1 S1
ational
n × 2n
n bit logic
Demultiplexe output
Binary UP circuit
Y Q
clk Qn-1 Sn-1 I

1 clk clk
3.200 | Digital Circuits Test 4

Then what is the equation of combinational logic cir- (A) 10

cuit output in terms of X, Y and Qn? (B) 9
(A) D = X Qn + Y Qn (B) D = X Qn + YQn (C) 16
(D) a large memory block will be erased
(C) D = XY ∑ Qn (D) D = (X + Y) ∑ Qn
12. The following program reads one data byte (X) at a
9. A clocked sequential circuit has 3 states A, B, C and time from input port1.
1 input X. As long as input X = 0, the circuit alternates IN PORT1
between states A and B, if input X = 1(either in state MVI B, 20H
A or B), The circuit goes to state C and remain in state
CMP B
C as long as X = 1, from state C, circuit returns to state
JC REJECT
A when input X = 0, and then a repeats its behavior.
JM REJECT
Assume A = 01, B = 10, C = 11 the state diagram will
STA 3010H
be?
JMP ACCEPT
01 01 REJECT: JMP INVALID
0 0 0 1 Indentify the range of number is Decimal that will
1 0
0 transfer the program to location INVALID.
0 1
(A) 11 10 (B) 10 11 (A) 20H < X < A0H
1 0 (B) X < 20H and X > A0H
(C) X < 32 and X > 160
1
(D) 32 < X < 160
11 01
1 1 13. At the end of the following program
1
0 1 0 LXI SP, 31AE H
0
0 0 MOV C, 00H
(C) 01 10 (D) 11 10
PUSH B
1 POP PSW
10. Find the state (AB) diagram for the following sequen- RET
tial circuit? (A) The contents of Accumulator has been reset
(B) All the flags has been reset
A A B B
(C) The contents of Accumulator and Register B has
been swapped.
T T
(D) Program status word is loaded on stack.
Clock 14.
IO/M A14 A15

E1 E2 E3 RD
11 11
00 00 O7 WR
MSB
C O W
A13 3 to 8
(A) 01 10 (B) 10 01 A12 Decoder O
A11 3 R/W memory
O0 A10 2048 × 8
00
10
A0
Data
(C) 01 11 (D) None of these lines
D7 D0

11. The following program is intended to clear mem- A R/W memory is interfaced with 8085 microprocessor
ory locations starting from memory address 0000H. as shown. What is the range of memory map connected
How many memory locations will be cleared? to O3 line.
(A = 01H) (A) 6800 – 6FFFH (B) 9000 – 98FFH
LXI H, 0010H (C) 9800 – 9FFFH (D) 2300 – 2FFFH
ORA A 15. If we use all output lines (O7 – O0) of the above decoder
loop: MVI M,00H circuit to select eight memory chips of the same size
DCX H (2048 × 8). What is the total range of the memory map?
JNZ loop (A) 8000 – BFFFH (B) 9000 – CFFFH
HLT (C) 7000 – AFFFH (D) 0800 – ABFFH
 Digital Circuits Test 4 | 3.201

16. The following program get a data byte Byte 1 to 22. The waveforms of a counter are shown below, this is a
Accumulator, then the output at PORT address
1 2 3 4 5 6 7 8 9 10
01H is? clk
MVI A, Byte 1
ORA A Q
JM OUTPUT
OUT 01H Q
HLT Q
OUTPUT: CMA
ADI 01H
OUT 01H Q
HLT
(A) positive numbers except 00H, 01H
(B) negative numbers (A) synchronous BCD counter
(C) negative numbers except 00H, 01H (B) ripple counter
(D) positive numbers and negative numbers 2’s (C) ring counter
complement (D) twisted ring counter
17. Which one of the following is not true during the exe- 23. Symmetrical square wave of time period 200 µs can be
cution of an interrupt service routine, which does not obtained from square wave of time period of 20 µs by
contain any EI instruction? using a
(A) The µP can be interrupted by a non maskable (A) 4-bit binary counter
interrupt (B) divide by 5 counter
(B) The µP cannot be interrupted by any interrupt (C) BCD counter
(C) The µP cannot be interrupted by a maskable (D) divide by 5 counter followed by a divide by 2
interrupt counter
(D) All interrupts except the non maskable interrupt
are disable. 24. The outputs Q and Q of a master slave SR flipflop are
connected to its R and S inputs respectively. What hap-
18. Match with the semiconductor technology used for
pens to output Q when clock pulses are applied.
fabrication
(A) permanently 0
List-I List-II (B) permanently 1
P. dynamic RAM 1. bipolar technology (C) fixed 0 or 1
Q. static RAM 2. MOS technology (D) complementing with every clock pulse
R. EPROM 3. either bipolar or MOS technology 25. A 3 bit gray counter is used to control the output of the
multiplexer as shown in figure, the initial state of the
(A) P – 2, Q – 1, R – 2 (B) P – 1, Q – 2, R – 3 counter is 000. The output is pulled high, the output of
(C) P – 2, Q – 3, R – 2 (D) P – 2, Q – 1, R – 3 the circuit follows the sequence
19. The resolution of a D/A converter is approximately 0.4
A2
percent of its full scale range. It is 3 bit Gray
(A) an 8 bit converter (B) a 10 bit converter Counter A1 5V
(C) a 12 bit converter (D) a 16 bit converter A0
S0 S1 R
E
20. For a 12 bit A/D converter the range of input signal 4×1
is 0 to +10V. The voltage corresponding to 1 LSB will I0 0 MUX o/p
be Clk
I1 1
(A) 0 (B) 0.0012V I2 2
(C) 0.0024V (D) 0.833V 3
I3
21. A D/A converter has 5 V full scale output voltage and
an accuracy of + 0.2%, the maximum error for any out- (A) 1, I0, I1, 1, 1, I3, I2, 1, 1
put voltage will be (B) I0, 1, 1, I1, I3, 1, 1, I2, I0
(A) 5 mV (B) 10 mV (C) I0, 1, I1, 1, I2, 1, I3, 1, I0,
(C) 20 mV (D) 30 mV (D) 1, I0, 1, I1, I2, 1, I3, 1, I
3.202 | Digital Circuits Test 4

Answer Keys
1. D 2. D 3. C 4. D 5. D 6. A 7. D 8. A 9. C 10. B
11. D 12. C 13. B 14. C 15. A 16. D 17. B 18. C 19. A 20. C
21. B 22. D 23. D 24. D 25. B

Hints and Explanations

1. All flipflops have J = K = 1, so all are toggle switches fclk
The output of flipflop is connected to rising edge clk 7. The frequency of Qo =
2
input of next flip flop, so Down counter. clk input is fclk 2 fclk
given to flip flop A. (LSB). Frequency of Q1 = =
Preset is active high, so as preset = 1, all flip flops get 2 4
111, so AND gate o/p = 1, when A = 1, B = 0, C = 0 as fclk 4 fclk
Frequency of Q2 = =
A, B , C are inputs, so the CBA = 001, modulus 2 8
= 111 – 001 = 6. Choice (D) fclk
Frequency of Q3 =
2. The given circuit is T latch, The input A is connected 16
to first two NAND gates (J, K inputs connected together to fclk 128
make T latch) Frequency of Q4 = = = 4 kHz
32 32
So race around condition occurs when A = 1, clk = 1.
 Choice (D) fclk
Frequency of Q5 =  Choice (D)
3. When two counters are connected in cascade, the resul- 64
tant modulus is the multiplication of the individual 8. The given XY flip flop truth table is
modulus.
X Y Qn Qn+1
So 3 counters are connected so resultant modulus
0 0 0 0
= 4 × 4 × 4 = 64. Choice (C)
0 0 1 1
4. JK flip flop works as T flip flop if J = K = T 0 1 0 1
For D flip flop Qn+1 = D, Qn+1 = T ⊕ Qn(T flip flop) 0 1 1 1
So by taking D = T ⊕ Qn we get T flip flop. 1 0 0 0
 Choice (D) 1 0 1 0
5. n bit binary UP counter counts in Binary sequence, 1 1 0 1
so same binary sequence is applied to Demultiplexer, 1 1 1 0
so input I = 1, will be at output in sequence, for 3 bit
example. Y Q
X 00 01 11 10
Q2 Q1 Q0 S2 S1 S0 Y0 Y1 Y2 …. Y7 0 1 1 1
000 000 1 0 0 …… 0 1 1
001 001 0 1 0 …… 0
010 010 0 0 1 …… 0 Qn+1 = X Qn + Y Qn
The characteristic equation of D flip flop is Qn+1 = D,
It works like a module 2n ring counter. Choice (D)
This has to work like above XY flip flop. By equating
6. For D flip flop whatever input we apply, same output we Qn+1 = D = X Qn + Y Q n  Choice (A)
get after clk pulse 9. A = 01, B = 10, alternate states when X = 0
Clk
1
X
11
Qo
1
0 1
Q0
D1 0 0
01 10 01 10
Q1 0 0

When X = 1, A, B go to state C = 11 as long as X = 1,

 Choice (A) C will remain in same state
 Digital Circuits Test 4 | 3.203

When X = 0, C will return to state A = 01 So contents of flag register were made reset.
 Choice (C)  Choice (B)
10. Let us consider states as AB if initially state of the cir- 14. For the decoder to be enabled E2 = AM = 0, E3 = A15 = 1,
cuit is 00 (reset) E1 = IO/ M = D for memory operation
TA TB Address range is to select O3, A13 A12 A11 – 011
Clk AB
(A + B) (A + B)
1
A15 A14 A13 A12 A11 A10 A9 A8 A7 ......... A0
0 00 If initially at 00 state, 1 0 0 1 1 0 0 0 0…..0 → 9800H
0 1
1 01 after 3 Clk pulses it
1 1 1 0 0 1 1 1 1 1 1…..1 → 9FFFH
2 10 comes back to same
1 0
3 00 state 00.  Choice (C)
If initial state is 11, it 15. Eight memory chips are used each of size 2048 × 8
0 11
1 1 goes to 00 state after
1 00 ⇒ 2k Bytes
clock pulse
So total size = 8 × 2k = 16k Bytes
11 Oo will be selected when A13 A12 A11 are 000 and 07 will
00
be selected when A13 A12 A11 are 111. The range can be
known by the first address of memory connected to O0
10 01 to last address of memory connected to 07

 Choice (B) A15 A14 A13 A12 A11 A10 A9 A8 A7 .. A0

1 0 0 0 0 0 0 0 0…..0 → 8000H
11. LXI H, 0010 H → Load HL = 0010
1 0 1 1 1 1 1 1 1…..1 → BFFFH
ORA A → OR Accumulator with itself
A = A + A → contents will be same but flags will change Range = 8000 – BFFFH Choice (A)
as per result So Z = 0, (A ≠ 00H) 16. MVI A, Byte 1 – load A = Byte 1
MVI M, 00H → Copy 00H to memory location M ad- ORA A → OR Accumulator with A itself
dress specified by HL register pair. A = A + A → all flags will be set as per Byte 1
DCX H → Decrement HL register pair but this instruc- JM OUTPUT → if sign = 1 (negative number) to go
tion will not effect the flags. output else go to next instruction.
JNZ loop – If No zero flag go to loop, else Halt. OUT 01H → Display Accumulator at port Address
but zero flag = 1 because ORA A instruction and this 01H. (positive numbers)
will iterate infinitely and a large memory block will be HLT – stop
erased. Choice (D) OUTPUT: CMA – Complement Accumulator
12. IN Port 1 – take input from port 1 to Accumulator ADI 01H → Add 01H to Accumulator
MVI B, 20 H → Copy 20H to B = B = 20 H Now the contents of Accumulator are in 2’s comple-
CMP B → compare B with Accumulator ment OUT 01H → Display Accumulator at port Ad-
This will be performed by subtraction of (Accumulator dress 01H. So positive numbers and 2’s complement of
– B) if input byte is X, then as per X – B the flags will negative numbers will be given to OUT port Address
be effected. 01H. Choice (D)
We will get a carry flag when X – 20H < 00H [CY = 1] 17. Choice (B)
We will get a sign flag when X – 20 > 80H [S = 1]
JC REJECT – Jump on carry to REJECT location 18. Choice (C)
(CY = 1) 19. Resolution = 0.4% of full scale
JM REJECT – Jump as Minus to REJECT location
0.4 FSV
(S = 1) = × F .S .V =
So X < 20H = (32)D 100 250
X > A0H = (160)D Choice (C) FSV
Resolution =
13. LXI SP, 31AEH → load SP = 31AE, initialization of 2n
stack pointer So 2n ≈ 250 approximately n = 8 Choice (A)
MOV C, 00H → The contents of C were reset C = 00H
PUSH B → The contents of BC register pair loaded on 20. Resolution = 1
top of stack. FSV 10 10
POP PSW → retrieve the top of stack (now BC) to pro- LSB = 12
= 12 = = 0.0024V
2 2 4096
gram status word (Accumulator + Flag register)
So Accumulator = B, Flags = C = 00H  Choice (C)
3.204 | Digital Circuits Test 4

21. Error = Full scale output × Accuracy 25.

0.2 A2 A1 A0 E S1 S0 o/p
= 5V × = 10mV Choice (B)
100 000 000 I0
22. By observing sequence 0000 → 1000 → 1100 → 1110 001 100 1
→ 1111 → 0111 → 0011 → 0001 → 0000 011 101 1
It is twisted ring counter. Choice (D) 010 001 I1
23. As symmetrical square wave is required and time period 110 011 I3
got multiplied 10 times (i.e., frequency is divided 111 111 1
10 times) 101 110 1
But BCD counter will not give symmetrical square 100 010 I2
wave so divide by 5 counter followed by divide by 000 000 I0
2 counter is correct. Choice (D)
Enable is active low, when E = 1, the output is logic 1
24. Q is connected to R, Q to S input When E = 0, output is from multiplexer.
 Choice (B)
So Qn+1 = S + R Qn = Q n + Q n .Qn
So Qn+1 = Q n so next state is complement of present
state. Choice (D)