Digital Circuits Test 3

Number of Questions: 25 Time: 60 min.

Directions for questions 1 to 25: Select the correct alterna- (A) x1 y, z (B) x + y1, z1
tive from the given choices. (C) x, z (D) x1 + y, z
1. Assume the propagation delay time of 2 input gates 9. In the above problem statement, how many number of
as EXOR-20ns, AND – 10ns, OR-10ns, the propaga- NOR are gates required implement output B.
tion delay time for sum and carry output of a full adder (A) 3 (B) 4
circuit are respectively, when all the data inputs are (C) 5 (D) 6
applied simultaneously? 10. A combinational circuit takes 2 inputs and output is the
(A) 30ns, 20ns (B) 40ns, 30ns 2’s complement of input binary number. Consider the
(C) 40ns, 20ns (D) 20ns, 20ns inputs as a and b and output as x and y, the equations of
2. The minimized POS expression of the function x and y respectively?
f(A, B, C, D) = AB + A C + C + AD + A B C + ABC (A) a ⊙ b, b (B) a1 b, a ⊙ b
(C) a b, ab
1 1
(D) a ∑ b, b
(A) A + C (B) A + B
11. If X3 X2 X1 X0 are the inputs are Y3 Y2 Y1 Y0 are the
(C) AC (D) A + C outputs for the following PROM circuit, then the
3. The signed two’s complement representation of (–783)10 is output is?
(in HEX)?
0 X X
(A) 830FH (B) 04F1H
1 X
(C) FCF1H (D) F3F1H 2 X X X

4. The two numbers represented in signed 2’s comple- BCD

3 X X

ment form are P = 11011101 and Q = 11100101, 4

X3 Decoder X X
5
if Q is subtracted from P, the value obtained in signed X2 X
6
2’s complement form is? X1 7 X X

(A) 11110111 (B) 11000010 X0 8 X

(C) 11111000 (D) 00000111 9 X

5. The subtraction of a binary number B from another

binary number A, done by adding the 2’s complement
of B to A, results in a binary number without carry, this
implies that the result is Y3 Y2 Y1 Y0
(A) negative and is in normal form
(B) positive and is in normal form (A) 2’s complement of input
(C) negative and is in 2’s complement form (B) 8’s complement of input
(D) positive and is in 2’s complement form (C) 9’s complement of input
6. f(a, b, c) = ab + b1c in the canonical POS form is repre- (D) 10’s complement of input
sented as 12. To construct a 5 to 32 line decoder, how many num-
(A) (a + b + c) (a + b + c1) (a + b1 + c) (a1 + b1 + c) ber of 3 to 8 line decoders and 2 to 4 line decod-
(B) (a + b1 + c) (a + b1 + c1) (a + b + c) (a1 + b + c) ers are required respectively without using any extra
(C) (a + b + c) (a1 + b1 + c) (a + b1 + c) hardware?
(D) (a1 + b + c) (a1 + b1 + c) (a + b + c) (a + b1 + c) (A) 3, 2 (B) 4, 1
7. The Essential prime Implicants of the function (C) 2, 4 (D) 2, 2
13. Parity is a common error detection mechanism that
f(A, B, C, D) = AC + ABD + AB + B D + A B C D are
is often used in data reception or retrieval systems.
(A) BD, B D, A (B) AC , B D, B Consider a parity encoder that is used for data trans-
mission or storage. If a word contains an even number
(C) BD, AC , B (D) A B, B D, C
of 1’s, the parity bit is 0. If the word has odd number
8. A combinational circuit has 3 inputs x, y, z and three of 1’s the parity bit is 1. If the data is w, x, y, z then the
outputs A, B, C. When the binary input is 4, 5, 6 and 7, min terms for parity bit is?
the binary output is 2 less than the binary input. When (A) ∑m(1, 2, 4, 7, 8, 11, 13, 14)
the binary input is 0, 1, 2 and 3, the output is 4 more (B) ∑m(0, 3, 5, 6, 9, 10, 12, 15)
than the binary input the Boolean expression for output (C) ∑m(0, 1, 3, 5, 8, 10, 13, 15)
A and C respectively are? (D) ∑m(1, 3, 5, 7, 9, 11, 13, 15)
 Digital Circuits Test 3 | 3.195

14. Consider the Boolean functions (A) Q, R (B) P, R

f1(A, B, C, D) = AC + BD (C) P, S (D) R, S
f2(A, B, C, D) = ∑m(4, 5, 6, 7, 10, 11, 14, 15) 19. The output of the following Demultiplexer circuit is
Then find f1 + f2 in minimized POS form
( A + B) ( B + D) ( A + B + C )
0
(A) 3×8 1
Demultiplexer 2
(B) (A + B) (B + C) ( A + C + D ) 3
a I
4
(C) ( A + B) ( B + D) ( A + C + D ) 5
f(a, b, c, d)

6
(D) ( A + D) ( B + C ) ( A + B + C ) S1 S2 S0
7

15. The Boolean function f(a, b, c) = a1 b + b1 c + ac1 has to be

implemented by the following 2 × 1 multiplexer then b c d
the gate 1 and gate 2 are respectively? (A) a(b ⊙ c) (B) a(b ⊙ c)
(C) (a ⊙ b)c (D) (a ⊙ b)c
b
gate 1 I0 20. For a 4 bit magnitude comparator with two inputs each
c
2×1
of 4 bit A(a3, a2, a1, a0) and B(b3, b2, b1 b0), the Boolean
Y f(a, b, c)
Multiplexer equation for A < B is?
b
(A) a3 b3 + a2 b2 + a1 b1 + a0 b0
1 1 1 1
gate 2 I1
c
S
(B) a3 b3 + (a3 ⊕ b3) a2 b21 + (a3 ⊕ b3) (a2 ⊕ b3)
1

a a2 b11 + (a3 ⊕ b3)(a2 ⊕ b2) (a1 ⊕ b1) a0 b01

(A) OR, NAND (B) AND, OR (C) a3 b3 + (a3 ⊙ b3) a2 b2 + (a3 ⊙ b3) (a2 ⊙ b2)
1 1

(C) NOR, AND (D) NAND, OR

a11 b1 + (a3 ⊙ b3) (a2 ⊙ b2) (a1 ⊙ b1) a10 b0
16. Consider the NMOS circuit here, find the output
(D) a31 b3 + (a3 ⊕ b3) a2 b2 + (a3 ⊕ b3) a1 b1 +
1 1
VDD
(a3 ⊕ b3)(a2 ⊕ b2)(a1 ⊕ b1) a0 b0
1

Vout =
A
21. For an open collector TTL gate has the specifications
C VOH = 2.4 V, VOL = 0.4V, IOH = 250 µA, IOL = 16mA,
B
IIH = 40 µA, IIL = –1.6 mA
Find the fan out for TTL gate specified
(A) 6 (B) 8
(A) (A + B)C (B) ( A + B) C (C) 10 (D) 16
22. An 8 × 1 multiplexer has inputs A, B, C connected
(C) AB + C (D) AB + C
to the selection inputs S2, S1 and S0 respectively. The
17. If the Boolean function f(a, b, c, d) = a + b + c + d has data inputs I0 through I7 are as follows. I1 = I2 = 0;
to be implemented with only 2 input NAND gates, then I3 = I5 = I7 = 1; I0 = I4 = D; and I6 = D1 then the Boolean
how many NAND gates are required? function that the multiplexer implements is?
(A) 6 (B) 7 (A) AB + BC + AC D + B C D
(C) 8 (D) 9
18. Which of the following multiplexer implements 2 input (B) AC + BD + AB D + B C D
NAND gate? (C) BCD + ABD + BC + AC
a1 I0 a1 I0 (D) AB D + B C D + AC + BC
Y Y
(P) 0 I1 (Q) b1 I1 23.
S S y
x z

b b x x x x
x x x x
b1 I0 1 I0 x x x
Y Y x x x
(R) a1 I1 (S) b1 I1 x x x
S S
f1 f2 f3
b b
3.196 | Digital Circuits Test 3

In the above PLA implementation the Boolean func- AB

CD 00 01 11 10
tions
(A) f1 = f2 (B) f1 = f3 00 0 0 X
(C) f2 = f3 (D) f1 ≠ f2 ≠ f3
01 X X X
24. When a logic gate is driving another logic gate,
the condition which must be satisfied for proper 11 0 0 0
operation is
(A) VOH > VIH and VOL > VIL 10 0 0 0
(B) VOH < VIH and VOL > VIL
(C) VOH > VIH and VOL < VIL
(D) VOH < VIH and VOL < VIL (A) A + B (B) AB
25. The minimized POS expression for k-map shown (C) ( A + B ) ( A + B ) ( A + B) (D) A ( A + B )
is

Answer Keys
1. B 2. D 3. C 4. C 5. C 6. B 7. A 8. D 9. C 10. D
11. C 12. B 13. A 14. B 15. A 16. D 17. D 18. D 19. B 20. C
21. A 22. C 23. C 24. C 25. B

Hints and Explanations

1. Sum = a ⊕ b ⊕ c P – Q = –35 – (–27) = –8 = 1111 1000 (in signed 2’s
Carry = ab + bc + ac complement form)
a (or)
b Sum P = 1101 1101
c Q = 1110 0101 (direct subtraction)
1111 1000 Choice (C)
20 + 20 = 40 ns
5. A – B has to be performed
a
b So the 2’s complement of B (which is 2n – B, n = no. of
bits in B) is added to A
b
c So result is A + 2n – B; and there is no carry
a
A + 2n – B = 2n – (A – B)
c So the result is negative and it is in 2’s complement
10 + 10 + 10 = 30 ns form. Choice (C)
Two level exor gate for sum 6. f(a, b, c) = ab + b1.c
So 20 + 20 = 40 ns = (ab + b1)(ab + c) [x + yz = (x + y)(x + z)]
Carry will be implemented with 2 input gates in = (a + b1)(a + c)(b + c)
3 levels, so 10 + 10 + 10 = 30 ns Choice (B) = (a + b1 + c.c1)(a + b.b1 + c)(a.a1 + b + c)
= (a + b1 + c)(a + b1 + c1)(a + b + c)(a + b1 + c)
2. f = AB + AC + C + AD + AB C + ABC (a + b + c) (a1 + b + c)
= AB + A + C + AD + AC = (a + b1 + c)(a + b1 + c1)(a + b + c)(a1 + b + c)
= A(B + 1 + D + C) + C = A + C Choice (D)  Choice (B)
3. 783 = 512 + 256 + 8 + 4 + 2 + 1 = 1100001111
+ 783 = 0000 0011 0000 1111 (add 0’s to MSB) 7. f(A, B, C, D) = A C + ABD + A B + B D + A B C D
– 783 = 1111 1100 1111 0001 (2’s complement of Product term Equivalent Min terms
+783)
In HEX ⇒ FCF1 Choice (C) AC 0X1X 0010, 0011, 0110, 0111

4. P = 11011101 ABD 11X1 1101, 1111

00100011 (by taking 2’s complement) AB 01XX 0100, 0101, 0110, 0111
P = –35
BD X0X0 0000, 0010, 1000, 1010
Q = 11100101
00011011 (By taking 2’s complement) 0001 0001
A BC D
Q = –27
 Digital Circuits Test 3 | 3.197

f(A, B, C, D) = ∑m(0, 1, 2, 3, 4, 5, 6, 7, 8, 10, 13, 15) a b x y

CD 0 0 0 0
AB 00 01 11 10 0 1 1 1
00 1 1 1 1 1 0 1 0
1 1 0 1
01 1 1 1 1
x = a1b + ab1 = a ⊕ b
11 1 1
y = b Choice (D)
11. From the circuit diagram, we can write truth table
10 1 1
X3 X2 X1 X0 Y3 Y2 Y1 Y0
0 0 0 0 1 0 0 1
0 0 0 1 1 0 0 0
f(A, B, C, D) = A + BD + BD 0 0 1 0 0 1 1 1
Essential prime implicants are A , BD, B D 0 0 1 1 0 1 1 0
0 0 1 1 0 1 1 0
 Choice (A)
0 1 0 0 0 1 0 1
8. The truth table is
We can observe that output is 9’s complement of input.
x y z A B C
0 0 0 1 0 0 output is 4 more
 Choice (C)
0 0 1 1 0 1 than input 12. 5 to 32 line decoder will have 32 output lines
0 1 0 1 1 0
0 1 1 1 1 1
So 4, 3 to 8 line Decoders are required, these 4 decod-
1 0 0 0 1 0 ers will be selected by one 2 to 4 lines decoder.
1 0 1 0 1 1 output is 2 less So 4, 3 to 8 line decoder and 1, 2 to 4 line decoder (or)
1 1 0 1 0 0 than input
1 1 1 1 0 1
5 to 32 line decoder will have 32 output lines
So 8, 2 to 4 line Decoders are required, to select one of
these 8, one 3 to 8 line Decoder is required.
A(x, y, z) = ∑m(0, 1, 2, 3, 6, 7)
8, 2 to 4 Decoders, and 1, 3 to 8 Decoder. Choice (B)
B(x, y, z) = ∑m(2, 3, 4, 5)
C(x, y, z) = ∑m(1, 3, 5, 7) 13. For even number of 1’s parity bit is 0.
The k map for A So even parity,
yz
Even parity can be implemented by XOR gate
x 00 01 11 10 XOR of even 1’s given output 0.
0 1 1 1 1 XOR of add 1’s gives output 1.
A = x1 + y So parity bit P = w ⊕ x ⊕ y ⊕ z
1 1 1 P = ∑m(0001, 0010, 0100, 0111, 1000, 1011, 1101,
1110)
The k map for C = ∑m(1, 2, 4, 7, 8, 11, 13, 14) Choice (A)
yz 14. f1(A, B, C, D) = AC + BD
00 01 11 10
x = AC(B + B ) (C + C ) + (A + A ) (C + C )BD
0 1 1 = ∑m(5, 7, 10, 11, 13, 14, 15)
C=z = ΠM(0, 1, 2, 3, 4, 6, 8, 9, 12)
1 1 1
f2 = ∑m(4, 5, 6, 7, 10, 11, 14, 15)
= ΠM(0, 1, 2, 3, 8, 9, 12, 13)
 Choice (D) f1 + f2 = ΠM(0, 1, 2, 3, 8, 9, 12)
9. B(x, y, z) = ∑m(2, 3, 4, 5) [common max terms of f1 and f2]
yz CD
00 01 11 10 00 01 11 10
x AB
0 1 1 00 0 0 0 0
B = xy1 +x1y = x ⊕ y
1 1 1 01

11 0
2 input XOR required 5 NOR gates. Choice (C)
10. a, b are inputs of 2’s complementer, and x, y are the 10 0 0
outputs.
So truth table is
3.198 | Digital Circuits Test 3

(a3 ⊙ b3) (a2 ⊙ b2) a1 b1 + (a3 ⊙ b3)(a2 ⊙ b2)(a1 ⊙ b1)

1
f1 + f2 = (A + B) (B + C) ( A + C + D)
 Choice (B) a10 b0. Choice (C)
15. Given f(a, b, c) = a b + b c + ac
1 1 1
I OH
= a1b + (a + a1)b1c + ac1 21. Fan out (logic 1) = n1 =
I IH
= a1b + a1b1c + ab1c + ac1
= a1[b + b1c] + a[b1c + c1] 250 m A
= = 6.25
= a1[b + c] + a[b1 + c1] 40 m A
By comparing this equation with output of 2 × 1
I OL 16 mA
multiplexer Fanout (logic 0) n0 = = = 10
I IL 1.6 mA
Y = I0 S + I1 S = I0 a + I1 a = [b + c]a1 + [ bc ] a
The overall fanout = min(n1, n0) = 6 Choice (A)
Gate 1 is OR gate, gate 2 is NAND gate. Choice (A)
22. For 8 × 1 multiplexer output
16. For NMOS, when transistors are in series AND opera-
Y = l0 S2 S1 S0 + I1 S2 S1 S0 + I 2 S2 S1 S0 + I 3 S2 S1 S0 +
tion, transistors are in parallel OR operation overall
output is in complement form. I 4 S2 S1 S0 + I 5 S2 S1 S0 + I 6 S2 S1 S0 + I 7 S2 S1 S0
Vout = AB + C  Choice (D)
= A B C D + 0 + 0 + A BC + AB C D + A B C +
17. ABC D + ABC
A
CD
B f 00 01 11 10
AB
C 00 1
D
01 1 1
Each 2 input OR gate required 3 – 2input NAND
gates 11 1 1 1
So total 9 NAND gates are required. Choice (D)
10 1 1 1
18. For multiplexer P, Y = I0 S + I1S = a1 b1 + 0.b
For mux, Q Y = a1 b1 + b1.b = a1 b1
For mux, R, Y = b1.b1 + a1.b = a1 + b1 = (ab)1 = ∑m(1, 6, 7, 9, 10, 11, 12, 14, 15)
For mux, S, Y = 1.a1 + b1.a = a1 + b1 = (ab)1 Y = B C D + ABD + BC + AC  Choice (C)
So, R, S implement NAND gate P, Q implements NOR
gate. Choice (D) 23. The product terms are xz , x y, yz , y z, xy
1 1 1 1 1

So f1 = xz1 + x1y + yz1 = xz1 + x1y [consensus theorem]

19. The demultiplexer output Y0 = I S2 S1 S0 = ∑m(2, 3, 4, 6)
f2 = xz1 + x1y + y1z = ∑m(1, 2, 3, 4, 5, 6)
Y1 = I S2 S1 S0 f3 = x1y + yz1 + y1z + xy1 = ∑m(1, 2, 3, 4, 5, 6)
Y2 = I S2 S1 S0 So f2 = f3 Choice (C)

Y3 = I S2 S1 S0 …. Etc 24. Choice (C)

f(a, b, c, d) = Y0 + Y1 + Y6 + Y7 25. Two octates present so minimized expression is A .B

= ab1c1d1 + ab1c1d + abcd1 + abcd AB
00 01 11 10
= ab1c1 + abc = a[b ⊙ c] Choice (B) CD
00 0 X X
20. If A(a3 a2 a1 a0) and B(b3 b2 b1 b0) are the two inputs the
A < B is possible only when the bits in A are 0 and the 01 X X X
1
bits in B are 1. So we can check MSB by using a3 b3 , if
11 0 0 0
the MSB bits are equal, then we check next bits (a3 ⊙
1
b3) a2 b2 and if the higher order bits are equal then we 10 0 0 0
move to next bits so (A < B) = a3 b3 + (a3 ⊙ b3) a2 b2 +
1 1

 Choice (B)