Digital Circuits Test 2

Number of Questions: 35 Time: 90 min.

Directions for questions 1 to 35: Select the correct alterna- (A) PQ + QR (B) PQR + QR
tive from the given choices.
(C) PR + QR (D) PQ + R
1. The following flip flop is
7. The max term expression of a four variable even
A S Q
function is
clk
(A) π M (0, 2, 4, 6, 8, 10, 12, 14)
B R Q (B) π M(1, 3, 5, 7, 9, 11, 13, 15)
(C) π M (0, 3, 5, 6, 9, 10, 12, 15)
(A) D flip flop when A = 0
(D) π M (1, 2, 4, 7, 8, 11, 13, 14)
(B) D flip flop when A = B
(C) T flip flop when A = 0 8. Find which of the following is not a minimum sum of
(D) T flip flop when A = B the products expression for f(w, x, y, z)
2. The flip flops used in this circuit are master slave JK = Σm(0, 3, 5, 7, 8, 9, 10, 12, 13) + d(1, 6, 11, 14)
flip flops. If the counter is initially at reset state after (A) wz + x y + wx + yz (B) wx + w y + x y + wz
how many clock pulses it gets reset?
(C) x y + wz + wz + yz (D) wz + x y + w y + wz
Jo Qo J1 Q1 9. The input clock frequency is 10kHz, then the
clk clk frequency of Y is (initially Q = 0)
1 Ko Qo K1 Q1 1 J Q Y
clk clk
K Q
(A) 2 (B) 3
(C) 4 (D) 1
3. (A) 5 kHz (B) 10 kHz
(C) 2.5 kHz (D) 0 Hz
S Q0 S Q1 S Q2 10. A Hexa Decimal Number X is converted to binary
initially, then all zero and one’s are interchanged with
R Q0 R Q1 R Q2
1’s and 0’s. Then it was incremented by 1 in binary,
finally the binary number was converted back to Hexa
clk Decimal again, this number is
(A) 15’s complement of X.
The above counter shown has initial state Q2 Q1 Q0 = (B) 16’s complement of X + 1.
111(7), then the next states are? (in decimal) (Q2 Q1 Q0) (C) 15’s complement of X + 1.
(A) 7621435 (B) 7352614 (D) 1’s complement of X.
(C) 7324165 (D) 7514236
11. The minimum decimal equivalent of the number
4. If a ≤ b, which of the following is true (21A)x is
(P) a1 + b = 1 (Q) a1≤b1 (A) 538 (B) 1032
(R) ab = 0
1
(C) 263 (D) 220
(A) P, Q (B) P, R
(C) Q, R (D) P, Q, R 12. If (3.5)base 6
+ (2.3)base 6
= (X)base 6
then the value
of X is
5. If a = (b + c) (b1 + c1), then the value of b is
(A) 5.8 (B) 10.2
(A) (a1 + c) (a + c1) (B) a1c + ac1
(C) 6.2 (D) 5.6
(C) a c + a c
1 1 1
(D) (a1 + c1)(a + c1)
13. A number in 4 bit two complement signed representa-
6. Calculate switching function realized by this network
tion is a3 a2 a1 a0. The same number, when stored using
in minimized SOP form.
8 bits will appear like.
P (A) 0000 a3 a2 a1 a0
Q
(B) a3 a3 a3 a3 a3 a2 a1 a0
f (C) a3a2a1a0a3a2a1a0
R (D) a3a3a3a3a3a2a1a0
 Digital Circuits Test 2 | 3.187

14. Suppose that as a result of drift of component values

Y0 etc,. The output may be in error by an amount ∆V. How
Y1 large can ∆V be before the LSB would no longer be
1 I F(a, b) significant?
Y2
(A) 5.51 mV (B) 2.93 mV
S1 S0 Y3
(C) 9.3 mV (D) 3.75 mV
a b 20. A 3 bit Digital to Analog converter is modified as
follows, to make it 6 bit Digital to analog converter.
In the above circuit the function F(a, b) in POS form So what will be the value of resistor ‘r’ for proper
(A) (a + b)(a1 + b1) (B) (a1 + b)(a + b1) operation?
(C) (a + b )(a + b )
1 1 1
(D) (a + b)(a1 + b)
Rf
15. A combinational circuit takes input in the range of 000
to 101, (remaining combinations are unused) The out-
r
put of the circuit is 1 when ever input is a power of 2 (in (-)
Vout
decimal) find the minimized expression for output, if x,
y, z are inputs of the combinational circuit. 4R 2R R 4R 2R R
(A) x1 y ∑ z1 (B) (x + y) ⊙ z
(C) x1 y1 ∑ z (D) (x + y) ∑ z S S S S S S
16.
1 I0 (A) 16 R (B) 8 R
Y1 (C) 4 R (D) 2 R
b1
S 21. The switches Si will be connected to VR = 1V for logic
I1 1, and will be connected to 0V for logic 0. Find the
a F(a, b, c)
I0 output Vo for input S3S2S1S0 = 0101
S
1 I0 S R
Y2 c 2R
1 I1
–
R R R
The function F(a, b, c) is + V0
(A) a1 + b1 + c (B) (abc)1
(C) (a + b )c
1 1 1
(D) (a + b)1 + c1 2R 2R 2R 2R 2R

17. If the following circuit is converted to all-NAND net- S0 S1 S2 S3

work, then how many number of NAND gates are
required? (inverted inputs are available) (A) 0.468 V (B) 5 V
a (C) 7.5 V (D) 0.3125 V
b1
c 22. The following circuit is (0 < VA < VDD)
VDD VDD
d1 f(a, b, c, d, e) VA

(A) 3 (B) 4
(C) 5 (D) 6
18. A 5 × 32 Decoder can be constructed by using
S1: four 3 × 8 Decoders and one 2 × 4 Decoder (A) 1 bit counter
S2: five 2 × 4 Decoders (B) 1 bit memory element
S3: eight 2 × 4 Decoders, one 3 × 8 Decoder (C) 1 bit DRAM cell
S4: four 3 × 8 Decoders (D) 1 bit buffer
Consider all the decoders are having enable input. 23. How many number of 256 × 8 bit RAMs are required to
(A) S1, is true alone (B) S1, S3, S4 are true build 1kB × 16 RAM?
(C) S2, S3 are true (D) S1, S3 are true (A) 5 (B) 6
19. A digital to analog converter accepts 12 input bits, (C) 4 (D) 8
i.e., has a resolution of 12 bits, and provides an output 24. A 2048 × 8 bit memory element is interfaced with 8085
which is 12V maximum. microprocessor, if the address of first memory location
3.188 | Digital Circuits Test 2

in the RAM is 0900H. Then the address of the last A2

memory location will be? A3
(A) 1000H (B) 0FFFH CS
(C) 27FFH (D) 10FFH A4
25. The circuit shown in the figure below works as 2-bit A5 I/O
analog to digital converter for 0 ≤ Vin ≤ 6V. The MSB
of output Y1, expressed as Boolean function of input X3, A6
X2, X1 is given by A7
6V
(A) A8H – ABH (B) 80H – 83H
1kΩ (C) 68H – 6BH (D) 44H – 47H
– X3
1kΩ + 30. MVI A, 69H
X2
CMA
– Y1
Digital MOV B, A
+
Circuit
1kΩ STC
– X1 CMC
+ Y0 RAR
1kΩ
RAR
Vin XRA B
NOP
(A) X1 + X3 (B) X2 + X1 at the end of this program contents of Accumulator,
(C) X3 + X2 (D) X3 Carry are?
26. Two basic TTL gates are connected as shown in the fig- (A) B3, 1 (B) B3, 0
ure, the function f is (C) F3, 1 (D) F3, 0
a TTL 31. MVI A, Byte1
b gate ORA A
f JM Output
c TTL XRA A
d gate Output: OUT Port
HLT
(A) ab + cd (B) (a + b) (c + d) The program will give output,
(C) (a1b1 + c1d1)1 (D) (a1 + b1) (c1 + d1) (A) negative numbers
27. The voltage and current parameters of ECL logic fam- (B) positive numbers
ily are given by (C) odd numbers
VOH = –0.76 V, VIH = –1.1 V, (D) negative numbers or zero
VOL = –1.58 V, VIL = –1.25 V Common Data for Questions 32 and 33:
IOH = 3 mA, IIH = 107 μA, IOL = 3.7 mA, IIL = 137 μA
B 0
The fan out, noise margin of the logic family are? B1
(A) 28, 0.34 V (B) 27, 0.34 V 2×4 1
Decoder 2
(C) 28, 0.33 V (D) 27, 0.33 V C B0
EN 3
28. 4000: L X I SP, 5000 H A
4003: L X I H, 5050 H
4006: SPHL B B1 EN 0
4007: PUSH H 2×4 1
4008: PUSH B Decoder 2
C B0
4009; CALL 4050H 3
400C: POP D
400D: HLT
at the end of this program, contents of SP and PC are
f1 f2
(A) 4FFEH, 400DH (B) 5048H, 400EH
(C) 504EH, 400EH (D) 5052H, 400EH 32. The function f1(A, B, C) in SOP form is
29. An I/O device is interfaced with μP 8085 in the follow- (A) AB + BC (B) AC + B C
ing circuit diagram then the range of address for the
I/O is (C) AB + AC (D) AC + BC
 Digital Circuits Test 2 | 3.189

33. The function f2(A, B, C) in POS form is 34. If the counter is initially at reset state, the total number
(A) B + A (B) A + C states are (i.e., modulus of counter is)
(A) 6 (B) 5
(C) B + C (D) A + C (C) 7 (D) 8
Statement for Linked Answer Question 34 and 35: 35. Initially ABC is 100 then next state of the counter
is?
C1 C B1 B A1 A (A) 100 (B) 101
(C) 111 (D) 110
TC TB TA

clk

C B

C1 B1 C B C B1 C1 A

Answer Keys
1. D 2. B 3. C 4. B 5. B 6. C 7. D 8. A 9. B 10. C
11. C 12. B 13. D 14. B 15. D 16. B 17. A 18. D 19. B 20. C
21. A 22. B 23. D 24. D 25. C 26. D 27. D 28. C 29. D 30. B
31. D 32. B 33. C 34. B 35. C

Hints and Explanations

1. The characteristic equation of SR flip flop is 3.
Qn+1 = S + R Qn S Q D Q
=
Given (from circuit) S = A. Qn , R = B.Qn R Q

Qn+1 = A Qn + B.Qn Qn clk clk

= AQn + B + Qn Qn ( ) We can observe that SR connected in D flip flop mode,
S, R are connected with normal (Q), complemented
Qn+1 = A Qn + B Qn
The equation like JK flip flop
(Q ) out put forms.
We can draw the circuit as follows
(JK equation Qn+1 = J Qn + KQn )
So it works like T flip flop if A = B.
D0 Q0 D1 Q1 D2 Q2
 Choice (D)
2. Master slave flip flop also works like normal flip flop Q
only, to eliminate race around condition in JK latch, we
clk
go for JK master slave flip flop.
From the circuit J0 = Q1 , K0 = 1, J1 = Q0, K1 = Qo From given circuit D0 = Q2, D1 = Q0
( )
D2 = ( Q1 + Q0 ) (Q1 .Q0 ) = ( Q1 + Q0 ) Q1 + Q 0 = Q1 ⊕ Q0
Q1 Q0 J1=Q0 K1= Q0 J0= Q1
clk clk Q2  Q1  Q0 D2=Q1 ⊕ Q0 D1=Q0 D0=Q2
K0=1
0 1   1   1 0 1 1
0 0 0 0 1 11 1 0   1   1 0 1 0
2 0   1   0 1 0 0
1 0 1 1 0 11
3 1   0   0 0 0 1
2 1 0 0 1 01 4 0   0   1 1 1 0
5 1   1   0 1 0 1
3 0 0 6 1   0   1 1 1 1
3 clk pulses required to reset again. 7 1   1   1
 Choice (B)  Choice (C)
3.190 | Digital Circuits Test 2

4. If a ≤ b then yz
wx 00 01 11 10
a b a1 + b ab1 00 1 X 1
0 0 1 0
01 1 1 X
0 1 1 0
1 1 1 0 11 1 1 X

(ab = 10 is not valid condition for a ≤ b) 10 1 1 X 1

We can observe that a1 ≥ b1, so only (P) a1 + b = 1,
(R) ab1 = 0 are true. Choice (B)
wz , x y, wx, yz will not implement the k-map as in the
5. From given a = (b + c)(b + c )
1 1

= bc1 + b1 c = b ∑ c above k-map min term wxyz = 1100 is not covered.

EXOR with c both sides  Choice (A)
a∑c=b∑c∑c=b∑0=b 9. When Q = 0, initially, Q = 1
So b = a ∑ c = a1 c + ac1 or (a + c)(a1 + c1).
So J = K = 1, by applying first clk pulse Qn+1 = 1, Then
 Choice (B)
Q n +1 = 0. So J = 1, K = 0, after clock pulse Qn+2 = 1, …
6.
P PQ
and for next clock pulses it will remain in same state, so
Q the frequency of Q = 0Hz (Q = 1 always) but Q = 1, so
the clk pulse ANDed with Q = 1 and Y is same as clk
pulse so frequency of Y is 10kHz. Choice (B)
f
QR 10. The explained process is converting to binary, and inter-
R
changing 1 to 0’s and 0’s to 1’s, same as 1’s complement
QR in binary, by adding 1 to 1’s complement number we
will get 2’s complement.
QR Converting it back to Hexa Decimal, gives 16’s com-
plement of X, or it is also same as 15’s complement of
f = (PQ + Q R)R = PQR + QR
the Hexa Decimal number X + 1. Choice (C)
= (PQ + Q )R = (P + Q )R = PR + QR 11. Here (21A)x is a number with unknown number
 Choice (C) system x.
7. Even function is a Boolean function, and it will be When we need to find out minimum decimal equivalent
equal to 1, if the input variables have an even number value, then the base of the number system should be
of 0’s. minimum.
(odd function is a Boolean function for which output is Here (A = 10) is the largest number in the number
1, for input combinations with odd number of 1’s) system, so possible base will be 11.
So for 4 variables, even number of zeroes occur for in- So minimum decimal equivalent of (21A)11 = 2 × 112 +
put combinations 1 × 11 + 10 = 263. Choice (C)
0000, 0011, 0101, 0110, 1001, 1010, 1100, 1111 12. 3.5
For these combinations, even function output is 1. + 2.3
So remaining terms are max terms. ?
So feven = ∏M(1, 2, 4, 7, 8, 11, 13, 14) Choice (D) 5+3=8
8. (12)6 so result is 2 and carry is 1.
yz 1
wx 00 01 11 10
3.5
00 1 X 1
+2.3
01 1 1 X ?.2
1+3+2=6
11 1 1 X
(10)6 so result is 0 and carry is 1
10 1 1 X 1 3.5
+ 2.3
10.2 Choice (B)
x y, w z is the essential prime implicants, remaining
13. When a signed integer stored in 2’s complement for-
prime implicants can be used to cover all the min mat, the MSB will give the sign, if MSB = 0, then it’s a
terms. positive number, else if MSB = 1 it’s a negative number.
 Digital Circuits Test 2 | 3.191

When we are extending the number of bits, the sign by using one 3 × 8 Decoder.
of the number should not change, so all negative num- So valid statements are S1 and S3. Choice (D)
bers will be appended with 1’s and all positive numbers 19. The LSB (Least Significant Bit) would be no longer be
will be appended with 0’s. So the same MSB will be significant if ∆V is more than LSB value.
repeated for extra bits on left hand side. So here max output is = 12V.
 Choice (D) Maximum input we can apply (12 bit) = 212 – 1
14. Given circuit is Demultiplexer 12
So resolution = 12 = 2.93 mV
Output equation are Y0 = I S 1 S 0 2 −1
Value of LSB = 2° × resolution = resolution = 2.93mV.
Y1 = I S 1 S0
 Choice (B)
Y2 = I S1 S 0 20. The S2 S1 S0 are lower order bits, S5 S4 S3 are higher
Y3 = I S1 S0 order bits so the current due to bits S2 S1 S0 should be
one eighth of the current due to S5 S4 S3.
F(a, b) = Y 0 .Y 3 = Y0 + Y3 = 1.a b + 1.ab
1 1
The resistor r has been inserted to provide the attenu-
= a1 b1 + ab = (a1 + ab)(b1 + ab) ation.
By applying x + yz = (x + y)(x + z) Such attenuation, is possible when r = 4R. Choice (C)
= (a1 + b)(a + b1) Choice (B) 21. Given circuit is a DAC. (R – 2 R type)
15. If the output of the circuit is F then F(x, y, z) = Σ(1, 2, So the voltage at non inverting terminal is
4) + f d(6, 7) in the given range 000 to 101, only for V
V+ = Rn (S × 20 + S × 21 + S × 22 + S × 23)
inputs 001, 010, 100 output is 1 (min terms) 110, 111 2 0 1 2 3

are unused combinations (don’t cares) 1 5

yz = × (1 + 0 + 4 + 0) =
x 00 01 11 10 16 16
0 1  R  5 3 5 1 15
V0 = 1 +  = × = × = 0.46875 V
1 1 X x  2 R  16 2 16 2 16
 Choice (A)
F(x, y, z) = xz1 + yz1 + x1 y1 z 22. The given circuit has 2 NMOS inverters, connected
= (x + y)z1 + x1 y1 z back to back,
= (x1 y1)1z1 + (x1 y1)z = (x + y)z1 + (x + y)1z
Q
= x1 y1 ⊙ z = (x + y) ∑ z Choice (D)
Q
16. Output of 1 MUX Y1 = 1.a + b .a
st 1 1

= a1 + b1
Output of 2nd MUX Y2 = 1.a + 1.a1 = 1
Output of 3rd MUX F(a, b, c) = Y1.c + Y2.c1 it forms a 1 bit memory element.
= (a1 + b1)c + 1.c1 = a1 + b1 + c1 Choice (B) 1 bit buffer will have 1 input and 1 output
17. Given function has to be in SOP form, so it can Because of feedback connection it will work like basic
be implemented by AND-OR gates, same as memory element latch,
NAND-NAND gates This is the basic structure in SRAM cell, Dynamic
f(a, b, c, d, e) = (a + b1)c + cd1 + (d1 + e) RAM requires only 1 MOSFET for 1 bit storage, as the
= ac + b1 c + cd1 + d1 + e bit will be stored in gate capacitance. Choice (B)
a required memory
a c 23. No. of memory elements =
b Available memory
b1 b1
c = c 1kB × 16 1024 × 16
= = = 8 Choice (D)
d1 d 256 × 8 256 × 8
e e1
24. Address of last memory location – Address of first
= ac + b1 c + d1 + e Choice (A) Memory location
18. 5 × 32 Decoder has 32 outputs, we can built 32 outputs = (Number of address locations – 1)
By using four 3 × 8 Decoders, and again one of these Here given RAM number of address locations = 2048
four 3 × 8 Decoders can be selected by using a 2 × 4 (2048)10 = 0800H
Decoder 0800H – 1 = 07FFH
Similarly we can build 32 outputs by using eight 2 × 4 X – 0900H = 07FFH
Decoders, and one of these 8 Decoders can be selected X = 07FF + 0900H = 10FFH Choice (D)
3.192 | Digital Circuits Test 2

25. The given circuit is flash type ADC, and the Digital cir- 30. MVI A, 69H → A = 69H
cuit is priority Encoder. So when Y1(MSB) = 1, then CMA → complement Accumulator
output can be 11 or 10 so input X3 has to be present or Now A = 96H
if not X3, X2 has to be there Y1 = X3 + X 3 X2 = X3 + X2 MOV B, A → Copy A to B → B = 96 H
(Priority Encoder equation) Choice (C) STC – set carry CY = 1
CMC – complement carry CY = 0
26. Basic TTL gate is NAND gate, and TTL has wired RAR – rotate arithmetically right (Accumulator)
AND operation. 0 0
So given circuit is like 1 0 0 1 0 1 1 0→ 0100 1011
a RAR – rotate arithmetically right (Accumulator)
b 0 0
(ab)1.(cd)1 = (ab + cd)1
or (a1 + b1)(c1 + d1) 0 1 0 0 1 0 1 1→ 0 0 1 0 0 1 0 1
c XRA B – XOR B with Accumulator store in Accumula-
d tor
A=00100101
 Choice (D)
B = 1 0 0 1 0 1 1 0 (XOR)
27. Noise Margin 10110011
∆1 = –0.76 – (–1.1) = 0.34V A = 10110011, CY = 0 (logical operation) Choice (B)
∆0 = –1.25 – (–1.58) = 0.33V
31. MVI A, Byte1 → A = Byte1, copy number to A.
Noise margin is min (∆0, ∆1) = 0.33V.
ORA A – make A + A = A, contents of Accumulator
I OH 3mA remain same but CY = 0, and other flags will change as
Fanout:- N1 = = = 28
I IH 107µA per number in Accumulator.
I OL 3.7mA JM output – Jump on minus to output port if S = 1 go
N0 = = = 27 to output.
I IL 137µA
XRA A – else XOR A with A, A ∑ A = 00H
Fanont = min (N1, N0) = 27 Choice (D) A = 00H
28. As the above programs ends at memory location OUT port → send the contents of Acc to output port
400DH, the address of next memory location is 400EH, HLT – stop.
which will be stored in Program Counter at the end of So if there is any negative number it will be the output
the program. or zero is the output. Choice (D)
L X I SP, 5000H → load SP = 5000H 32. Given is a 3 × 8 Decoder with two 2 × 4 Decoders, and
L X I H, 5050H → load HL = 5050H a NOT gate, LSB are connected to inputs of Decoder
SPHL → move HL to SP, so SP = 5050H (B1 B0 = BC), MSB (A) is connected to check which
PUSH H → SP decremented by 2 (SP – 2) decoder has to be selected by using enable input, When
PUSH B → SP decremented by 2 (SP – 4) A = 0, first Decoder will be selected, when A = 1, sec-
CALL 4050H → after call instruction, again returned ond decoder will be selected.
to next instruction, so no charge for SP. f1 is connected through NOR gate
POP H → increment SP by 2 (SP – 4 + 2) = SP – 2
HLT – stop =
So contents of stack pointer are 5050-2 = 504EH.
 Choice (C)
outputs of Decoder (here active High outputs) are min
29. For the chip select to get enable CS = 0. terms, min terms connected to NOR gate.
Nand gate output = 0, when inputs are 1 and 1. f1 = πM(1, 3, 4, 5, 7) = Σm(0, 2, 6) because in second
So Exor operation of A2, A3 and A4, A5, A6, A7 should decoder A = 1, BC vary as per inputs applied so 4, 5, 6,
be 1. 7 are output of second decoder (min terms)
exor operation gives output 1, when input is having odd f1
number of 1’s BC
A 00 01 11 10
A7 A6 A5 A4 A3 A2 A1 A0
1 1 1 0 1 0 x x → E 8 – EB H 0 1 1
1 1 1 0 0 1 x x → E 4 – E7 H f1 = AC + BC
1 1
……………………………………………………..
0 0 0 1 0 1 x x → 14 – 17 H
 Choice (B)
0 0 0 1 1 0 x x → 18 – 1B H
In this way many ranges we will get 33. f2 is connected to OR gate, so sum of min terms
as per options 44 – 47H Choice (D) f2 = Σm(0, 2, 3, 4, 6, 7) = πM(1, 5)
 Digital Circuits Test 2 | 3.193

f2 BC Clk QA Q­­B QC TA TB TC
A 00 01 11 10
0 0 0 0 0 0 1
0 0 1 0 0 1 1 1 0
2 1 1 1 1 0 1
1 0
3 0 1 0 1 0 0
4 1 1 0 1 1 0
(
f2 = B + C ) 5 0 0 0

 Choice (C) So mod–5 counter, when it starts from reset state.

34. From the circuit diagram  Choice (B)
TA = C + B, TB = CB1 + C1 A, TC = CB + 35. If present state ABC = 100
C1 B1 = B ⊙ C then TA TB TC = 011 then next states ABC = 111.
 Choice (C)