Object Oriented Programming in SystemVerilog
Why OOP in SystemVerilog?
--------------------------
In modern verification environments (especially in UVM), we deal with complex testbenches (TBs)
where modeling behavior and state of digital components in a modular, reusable way is essential.
SystemVerilog's OOP capabilities make it ideal for this. It allows us to:
- Model data and behavior together (encapsulation)
- Reuse existing code (inheritance)
- Write flexible/testable components (polymorphism)
1. Encapsulation
-----------------
Encapsulation = Binding data (properties) + behavior (methods) + constraints into a class
Example:
class Device;
rand bit [3:0] voltage; // randomizable
bit [3:0] temperature; // non-random
function void display();
$display("Voltage = %d", voltage);
$display("Temperature = %d", temperature);
endfunction
endclass
2. Properties
--------------
These are variables declared inside a class using SystemVerilog data types like bit, int, byte, etc.
Example:
class Sensor;
bit [3:0] pressure;
bit [6:0] current;
endclass
3. Methods
-----------
Methods = Functions or Tasks that define behavior.
Types:
- function: No delay support
- task: Supports delays
Example Function:
class Test;
bit [3:0] a = 5;
function void print_a();
$display("a = %d", a);
endfunction
endclass
Example Task:
class Test2;
bit [3:0] b = 7;
task print_b();
#5 $display("After delay: b = %d", b);
endtask
endclass
4. Using Class in Module
-------------------------
To use a class in the testbench:
1. Handle Declaration
2. Object Creation
Example:
class mit;
bit [3:0] a, b;
function void final_year();
$display("a = %0d", a);
$display("b = %0d", b);
endfunction
endclass
module top;
mit m;
initial begin
m = new();
m.final_year(); // Output: a = 0, b = 0
end
endmodule
5. Randomization
-----------------
Use the rand keyword before property declaration. Call .randomize() using object handle.
Example:
class Packet;
rand bit [3:0] id;
bit [3:0] fixed_id;
endclass
module tb;
Packet p;
initial begin
p = new();
p.randomize();
$display("Random ID = %0d", p.id);
$display("Fixed ID = %0d", p.fixed_id);
end
endmodule
6. Constraints
---------------
You can restrict the range or relation of randomized values.
Example:
class Packet;
rand bit [3:0] id;
constraint id_c { id > 4 && id < 10; }
endclass
7. Procedural Blocks
---------------------
initial: Executes once (for TB)
always: Executes repeatedly (for design)
Examples:
initial begin
#5 $display("Welcome");
#10 $display("VLSI");
end
Parallel Execution:
initial fork
#5 $display("Message 1");
#10 $display("Message 2");
join
Summary Table
--------------
Concept | Description | Keyword
----------------|-------------------------------------|---------
Encapsulation | Group data & methods in class | class
Properties | Variables in class | bit, rand
Methods | Logic via functions/tasks | function, task
Randomization | Generate random values | randomize()
Constraints | Limit value ranges of properties | constraint
Handle/Object | Object creation with new() | handle = new();
Procedural Block| Execution block in Verilog | initial, always
Final Code Example
-------------------
class pkt;
rand bit [3:0] id;
bit [3:0] type;
function void show();
$display("ID = %0d", id);
$display("Type = %0d", type);
endfunction
constraint id_c { id < 8; }
endclass
module tb;
pkt p;
initial begin
p = new();
p.randomize();
p.show();
end
endmodule
