SystemVerilog-UNIT-2

Class and Randomization

Prof. Sowmya K B
ECE Deptartment
RVCE, Bengaluru

Prof.Sowmya K B 1
 SystemVerilog classes
Classes
• A class is a user defined data type that includes
data (class properties), functions and tasks that
operate on data. functions and tasks are called
methods, both are members of the class.

• classes allow objects to be dynamically created,

deleted, assigned, and accessed via object
handles.

Prof.Sowmya K B 2
 Class Declaration

class sv_class;

int x; //class properties

task set(int i); //method-1

x = i;
endtask

function int get(); //method-2

return x;
endfunction

endclass

Prof.Sowmya K B 3
 Class handle and Object Creation
• class is a data type, variable (class handles)
can be declared with the class type
sv_class class_1;
class handle

• class properties and methods can be accessed

only after creating the object.
class_1 = new();

• Both declaration of variable and object

creation.
sv_class class_1 = new();
Prof.Sowmya K B 4
Class handle and Object Creation

Prof.Sowmya K B 5
Accessing class properties and methods

Prof.Sowmya K B 6
• Simulator Output

class_1 :: Value of x = 10
class_1 :: Value of x = 20

Prof.Sowmya K B 7
 SystemVerilog Class Constructors

• Constructor can be used for initializing the

class properties.

• In case of any initialization required, those

can be placed in the constructor and It is also
possible to pass arguments to the constructor,
which allows run-time customization of an
object.

Prof.Sowmya K B 8
Class properties initialization by Constructor

Prof.Sowmya K B 9
class packet;
bit [31:0] addr;
bit [31:0] data; //class properties
bit write;
string pkt_type;
function new();
addr = 32'h10; //constructor
data = 32'hFF;
write = 1;
pkt_type = "GOOD_PKT";
endfunction

function void display(); // methods

$display("---------------------------------------------------------");
$display("\t addr = %0d",addr);
$display("\t data = %0h",data);
$display("\t write = %0d",write);
$display("\t pkt_type = %0s",pkt_type);
$display("---------------------------------------------------------");
endfunction
endclass Prof.Sowmya K B 10
module sv_constructor;
packet pkt;
initial begin
pkt = new();
pkt.display();
end
endmodule

Prof.Sowmya K B 11
• Simulator Output
addr = 16
data = ff
write = 1
pkt_type = GOOD_PKT

Prof.Sowmya K B 12
 SystemVerilog class this keyword

" this " keyword

The this keyword is used to refer to class
properties.

• If the properties of class and argument to the

constructor are having the same name, this will
lead to an ambiguity in assignment and values
will not be assigned properly.

Prof.Sowmya K B 13
class packet;
bit [31:0] addr; //class properties
string pkt_type;
function new(bit [31:0] addr, pkt_type); // class constructor
addr = addr;
pkt_type = pkt_type;
endfunction
function void display(); //methods
$display("\t addr = %0h",addr);
$display("\t pkt_type = %0s",pkt_type);
endfunction
endclass
module sv_constructor;
packet pkt;
initial begin
pkt = new(32'h10,"GOOD_PKT");
pkt.display();
end
Prof.Sowmya K B 14
endmodule
The above problem can be overcome by using
"this" keyword to the class properties.

Prof.Sowmya K B 15
class packet;
bit [31:0] addr; //class properties
string pkt_type;
function new(bit [31:0] addr, string pkt_type);
this.addr = addr;
this. pkt_type = pkt_type; //constructor
endfunction
function void display(); //methods
$display("\t addr = %0h",addr);
$display("\t pkt_type = %0s",pkt_type);
endfunction
endclass
module sv_constructor;
packet pkt;
initial begin
pkt = new(32'h10,"GOOD_PKT");
pkt.display();
end endmodule Prof.Sowmya K B 16
Simulator Output
addr = 10
pkt_type = GOOD_PKT

Prof.Sowmya K B 17
 SystemVerilog Class Assignment

Object will be created only after doing new to an

class handle,
packet pkt_1;
pkt_1 = new();
packet pkt_2;
pkt_2 = pkt_1;

Prof.Sowmya K B 18
 Class Assignment
Here object is created only for pkt_1, pkt_2 is just an handle to the packet. pkt_1 is
assigned to the pkt_2. so only one object has been created, pkt_1 and pkt_2 are two
handles both are pointing to the same object. As both the handles are pointing to the
same object any changes made with-respect to pkt_1 will reflect on pkt_2.

Prof.Sowmya K B 19
ShallowCopy

Prof.Sowmya K B 20
Limitations of Shallow Copy

Prof.Sowmya K B 21
 Deep Copy

Prof.Sowmya K B 22
endclass
 Ex: Shallow Copy
class A;
int i;
endclass
class B;
A a;
endclass
module main;
initial
begin
B b1;
B b2;
b1 = new();
b1.a = new();
b1.a.i = 123; OUTPUT:
b2 = new b1;
$display( b1.a.i );
$display( b2.a.i );
b1.a.i = 321;
$display( b1.a.i );
$display( b2.a.i );
end endmodule Prof.Sowmya K B 23
 Ex: Deep Copy
class A;
int i;
endclass
class B;
A a;
task copy(A a);
this.a = new a;
endtask
endclass
module main;
initial begin
B b1;
B b2;
b1 = new();
OUTPUT:
b1.a = new();
b1.a.i = 123;
b2 = new b1;
$display( b1.a.i );
$display( b2.a.i );
b2.copy(b1.a);
b1.a.i = 321;
$display( b1.a.i );
$display( b2.a.i );
end endmodule Prof.Sowmya K B 24
 Extending Classes – Inheritance
• One of the key features of object-oriented programming
is the ability to create new classes that are based on
existing classes.

• A derived(child) class by default inherits the properties

and methods of its parent or base class. However, the
derived class may add new properties and methods, or
modify the inherited properties and methods.

• In other words, the child class is a more specialised

version of the parent class.
Prof.Sowmya K B 25
In SystemVerilog the syntax for deriving or inheriting one class
from another is this:

class DerivedClass_name extends BaseClass_name;

// New and overridden property and method declarations.
endclass

Ex:
class ShiftRegister extends Register;
task shiftleft; data = data << 1; endtask
task shiftright; data = data >> 1; endtask
endclass
Prof.Sowmya K B 26
Example - 1 : parent class properties is accessed using child class
handle, i.e child class will have(inherit) parent class properties
and methods.
class parent_class;
bit [31:0] addr;
endclass

class child_class extends parent_class;

bit [31:0] data;
endclass

module inheritence1;
initial begin
child_class c = new();
c.addr = 10;
c.data = 20;
$display("Value of addr = %0d data = %0d",c.addr,c.data);
end
endmodule

Prof.Sowmya K B 27
• Simulator Output

Value of addr = 10 data = 20

Prof.Sowmya K B 28
 Overriding class properties
or Methods
Base class or parent class properties and methods can be overridden in the
child class or extended class.

class parent_class;
function display();
endclass

class child_class extends parent_class;

function display();
endclass

module inheritence;
child_class c=new();
c.display();
end
endmodule
Prof.Sowmya K B 29
Example - 1
parent class method display is overridden in the child class. calling c.display will call display of child class not the parent
class.

class parent_class;
bit [31:0] addr;
function display();
$display("Addr = %0d",addr);
endfunction
endclass

class child_class extends parent_class;

bit [31:0] data;
function display();
$display("Data = %0d",data);
endfunction
endclass

module inheritence;
initial begin
child_class c=new();
c.addr = 10;
c.data = 20;
c.display();
end
endmodule
Prof.Sowmya K B 30
 super keyword
The super keyword is used in a child class to refer to
members of the parent class.

It is necessary to use super to access members of a

parent class when those members are overridden by
the derived class.

In child class, method with the same name of parent

class will override the method. By using super
keyword parent class method can be accessed from
child class.
Prof.Sowmya K B 31
 Example - 1
parent class method display is overridden in the child class, by calling super.display()
from child class display method of parent class can be accessed.
class parent_class;
bit [31:0] addr;
function display();
$display("Addr = %0d",addr);
endfunction
endclass

class child_class extends parent_class;

bit [31:0] data;
function display();
super.display();
$display("Data = %0d",data);
endfunction
endclass

module inheritence;
initial begin
child_class c= new();
c.addr = 10;
c.data = 20;
c.display();
end
endmodule
Prof.Sowmya K B 32
class parent ;
int a,b;
function display();
$display(“a=%d,b=%d",a,b);
endfunction
endclass

class subclass extends parent;

function display();
$display("a=%d,b=%d",a,b);
endfunction
endclass

module inharit_overried; OUTPUT:

initial begin a= 0,b= 0
parent p = new();
subclass s = new();
s.display();
end
Prof.Sowmya K B 33
endmodule
class parent ;
int a,b;
function display();
$display(“a=%d,b=%d",a,b);
endfunction
endclass

class subclass extends parent;

function display();
super.display();
$display("a=%d,b=%d",a,b);
endfunction
endclass

module inharit_overried;
a= 0,b= 0
initial begin a= 0,b= 0
parent p = new();
subclass s = new();
s.display();
end
endmodule
Prof.Sowmya K B 34
class parent ;
int a,b;

function new();
this.a=1;
this.b=2;
endfunction

function display();
$display(“a=%d,b=%d",a,b);
endfunction
endclass
OUTPUT:
class subclass extends parent; a= 1,b= 2
function display(); a= 1,b= 2
super.display();
$display("a=%d,b=%d",a,b);
endfunction Prof.Sowmya K B 35
class parent ;
int a,b; Chaining new()
function new();
this.a=1;
constructors
this.b=2;
endfunction
function display();
$display("x=%d,y=%d",a,b);
endfunction
endclass

class subclass extends parent;

function new();
super.new();
super.a=4;
super.b=5;
endfunction OUTPUT:
function display(); x= 4,y= 5
super.display(); a= 4,b= 5
$display("a=%d,b=%d",a,b);
endfunction
endclass Prof.Sowmya K B 36
Ex2:
class A ;
integer j;
function new();
begin
j = 10;
end
endfunction
task print();
begin
$display("j is %0d",j);
end
endtask
endclass
Prof.Sowmya K B 37
class B extends A;
integer i = 1;
function new();
begin
// call the parent new
super.new(); // constructor chaining
$display("Done calling the parent new");
i = 100;
end
endfunction
// Override the parent class print
task print();
begin
$display("i is %0d",i);
$display("Call the parent print");
super.print();
end
endtask
endclass

module class_super;
initial begin
B b1;
b1 = new;
b1.print();
end
endmodule Prof.Sowmya K B 38
• Simulator Output
Done calling the parent new
i is 100
Call the parent print
j is 10

Prof.Sowmya K B 39
 Encapsulation in system verilog :
local and protected keywords
• In systemverilog all the properties of the class are
public by default or we can say it be accessed outside
the class directly using the dot operator.

• If we want to protect the access of the class

variables/properties from outside the class we can use
the local keyword. Hiding the properties from being
accessed outside the class is called encapsulation.

• If we want to make the properties accessible in the

child classes but not outside the classes. We can declare
the properties as protected. Then it will be available in
the child classes but not in the main module.
Prof.Sowmya K B 40
 Ex1:
Protecting the access of the class variables/properties from
outside the class
class parent_class;
local bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass
module encapsulation;
initial begin
parent_class pc = new();
pc.tmp_addr = 20; //Accessing local variable outside the class
pc.display();
end
endmodule
Prof.Sowmya K B 41
• Simulator Output
Error
Local member 'tmp_addr' of class 'parent_class' is not
visible to scope 'encapsulation'.

Prof.Sowmya K B 42
 Accessing local variable within the
class ( Allowed )
class parent_class;
local bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass
Simulator Output
module encapsulation;
initial begin Addr = 15
parent_class pc = new(5);
pc.display();
end
endmodule Prof.Sowmya K B 43
Example-1: Accessing protected variable outside the class ( Not allowed )
class parent_class;
protected bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass

class child_class extends parent_class;

function new(bit [31:0] r_addr);
super.new(r_addr);
endfunction
function void incr_addr();
tmp_addr++;
endfunction
endclass
Prof.Sowmya K B 44
module encapsulation;
initial begin
parent_class p_c = new(5);
child_class c_c = new(10);
// variable declared as protected cannot be accessed outside the
//class
p_c.tmp_addr = 10;
p_c.display();
c_c.incr_addr(); //Accessing protected variable in extended class
c_c.display();
end endmodule

Prof.Sowmya K B 45
• Simulator Output
Error
Protected member 'tmp_addr' of class 'parent_class'
is not visible to scope 'encapsulation'.

Prof.Sowmya K B 46
Example-2: Accessing protected variable in the extended class ( allowed )

class parent_class;
protected bit [31:0] tmp_addr;
function new(bit [31:0] r_addr);
tmp_addr = r_addr + 10;
endfunction
function display();
$display("tmp_addr = %0d",tmp_addr);
endfunction
endclass

class child_class extends parent_class;

function new(bit [31:0] r_addr);
super.new(r_addr);
endfunction
function void incr_addr();
tmp_addr++;
endfunction
endclass
Prof.Sowmya K B 47
module encapsulation;
initial begin
child_class c_c = new(10);
c_c.incr_addr(); //Accessing protected variable in extended class
c_c.display();
end
endmodule

Prof.Sowmya K B 48
Simulator Output
tmp_addr = 21

Prof.Sowmya K B 49
 Constrained Randomization
• Random Variables - rand and randc,

• Randomize( ) Method - Pre/Post Randomize( )

methods

Prof.Sowmya K B 50
 Constrained Randomization
• Complex designs pose more difficulty as they need a complex set of
stimuli needed to check their complete functionality

• Directed test-cases may be written to check a certain set of features,

but, enough directed test-cases cannot be written when the number
of features keeps doubling

• The solution is to create test-cases automatically using constrained-

random tests (CRT). (the test scenarios may be restricted to those
that are both valid and of interest by using constraints).

• A CRT finds bugs even from corner cases (un-predictable), by using

random stimulus. (A directed test finds the bugs that are predictable)

• A CRT is made of 2- parts: the test code that uses a stream of

random values to create input to the DUT, and a seed to the pseudo-
random number generator (PRNG)
Prof.Sowmya K B 51
 Directed Vs Random testing
Directed Random

•Detect the expected bugs •Detects unexpected bugs

(corner cases)

•Time consuming •Tremendously reduce the

efforts

•Enough directed test-cases •Random variables are best

cannot be written when the packaged in a class, since they
design complex is more can be grouped along with their
constraints and reused
So, Shift from directed to
randomized test cases.
Prof.Sowmya K B 52
 Random Variables
Class variables can be declared random using the rand and randc(constrained) type-modifier
keywords.

Following types can be declared as rand and randc,

• singular variables of any integral type
• arrays
• arrays size
• object handle's

Variables declared with the rand keyword are standard random variables. Their values are
uniformly distributed over their range.
rand bit [3:0] addr;
addr is a 4-bit unsigned integer with a range of 0 to 15. on randomization this variable shall be
assigned any value in the range 0 to 15 with equal probability.

Variables declared with the randc keyword, their values doesn't repeat a random value until every
possible value has been assigned.
randc bit wr_rd;

In order to randomize the object variables, need to call randomize() method.

object.randomize();
Prof.Sowmya K B 53
 Random Variables:Example-1
2-variables addr1 and addr2 of same bit type is declared as rand and randc

class packet;
rand bit [2:0] addr1;
randc bit [2:0] addr2;
endclass

module rand_methods;
initial begin
packet pkt;
pkt = new();
repeat(10)
begin
pkt.randomize();
$display("\taddr1 = %0d \t addr2 = 0d", pkt.addr1, pkt.addr2);
end
end
endmodule
Prof.Sowmya K B 54
Prof.Sowmya K B 55
 Enabling and disabling the random
variables
•The rand_mode() method can be used to enable or disable the
randomization of variable declared with rand/randc.

•The syntax for the rand_mode() method is:

addr.rand_mode(0); //disable randomization of addr

packet.addr.rand_mode(0);

•By default rand_mode value for all the random variables will
be 1.

•After setting rand_mode(0) to any random variable, it will get

randomized only after rand_mode(1).
Prof.Sowmya K B 56
module top;
initial
begin
int result;
box b1;
b1 = new();
result = b1.bt.rand_mode();
result = b1.et.rand_mode();
b1.rand_mode(0);
result = b1.bt.rand_mode();
result = b1.et.rand_mode();
b1.bt.rand_mode(1);
result = b1.bt.rand_mode();
result = b1.et.rand_mode();
end
endmodule

Prof.Sowmya K B 57
module top;
initial
begin
int result;
box b1;
b1 = new();
result = b1.bt.rand_mode(); // result = 1;
result = b1.et.rand_mode(); // result = 1;
b1.rand_mode(0); // turns off all random variables in b1
result = b1.bt.rand_mode(); // result = 0;
result = b1.et.rand_mode(); // result = 0;
b1.bt.rand_mode(1); // turns on valid area constraint in b1
result = b1.bt.rand_mode(); // result = 1;
result = b1.et.rand_mode(); // result = 0;
end
endmodule

Prof.Sowmya K B 58
 SystemVerilog Randomization
The randomize() methods: Methods
•Every class contains built-in pre_randomize() and post_randomize() functions.

•Upon calling randomize(), pre_randomize() and post_randomize() functions will

get called before and after the randomize call respectively.

•Users can override the pre_randomize() and post_randomize() in any classes.

•pre_randomize → function used to set pre-conditions before the object

randomization.

Ex: user can disable the randomization of particular variables based on test
conditions.

•post_randomize → function used to check/perform conditions after the object

randomization.

Ex: user can override the randomized values or can print the randomized
variables.
Prof.Sowmya K B 59
 Example 1:
• 2-variables addr and wr_rd
• addr is adress of location
• wr_rd =1 write operation and wr_rd= 0 read operation
• In order to perform write followed by read to the same addr,
randomization of addr is controlled based on the previous
randomization value of wr_rd.

class packet;
rand bit [7:0] addr;
randc bit wr_rd;
bit tmp_wr_rd;

//pre-randomization function - disabling randomization of addr, if the

previous operation is write.

function void pre_randomize();

if(tmp_wr_rd==1)
addr. rand_mode(0);
else
addr.rand_mode(1); Prof.Sowmya K B 60
endfunction
//post-randomization function - store the wr_rd value to //tmp_wr_rd and
display randomized values of addr and wr_rd

function void post_randomize();

tmp_wr_rd = wr_rd;
$display("POST_RANDOMIZATION:: Addr = %0h,
wr_rd = %0h", addr, wr_rd);
endfunction
endclass

module rand_methods;
initial begin
packet pkt=new();
repeat(4)
pkt.randmize();
end
endmodule

Prof.Sowmya K B 61
Prof.Sowmya K B 62
 Random weighted case
If we want to Randomly pick one out of the many
statements. Then
• The keyword randcase introduces a case statement that
randomly selects one of its branches.

• The case item expressions are positive integer values that

represent the weights associated with each item.

• Probability of selecting an item is derived by the division

of that item’s weight by the sum of all weights

Prof.Sowmya K B 63
Syntax

randcase
item : statement;
...
endcase

Prof.Sowmya K B 64
 Example 1:
module ss;
initial begin
for (int i = 0; i < 10; i++)
randcase
1 : $display ("Wt 1");
5 : $display ("Wt 5");
3 : $display ("Wt 3");
endcase
end
endmodule

Prof.Sowmya K B 65
Output:
Wt 5
Wt 5
Wt 3
Wt 5
Wt 1
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5

Note: 5 appeared max time, 1 appeared least time and 3 appeared in moderate
Prof.Sowmya K B 66
 Example 2:
module tb;
initial begin
for (int i = 0; i < 10; i++)
randcase
0 : $display ("Wt 1");
5 : $display ("Wt 5");
3 : $display ("Wt 3");
endcase
end
endmodule

Prof.Sowmya K B 67
Output:
Wt 5
Wt 5
Wt 3
Wt 5
Wt 5
Wt 3
Wt 5
Wt 3
Wt 3
Wt 5
Prof.Sowmya K B 68
module m1;
task t1();
Example 3:
begin
randcase
20 : begin
$write ("What should I do ? \n");
end
20 : begin
$write ("Should I work\n");
end
20 : begin
$write ("Should I watch Movie\n");
end
40 : begin
$write ("Should I complete selfstudy\n");
end
endcase
end
endtask

initial
begin
repeat(10)
begin
t1();
end
$finish;
end Prof.Sowmya K B 69
endmodule
Output:
What should I do ?
Should I complete selfstudy
Should I watch Movie
What should I do ?
Should I complete selfstudy
Should I watch Movie
Should I complete selfstudy
Should I complete selfstudy
Should I work
Should I watch Movie

Prof.Sowmya K B 70
 RANDSEQUENCE
The random sequence generator is useful for
randomly generating sequences of stimulus.

Prof.Sowmya K B 71
 Example 1:
module m1();
initial
begin
repeat(5)
begin
randsequence( main1 )
main1 : two one three ;
one : {$write(" thing");};
two : {$write(" any");};
three: {$display(" read");};
endsequence
end
end
endmodule
Prof.Sowmya K B 72
Output:
any thing read
any thing read
any thing read
any thing read
any thing read

Prof.Sowmya K B 73
 SystemVerilog Fork Join

fork-Join will start all the processes inside it parallel'y and wait for the
completion of all the processes.
Prof.Sowmya K B 74
 SystemVerilog Fork Join

fork-Join will start all the processes inside it parallel'y and wait for the
completion of all the processes.
Prof.Sowmya K B 75
module fork_join;
initial begin
Example 1:
$display("-----------------------------------------------------------------");
fork
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join
$display($time,"\tOutside Fork-Join");
$display("-----------------------------------------------------------------");
$finish;
end
endmodule Prof.Sowmya K B 76
Output:
--------------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
20 Process-2 Finished
20 Outside Fork-Join
---------------------------------------------------------------

Prof.Sowmya K B 77
 SystemVerilog fork join_any

Fork-Join_any will be un-blocked after the completion of any of the

Process. Prof.Sowmya K B 78
 SystemVerilog fork join_any

Fork-Join_any will be un-blocked after the completion of any of the

Process. Prof.Sowmya K B 79
module fork_join;
Example 1:
initial begin
$display("-----------------------------------------");
fork
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end

begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join_any

$display($time,"\tOutside Fork-Join");
$display("-----------------------------------------------------------------");
end
endmodule
Prof.Sowmya K B 80
Output:

--------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
5 Outside Fork-Join
----------------------------------------------------------------
20 Process-2 Finished

Prof.Sowmya K B 81
 SystemVerilog fork join_none

Processes inside the fork-join_none block will be started at the same time,
fork block will not wait for the completion of Process inside the fork-
join_none.
Prof.Sowmya K B 82
 Example 1:
module fork_join_none;
initial begin
$display("-----------------------------------------------------------------");
fork
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
begin
$display($time,"\tProcess-2 Startedt");
#20;
$display($time,"\tProcess-2 Finished");
end
join_none
$display($time,"\tOutside Fork-Join_none");
$display("-----------------------------------------------------------------");
end Prof.Sowmya K B 83
Output:

----------------------------------------------------------------
0 Outside Fork-Join_none
-----------------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
20 Process-2 Finished

Prof.Sowmya K B 84
 wait fork
wait fork; causes process to block until the
completion of all processes started from fork
blocks.

Prof.Sowmya K B 85
module no_wait_fork;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join_any
$display("-----------------------------------------------------------------");
$finish; //ends the simulation
end
endmodule
Prof.Sowmya K B 86
Simulator output:
-----------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
-----------------------------------------------------------

Prof.Sowmya K B 87
In the below example, wait fork will wait for the completion of
second thread in the fork-join_any.
module no_wait_fork;
initial begin
$display("-----------------------------------------------------------------");
fork
//Process-1
begin
$display($time,"\tProcess-1 Started");
#5;
$display($time,"\tProcess-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 Started");
#20;
$display($time,"\tProcess-2 Finished");
end
join_any
wait fork; //waiting for the completion of active fork threads
$display("-----------------------------------------------------------------");
$finish; //ends the simulation Prof.Sowmya K B 88
Simulator output:
-----------------------------------------------------------------
0 Process-1 Started
0 Process-2 Started
5 Process-1 Finished
20 Process-2 Finished
-----------------------------------------------------------------

Prof.Sowmya K B 89
 disable fork
• disable fork; causes process to kill/terminate
all the active processes started from fork
blocks.

Prof.Sowmya K B 90
 Example: disable fork
module disable_fork;
initial begin
$display("-----------------------------------------------------------------");
//fork-1
fork
//Process-1
begin
$display($time,"\tProcess-1 of fork-1 Started");
#5; $display($time,"\tProcess-1 of fork-1 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 of fork-1 Started");
#20; $display($time,"\tProcess-2 of fork-1 Finished");
end
join_any
Prof.Sowmya K B 91
//fork-2
fork
//Process-1
begin
$display($time,"\tProcess-1 of fork-2 Started");
#5;$display($time,"\tProcess-1 of fork-2 Finished");
end
//Process-2
begin
$display($time,"\tProcess-2 of fork-2 Started");
#20; $display($time,"\tProcess-2 of fork-2 Finished");
end
join_none
disable fork;
$display("-----------------------------------------------------------------");
$display($time,"\tAfter disable-fork");
$display("-----------------------------------------------------------------");
Prof.Sowmya K B 92
end endmodule
Simulator output:
-----------------------------------------------------------------
0 Process-1 of fork-1 Started
0 Process-2 of fork-1 Started
5 Process-1 of fork-1 Finished
-----------------------------------------------------------------
5 After disable-fork
-----------------------------------------------------------------

Prof.Sowmya K B 93