SystemVerilog

Professor: Sci.D., Professor

Vazgen Melikyan

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
1
Classification of HDLs

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
2
Design Levels
Example of Mathematical
Level Modeling Object HDL
Modeling Object Apparatus

SystemVerilog,
System Structural Circuit RAM bus CPU Queuing theory
SystemC

Add
Accumulator
Functional
Register- Circuits on the Input
Transfer level of multibit Command Register
devices +1
Command Counter
Boolean Algebra Verilog,VHDL

Circuit on the
Gate level of gates and J
flip-flops
K

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
3
Design Levels (2)
Example of Mathematical
Level Modeling Object HDL
Modeling Object Apparatus

System of
Circuit Electrical Circuit differential Spice
equations

n+
System of
p+ differential
Device IC Components n equations with
n+ partial
p derivative

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
4
Overview of Synthesis

 Translation
 The process which converts an abstract form of
desired circuit behavior into a design implementation
in terms of logic gates
 Optimization
 Changing design to achieve design goal (required by
specification)

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
5
 What is Synthesis?
residue = 16’h0000;
Design RTL description if (high_bits == 2’b10)
residue = state_table[index];
Technology Specific else
Circuit is obtained state_table[index] = 16’h0000;
from independent one Translation
by replacing all
components by real
blocks (standard Technology Independent
cells). This
Circuit
replacement process
is also called
mapping. Technology
Compilation
Independent Circuit is
4x and Optimization
logic circuit which fully
3x
implements function
2x 8x described but is built
Technology Specific from Generic Boolean
1x 2x Circuit Gates.

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
6
Standard Cell List Example

Type&Drive
No Cell name Cell Description
Strength
Inverters. Buffers
SAED14_INV_* Inverter 0.5, 0.75, 1, 10,
1. 12, 16, 1.5, 2, 20,
3, 4, 6, 8
2. SAED14_INV_ECO_* Inverter 1, 2, 3, 4, 6, 8
3. SAED14_DEL_R2V3_* Delay buffer 1, 2
4. SAED14_DEL_L4D100_* Delay buffer 1, 2
5. SAED14_CLKSPLT_* Clock Splitter 1, 8

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
7
Standard Cell List Example (2)
No Cell name Cell Description Type&Drive Strength

Logic Gates
2-Input AND (A
inverted input),
7. SAED14_AN2B_MM_* 1, 12, 16, 2, 20, 4, 6, 8
symmetric
rise/fall
8. SAED14_AN2_* 2-Input AND 0.5, 0.75, 1, 2, 4, 8

9. SAED14_AN2_ECO_* 2-Input AND 2

SAED14_AN2_MM_* 2-Input AND, 0.5, 1, 12, 16, 2, 20, 3,
10.
symmetric rise/fall 4, 6, 8
11. SAED14_AN3_* 3-Input AND 0.5, 0.75, 1, 2, 4, 8

12. SAED14_AN3_ECO_* 3-Input AND 1

13. SAED14_AN4_* 4-Input AND 0.5, 0.75, 1, 2, 4, 8

14. SAED14_AN4_ECO_* 4-Input AND 2

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
8
Standard Cell List Example (3)
Cell
No Cell name Type&Drive Strength
Description
Complex Logic Gates
SAED14_NR2B_* 2-Input NOR (A
15. 0.75, 1, 1.5, 2, 4
inverted input)
SAED14_NR2B_U_* 2-Input NOR (A
16. 0.5
inverted input)
SAED14_NR2_* 2-Input NOR 0.5, 1, 16, 1.5, 2, 3, 4, 5, 6,
17.
8
18. SAED14_NR2_ECO_* 2-Input NOR
1, 2
SAED14_NR2_MM_* Symmetric
0.5, 1, 10, 12, 16, 2, 3, 4, 6,
19. rise/fall time 2-
8
input NOR
SAED14_NR3B_* 3-Input NOR (A
20. 0.75, 1, 1.5, 2, 4
inverted input)
SAED14_NR3B_U_* 3-Input NOR (A
21. 0.5
inverted input)
22. SAED14_NR3_* 3-Input NOR
0.5, 0.75, 1, 2, 3, 4, 8
SAED14_NR2B_* 2-Input NOR (A
23. 0.75, 1, 1.5, 2, 4
inverted input)
Synopsys University Courseware
Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
9
Coding Styles and Synthesis
Poor coding style

+ + MUX MUX MUX

MUX +

Total area 11 Total area 7

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
10
Coding Styles and Synthesis

 A Verilog coding style can be:

 Supported by synthesis
 Unsupported by synthesis

 Ignored by synthesis

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
11
Example, Always, Assign
always @(A, B, S) 0
if (S)
D_Out = B;
else 1
D_Out = A;

assign D_Out=S?B:A;

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
12
Example, If syntax
always @(A, B, S)
if (S)
D_Out = B;
else
D_Out = A;

always @(A, B, S)
if (S==1)
D_Out = B;
else
D_Out = A;

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
13
Example, initial block, delay
initial

begin
#5 a<=1’b1;
#10 b<=1’b0;
#30 $finish;

end

#5 assign D_Out=S?B:A;

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
14
 Combinational circuits modeling
Combinational circuit
•The output of combinational circuit depends only on input terminals.
•The combinational circuit do not use any memory.
• A combinational circuit can have an n number of inputs and m
number of outputs.
Block diagram

A A’
B B’
C Combinational C’
circuit
n m

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
15
Example, Half Adder

Half Adder Inputs Output

A B S C
0 0 0 0
Block Diagram
0 1 1 0
A S
B 1 0 1 0
1 1 0 1

C Truth table

Circuit Diagram

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
16
 Example, Full Adder Truth table
Inputs Output
A B Cin S C0
Full Adder
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
Block Diagram
0 1 1 0 1
Cin A S 1 0 0 1 0
B 1 0 1 0 1
AB 1 1 0 0 1
1 1 1 1 1
ACin C0= AB+ACin +BCin

BCin

Circuit Diagram
Synopsys University Courseware
Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
17
Example, Mux 1

2:1 0
MUX

Block Diagram 2
Block Diagram 1 Enable Select Output
E S Y
B 0 X 0
S
D_Out 1 0 D0
1 1 D1
A
X=Don’t care
Truth table
Circuit Diagram
Synopsys University Courseware
Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
18
Example, Demux

Enable Select Output

1:2 E S Y0 Y1
DEMUX
0 x 0 0
1 0 0 Din
1 1 Din 0
Block Diagram
Truth table

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
19
Example, Decoder
Inputs Output

2 to line A B D0 D1 D2 D3
decoder 0 0 1 0 0 0
0 1 0 1 0 0
A B
Block Diagram 0 1 0 0 1 0
1 1 0 0 0 1
D0=A!B!
Truth table
D1=AB!

D2=A!B

D3=AB

Circuit Diagram
Synopsys University Courseware
Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
20
Continuous Assignment

module half_adder(
input x, y, enable,
output carry, result);

assign carry=x&y:0;
assign result=x^y:0;

endmodule half_adder;

x
Half carry
y
Adder result

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
21
Continuous Assignment (2)

module half_adder(
input x, y, enable,
output carry, result);

assign carry=enable?x&y:0;
assign result=enable?x^y:0;

endmodule half_adder;

x
Half carry
y
Adder result
enable

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
22
Continuous Assignment (3)

module half_adder(
input x, y, enable,
output carry, result);

reg carry, result; // ERRROR

assign carry<=enable?x&y:0; //ERROR
assign result<=enable?x^y:0; //ERROR

endmodule half_adder;

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
23
Always block
 always - Verilog/SystemVerilog
 always_comb - SystemVerilog
 always_latch - SystemVerilog
 always_ff - SystemVerilog

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
24
always block
module always_block(
input A,B,S,
output reg Out
);
0
always @(A, B, S)
if (S) 1
Out <= B;
else
Out <= A;

endmodule

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
25
always block
No difference in terms of synthsis

module always_block( module always_block(

input a,b,s, input a,b,s,
output reg out output reg out
); );

always @(a, b, s) always @(a, b)

if (s) if (s)
out <= b; out <= b;
else else
out <= A; out <= a;

endmodule endmodule

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
26
Blocking and non blocking
assignment
always @(a,b)
begin
temp = (a & b) | c;
out = temp;
end

always @(a,b,temp)
begin
temp <= (a & b) | c;
out <= temp;
end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
27
Example
reg out;

always @(A,B)
Blocking
begin
Out = A & B;
Out = A | B;
end

reg out;

Non-blocking always @(A,B)

begin
Out <= A & B;
Out <= A | B;
end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
28
Always_comb
module always_block( module always_comb_block(
input A,B,S, input A,B,S,
output reg Out output logic Out
); );

always @* Always_comb
if (S) if (S)
Out <= B; Out <= B;
else else
Out <= A; Out <= A;

endmodule endmodule

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
29
 if Statement
always @(a, b, s)
if (s)
out <= b;
else
out <= a;

B
0 S

1 Out

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
30
If statement(2)

Specification always_comb

if (s==2’b00)
Mux out = a1;
Inputs – 4 else if (s==2’b01)
Output – 1 out = a2;
Select – 2 or 1 input 2 bit else if (s==2’b10)
out = a3;
else
out = a4;
end

end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
31
Iff qualifier
module latch (input [31:0] d,
input enable,
output logic [31:0] q);

always @(d iff enable == 1)

y <= q;
endmodule

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
32
 Case statement
Specification always @*
begin
Mux
Inputs – 4 case (s)
Output – 1 2’b00 : out = a1;
Select – 2 or 1 input 2 bit 2’b01 : out = a2;
2’b10 : out = a3;
default : out = a4;
endcase

end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
33
 Case statement (2)
Specification always @*
begin
Mux
Inputs – 4 case (s)
Output – 1 2’b01 : out = a1;
Select – 2 or 1 input 2 bit 2’b01 : out = a2;
2’b10 : out = a3;
default : out = a4;
endcase

end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
34
 Case statement, missed 2 combination
Specification always @*
begin
Mux
Inputs – 4 case (s)
Output – 1 2’b01 : out = a1;
Select – 2 or 1 input 2 bit 2’b10 : out = a2;

endcase

end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
35
Parallel case statement

always @*
begin
Multiplexer will be
synthesized case (s)
2’b00 : out = a1;
2’b01 : out = a2;
2’b10 : out = a1;
2’b11 : out = a2;
endcase

end

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
36
 For-loop
module(input [1:0] in,
output reg [3:0] out); module(input [1:0] in,
integer i; output reg [3:0] out);

always @(in)
always @(in)
for (i = 0; i <= 3; i = i + 1)
if (in == i) out=0;
out[i] = 1'b1; out[in]=1’b1;
else
out[i] = 1'b0; enmodule
enmodule

2 to 4 line
decoder

Synopsys University Courseware

Copyright © 2020 Synopsys, Inc. All rights reserved.
SystemVerilog
Lecture - 1
Developed By: Vazgen Melikyan
37