[go: up one dir, main page]
Scribd
Upload
86 views27 pages

To Verilog: Digital Design

Verilog is a hardware description language used to design digital circuits. It allows modeling at different levels of abstraction - gate level using primitive gates, data flow using continuous assignments, and behavioral level using procedural assignments. The basic unit of design in Verilog is called a module, which defines ports and contains concurrent or sequential statements. A test bench is used to simulate and verify the design behavior.

Uploaded by

bits_who_am_i
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
86 views27 pages

To Verilog: Digital Design

Verilog is a hardware description language used to design digital circuits. It allows modeling at different levels of abstraction - gate level using primitive gates, data flow using continuous assignments, and behavioral level using procedural assignments. The basic unit of design in Verilog is called a module, which defines ports and contains concurrent or sequential statements. A test bench is used to simulate and verify the design behavior.

Uploaded by

bits_who_am_i
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PPTX, PDF, TXT or read online on Scribd
You are on page 1/ 27

Introduction

to
Verilog
Digital Design

About Verilog
Verilog is a HDL (Hardware Description Language) to design
the digital system
VHDL is other hardware description language
Virtually every chip (FPGA, ASIC, etc.) is designed in part
using one of these two languages
Verilog was introduced in 1985 by Gateway Design System
Corporation

Concept of Verilog Module


In Verilog, the basic unit of hardware is called a module.
module module_name (list_of_ports);
input/output declarations;
local net declarations;
parallel statements;
endmodule

Example 1 :: simple AND gate


module simpleand (f, x, y);
input x, y;
output f;
assign f = x & y;
endmodule

Example 2 :: two-level circuit


module two_level (a, b, c, d, f);
input a, b, c, d;
output f;
wire t1, t2;
assign t1 = a & b;
assign t2 = (c | d);
assign f = t1 ^ t2;
endmodule

Variable Data Types


A variable belongs to one of two data types:
Net
Must be continuously driven
Used to model connections between continuous assignments &
instantiations
Register
Retains the last value assigned to it
Often used to represent storage elements

Net data type


Different net types supported for synthesis:
wire, supply0, supply1
supply0 / supply1 model power supply connections.

Register data type


Different register types supported for synthesis:
reg, integer
The reg declaration explicitly specifies the size.
reg x, y; // single-bit register variables
reg [15:0] bus; // 16-bit bus, bus[15] MSB
For integer, it takes the default size, usually 32-bits

Other differences:
In arithmetic expressions,
An integer is treated as a signed quantity.
A reg is treated as an unsigned quantity.
General rule of thumb
reg used to model actual hardware registers
such as counters, accumulator, etc.
integer used for situations like loop counting.

Specifying Constant Values


A value may be specified in either the sized or the unsized form.
Syntax for sized form:

<size> <base> <number>

Examples:
8b01110011 // 8-bit binary number
12hA2D
// 12-bit hexadecimal number
1b0
// Logic 0
1b1
// Logic 1

Primitive Gates
Primitive logic gates (instantiations):
and

G (out, in1, in2);

nand G (out, in1, in2);


or

G (out, in1, in2);

nor

G (out, in1, in2);

xor

G (out, in1, in2);

xnor G (out, in1, in2);


not

G (out1, in);

buf

G (out1, in);

Verilog Operators
Arithmetic operators
*, /, +, -, %
Logical operators
!
logical negation
&&
logical AND
| | logical OR
Relational operators
>, <, >=, <=, ==, !=
Bitwise operators
~, &, |, ^, ~^

Shift operators
>>, <<
Conditional
<condition> ? <expression1> : <expression2>

Description Styles in Verilog


Three different styles of description:
1.Gate Level
Gate Level assignment
2.Data flow
Continuous assignment
3.Behavioral
Procedural assignment

Gate Level Modeling


Logic gates can be used to design logic circuits
Basic Logic gates defined by Verilog Primitives
Not, And, Or, Xor, Xnor, Buf
Examples

module generate_sum (a, b, c);


input a, b;
output c;
xor (c, a, b);
endmodule

Data-flow Modeling
Identified by the keyword assign.
assign

a = b & c;

assign

f[2] = c[0];

The assignment is continuously active.


Almost exclusively used to model combinational logic.

module generate_sum (a, b, c);


input a, b;
output c;
assign
endmodule

c = a+b;

Behavioral Modeling
The procedural block defines
A region of code containing sequential statements.
Two types of procedural blocks in Verilog
The always block
A continuous loop that never terminates.
The initial block
Executed once at the beginning of simulation (used in
Test-benches).

Only reg type variables can be assigned within an always


block.

Verilog Test Bench


What is test bench?

A Verilog procedural block which executes only once.


Used for simulation.
Test bench generates clock, reset, and the required test
vectors

Examples
Majority Detector
Parity Checker
2 Input Multiplier

Majority Detector
Design Digital System to detect a majority vote
4 inputs
Detect majority vote if more than two inputs are pressed
Inputs : S1, S2, S3, S4
Function : S4S3(S2+S1) + S2S1(S3+S4)

Majority Detector Gate Level


Modeling
module majority_gate (S1,S2,S3,S4,Y);
input S1,S2,S3,S4;
output Y;
wire t1,t2,t3,t4,t5,t6;
and (t1,S1,S2);
or (t2,S3,S4);
and (t3,t1,t2);
and (t4,S3,S4);
or (t5,S1,S2);
and (t6,t4,t5);
or (Y,t3,t6);
endmodule

Majority Detector Data Flow Modeling


module majority_data(S1,S2,S3,S4,Y);
input S1,S2,S3,S4;
output Y;
assign Y = ((S1&S2)&(S3|S4)) | ((S3&S4)&(S1|S2));
endmodule

Majority Detector Behavioral


Modeling
module majority_behav(S1,S2,S3,S4,Y);
input S1,S2,S3,S4;
output Y;
reg Y;
always @(S1 or S2 or S3 or S4)
case ({S1,S2,S3,S4})
4'b0111: Y = 1;
4'b1011: Y = 1;
4'b1101: Y = 1;
4'b1110: Y = 1;
4'b1111: Y = 1;
default : Y = 0;
endcase
endmodule;

Test Bench
module stimulus;
reg s1,s2,s3,s4;
wire y;
majority_data m1(s1,s2,s3,s4,y);
initial
begin
s1 = 1'b0;
s2 = 1'b0;
s3 = 1'b0;
s4 = 1'b0;
#5 s1 = 1'b1;
#50 s2 = 1'b1;
#100 s3 = 1'b1;
#150 s4 = 1'b1;
#150 s4 = 1'b1;
end
endmodule

You might also like