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Verilog Test Bench
How to Write a Basic Verilog Testbench
Syntax of Verilog Test Bench & explanation
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VERILOG TEST BENCH
HA adder code with delay
module half_adder(
input a,b,
output sum, carry };
assign 0 sum =a 4b;
assign #10 carry =a & b;
endmodule
‘TEST BENCH EXAMPLE
module tb_half_adder;
/[1. Define inputs and outputs
rega,b; —// inputs using reg
wire sum, carry; // outputs using wire
1/2. \nstantiate or call the half adder module & map variables
half_adder wut (.a(a), .0(b), sum(sum), carry(carry) );
1/3. Allinput combinations
initial
begin
a=0;b=0; #10;
a=0;b=1; #10;
a= 1;b=0; #0;
a=1;b=1;#10;
Stinish; // End simulation
end
1/4.%o display values
initial
begin
$monitor(" 2 = %6b,b =%b, sum = %b, carry =%b", a,b, sum, carry);
end
endmodule
Explanation for Test Bench
Testbench :
Itis program used to tet the functionality of the main module or main program. It provides all posible input combinations to
check whether the main program works correctly.
Test bench is created using keyword module with the name tb_half_adder;
Here name of the test bench is tb_half_adder;
1. Define Inputs and Outputs:
* Inputs are defined using reg keyw
© rega,b;
ts
e keyword
2. Insatiate oF Call the Half Adder Modu:
+ The ha: module is instantiated (called) and given local name wut
+ Inpatsioutputs ofthe main program (half adder) are connected or mapped tothe testbench variables.
adde
Prof. Sujay Gejji ECE, SGBIT Belagavi VERILOG TEST BENCH
3. Generate Input Combinations:
‘© All possible input combinations are mentioned within the initial block
a=0;b=1; #10;
‘© Here 10 time units delayed is mentioned
4, Display Results:
‘+ Smonitor command is used to continuously print or display the values of variables 2, b, sum, and
carry whenever they change.
‘+ Alternatively, we can use Sdisplay to print or displ:
Sdisplay (" a = %eb, b = %kb, sum =%b, carry = %6b", a,b, sum, carry);
Sdisplay command displays or prints the values only once, but monitor displays values continuously
‘whenever they change.
© End the Simulation:
‘The $finish commend is used to stop the simulation afterall input combinations are tested,
Prof. Sujay Gejji ECE, SGBIT Belagavi
