Descriptive Hardware

Language: Verilog
Submitted by:
Group 2 | Group 5 | Group 8 | Group 9

Submitted to:
Prof. Marvin de Pedro
Verilog Introduction
Group 8
Members:
Sergio Flores
Kaye Gose
Patrick Tolentino
 What is Verilog?

Verilog is a Hardware Description Language; a textual format for describing electronic circuits and
systems. Applied to electronic design, Verilog is intended to be used for verification through
simulation, for timing analysis, for test analysis (testability analysis and fault grading) and for logic
synthesis.

The Verilog HDL is an IEEE standard - number 1364. The first version of the IEEE standard for
Verilog was published in 1995. A revised version was published in 2001; this is the version used by
most Verilog users. The IEEE Verilog standard document is known as the Language Reference
Manual, or LRM. This is the complete authoritative definition of the Verilog HDL.

A further revision of the Verilog standard was published in 2005, though it has little extra compared
to the 2001 standard. SystemVerilog is a huge set of extensions to Verilog, and was first published
as an IEEE standard in 2005. See the appropriate Knowhow section for more details about
SystemVerilog.

IEEE Std 1364 also defines the Programming Language Interface, or PLI. This is a collection of
software routines which permit a bidirectional interface between Verilog and other languages
(usually C).

Note that VHDL is not an abbreviation for Verilog HDL - Verilog and VHDL are two different
HDLs. They have more similarities than differences, however.
 A Brief History of Verilog

The history of the Verilog HDL goes back to the 1980s, when a company called Gateway Design
Automation developed a logic simulator, Verilog-XL, and with it a hardware description language.

Cadence Design Systems acquired Gateway in 1989, and with it the rights to the language and the
simulator. In 1990, Cadence put the language (but not the simulator) into the public domain, with
the intention that it should become a standard, non-proprietary language.

The Verilog HDL is now maintained by a non profit making organisation, Accellera, which was
formed from the merger of Open Verilog International (OVI) and VHDL International. OVI had the
task of taking the language through the IEEE standardisation procedure.

In December 1995 Verilog HDL became IEEE Std. 1364-1995. A significantly revised version was
published in 2001: IEEE Std. 1364-2001. There was a further revision in 2005 but this only added a
few minor changes.

Accellera have also developed a new standard, SystemVerilog, which extends Verilog.
SystemVerilog became an IEEE standard (1800-2005) in 2005. For more details, see the
Systemverilog section of KnowHow

There is also a draft standard for analog and mixed-signal extensions to Verilog, Verilog-AMS.
Verilog Combinational
Group 9
Members:
Jesalyn Biong
Christine Mae Nabos
Christian Ompad
Synthesis and HDLs

Hardware description language (HDL) is a convenient, device independent representation of digital logic.

Verilog
input a,b;
output [1:0] sum;
assign sum = ’{1b ’0, b};
0, a} + {1b

Compilation and  HDL description is compiled

into a netlist
Synthesis
Netlist  Synthesis optimizes the logic
g1 "and" n1 n2 n5
g2 "and" n3 n4 n6
g3 "or" n5 n6 n7
 Mapping targets a specific
Mapping hardware platform

FPGA PAL ASIC

(Custom ICs
)

Synthesis and Mapping for FPGAs

Infer macros: choose the FPGA macros that efficiently implement various parts of the HDL code.
Place-and-route: with area and/or speed in mind, choose the needed macros by location and route the
interconnect
 Verilog: The Module
 Verilog designs consist of interconnected
modules. a 1
 A module can be an element or collection of lower out
level design blocks. b 0 outbar
 A simple module with combinational
sel

logic might look like this:Out = sel ● a + sel ● b

2-to-1 multiplexer with inverted output

Declare and name a module; list its ports.

module mux_2_to_1(a, b, out, outbar, sel); Don’t forget that semicolon.
// This is 2:1 multiplexor Comment starts with //
Verilog skips from // to end of the line
input a, b, sel; Specify each port as input, output,
output out, outbar; or inout

Express the module’s behavior. Each

statement executes in parallel; order does
assign out = sel ? a : b; assign outbar = ~out; not matter.

endmodule Conclude the module code.

Gate Level Description

module muxgate (a, b, out, outbar, sel); input a, b, sel; output out, outbar; wire out1, out2, selb;

and a1 (out1, a, sel); not i1 (selb, sel); and a2 (out2, b , selb); or o1 (out, out1, out2); assign outbar =
~out; endmodule a
Verilog supports basic logic gates as out1
sel
primitives
out
 and, nand, or, nor, xor, xnor, not, buf outbar
 can be extended to multiple inputs: e.g., selb
out2
nand nand3in (out, in1, in2,in3); b
 bufif1 and bufif0 are tri-state buffers

Net represents connections between hardware elements. Nets are declared with the keyword wire.

Verilog Registers

 In digital design, registers represent memory elements (we will study these in the next few lectures)
 Digital registers need a clock to operate and update their state on certain phase or edge
 Registers in Verilog should not be confused with hardware registers
 In Verilog, the term register (reg) simply means a variable that can hold a value
 Verilog registers don’t need a clock and don’t need to be driven like a net. Values of registers can be
changed anytime in a simulation by assigning a new value to the register.

Mix-and-Match Assignments

 Procedural and continuous assignments can (and often do) co-exist within a module
 Procedural assignments update the value of reg. The value will remain unchanged till another
procedural assignment updates the variable. This is the main difference with continuous assignments in
which the right hand expression is constantly placed on the left-side

module mux_2_to_1(a, b, out, a 1

outbar
, sel);
input a, b,
sel; out
output out,
outbar; b 0 outbar
reg out;
always @ (a or b sel
or ) sel
begin
if sel
( ) out = a; procedural
else out = b; description
end
assignoutbar= ~out; continuous
description
endmodule
 The case Statement
 case and if may be used interchangeably to implement conditional execution within always blocks
 case is easier to read than a long string of if...else statements

module mux_2_to_1(a, b, out, outbar, sel);

input a, b, sel; output out, outbar; reg out;

always @ (a or b or sel) begin

if (sel) out = a; else out = b; end

assign outbar = ~out; endmodule

module mux_2_to_1(a, b, out, outbar, sel);

input a, b, sel; output out, outbar; reg out;

always @ (a or b or sel) begin case (sel)

1’b1: out = a; 1’b0: out = b; endcase end

The Power of Verilog: n-bit Signals

 Multi-bit signals and buses are easy in Verilog.
 2-to-1 multiplexer with 8-bit operands:
 module mux_2_to_1(a, b, out, outbar,
sel); input[7:0] a, b; input sel;
output[7:0] out, outbar; reg[7:0] out; 8
always @ (a or b or sel) begin if a 1 8
(sel) out = a; else out = b; end out
assign outbar = ~out; endmodule
b 0 outbar
 Concatenate signals using the { } operator assign 8 8
{b[7:0],b[15:8]} = {a[15:8],a[7:0]}; sel
 The Power of Verilog: Integer Arithmetic

 Verilog’s built-in arithmetic makes a 32-bit adder easy:

module add32(a, b, sum); input[31:0] a,b; output[31:0] sum;

assign sum = a + b; endmodule
 A 32-bit adder with carry-in and carry-out:
module add32_carry(a, b, cin, sum,
cout); input[31:0] a,b; input cin;
output[31:0] sum; output cout;
assign {cout, sum} = a + b + cin;
endmodule

module maybe_mux_3to1(a, b, c,
a 00 sel, out); input [1:0] sel;
input a,b,c; output out; reg
b 01 out out;
always @(a or b or c or sel)
c 10 begin case
(sel) 2'b00:
out = a;
2 2'b01: out =
b; 2'b10:
sel out = c;
endcase end
endmodule
3-to-1 MUX
(‘11’ input is a don’t-care) Is this a 3-to-1 multiplexer?
 Incomplete Specification Infers Latches

module maybe_mux_3to1(a, b, c, sel, out);

input [1:0] sel; input a,b,c; output out; reg out;

always @(a or b or c or sel) begin case (sel)

2'b00: out = a;
2'b01: out = b; 2'b10: out = c;
endcase end endmodule

if out is not assigned

during any pass through
the always block, then the previous value must be retained!

Synthesized Result:

a 00
b 01 D Q out
c 10
G
2
sel

sel[1]
sel[0]
 Avoiding Incomplete Specification

always @(a or b or c
or sel) begin
Precede all conditionals out = 1’bx;
with a default assignment case (sel) 2'b0
for all signals assigned within them… out = a;
2'b01: out = b;
2'b10: out = c; endca
end endmodule

Dangers of Verilog: Priority Logic

4-to-2 Binary Encoder

0 I3
1 I2 E1 1
0 I1 E0 0
0 I0

I3 I2 I1 I0 E1 E0
0 0 01 00
0 0 10 01
0 1 00 10
1 0 00 11
all others XX
module binary_encoder(i, e);
input [3:0] i; output [1:0] e;
reg e; always @(i) begin
if (i[0]) e = 2’b00; else if
(i[1]) e = 2’b01; else if (i[2])
e = 2’b10; else if (i[3]) e =
2’b11; else e = 2’bxx; end
endmodule

Intent: if more than one input is 1, the result

is a don’t-care.

I3 I2 I1 I0 E1 E0

0001 00
0010 01
0 100 10
1 000 11

Priority Logic

all others XX

Code: if i[0] is 1, the result is 00 regardless of the other inputs. i[0]

takes the highest priority.
 if-else and case statements are interpreted very literally!
Beware of unintended priority logic

Useful Boolean Operators

Bitwise operators perform bit-sliced operations on vectors
 ~(4’b0101) = {~0,~1,~0,~1} = 4’b1010
 4’b0101 & 4’b0011 = 4’b0001
Logical operators return one-bit (true/false) results
 !(4’b0101) = ~1 = 1’b0
Reduction operators act on each bit of a single input vector
 &(4’b0101) = 0 & 1 & 0 & 1 = 1’b0
Comparison operators perform a Boolean test on two
arguments
Verilog Sequential
Group 5
Members:
Jonesa Asis
Qerzey Tess Cisnero
Catherine Anne Jabague
 Verilog for Sequential Circuits

What will we learn?

 Short summary of Verilog Basics

 Sequential Logic in Verilog
 Using Sequential Constructs for Combinational Design
 Finite State Machines

Summary: Defining a module

 A module is the main building block in Verilog

 We first need to declare:

 Name of the module

 Types of its connections (input, output)

 Names of its connections

Summary: Defining a module

 Summary: What if we have busses ?
 You can also define multi-bit busses.
 [ range_start : range_end ]

Structural HDL Example

Short Instantiation
Summary: Bitwise Operators

Summary: Conditional Assignment

 ? : is also called a ternary operator because it operates on 3 inputs:

 s

 d1

 d0.
 Summary: How to Express numbers ?
N’Bxx
8’b0000_0001
 (N) Number of bits
 Expresses how many bits will be used to store the value
 (B) Base
 Can be b (binary), h (hexadecimal), d (decimal), o (octal)
 (xx) Number
 The value expressed in base, apart from numbers it can also have X and Z as values.

 Underscore _ can be used to improve readability

Summary: Verilog Number Representation

Precedence of Operations in Verilog

Sequential Logic in Verilog

 Define blocks that have memory

  Flip-Flops, Latches, Finite State Machines

 Sequential Logic is triggered by a ‘CLOCK’ event

 Latches are sensitive to level of the signal

 Flip-flops are sensitive to the transitioning of clock

 Combinational constructs are not sufficient

 We need new constructs:

 always

 initial
always Statement, Defining Processes

 Whenever the event in the sensitivity list occurs, the statement is executed

Example: D Flip-Flop
Example: D Flip-Flop

 The posedge defines a rising edge (transition from 0 to 1).

 This process will trigger only if the clk signal rises.

 Once the clk signal rises: the value of d will be copied to q

 ‘assign’ statement is not used within always block

 The <= describes a ‘non-blocking’ assignment

 We will see the difference between ‘blocking assignment’ and ‘non-blocking’
assignment in a while
Example: D Flip-Flop

 Assigned variables need to be declared as reg

 The name reg does not necessarily mean that the value is a register. (It could be, it does
not have to be).

D Flip Flop with Asynchronous Reset

 In this example: two events can trigger the process:

 A rising edge on clk

 A falling edge on reset

 For longer statements a begin end pair can be used

 In this example it was not necessary

 The always block is highlighted

 First reset is checked, if reset is 0, q is set to 0.

 This is an ‘asynchronous’ reset as the reset does not care what happens with the clock

 If there is no reset then normal assignment is made

D Flip-Flop with Synchronous Reset

 The process is only sensitive to clock
 Reset only happens when the clock rises. This is a ‘synchronous’ reset
 A small change, has a large impact on the outcome
D Flip-Flop with Enable and Reset

 A flip-flop with enable and reset

Note that the en signal is not in the sensitivity list
 Only when “clk is rising” AND “en is 1” data is stored

Example: D Latch
Summary: Sequential Statements so far

 Sequential statements are within an ‘always’ block

 The sequential block is triggered with a change in the sensitivity list

 Signals assigned within an always must be declared as reg

 We use <= for (non-blocking) assignments and do not use ‘assign’ within the always
block.

Blocking and Non-Blocking Assignments

 Blocking assignments (X=A)
 completes the assignment before continuing on to next statement
 Non-blocking assignments (X<=A)
 completes in zero time and doesn’t change the value of the target until a blocking point
(delay/wait) is encountered
 Example: swap
Swap
 The following code executes incorrectly
 One block executes first
 Loses previous value of variable
always @(posedge always @(posedge
CLK) begin CLK) begin
A = B; B = A;
end end
 Non-blocking assignment fixes this
 Both blocks are scheduled to execute by posedge CLK

always @(posedge always @(posedge

CLK) begin CLK) begin
A <= B; end B <= A; end
Summary: Basics of always Statements

 You can have many always blocks

Summary: Basics of always Statements

Assignments are different within always block

Verilog Syntax and
Commands
Group 2
Members:
Mark Christian Angeles
Jay Dan Baculi
John Michael Salinas
 Verilog Syntax and Structure
Design Entity

In Verilog, a design entity has only one design unit, the module declaration as depicted below.

module Module1
...
`include "module2.v"
...
endmodule

Module Declaration: The module declaration is the only design unit (design entity) in Verilog. It describes
both a design's interface to other desugns in the same environment, and its functional composition. All
declarations used within a model must be declared locally within the module. However, the compiler
directive `include is often used to reference to a separate system file. This directive is replaced with the
contents of the file it references when compiled by a simulator, synthesizer, or other similar tool. This is
very useful for writing generic Verilog code in a separate file that can be referenced from the code in any
other Verilog file.

Code structure

A design unit may instantiate other design units, which in turn may instantiate other design units in a
hierarchial manner. This hierarchical code structure should mimic inferred hardware structure when
hardware structure is being modelled. .

Declaration Statements

These statements declare objects for use in concurrent and sequential statements.

In Verilog design unit, a module statement does not need to be declared; nor do subprograms, that is,
a task or function. There is mo dedicated declarative region in a module, sequential block, concurrent
block, task or function.

Concurrent Statement
These are statements that are executed in paralllel. They operate independently of all other concurrent
statements. When modelling hardware strucutre they represent independent sections of the circuit being
modeled. Each concurrent statement is executed asynchronously with all other concurrent statement.

The continuous assignment and always statement are concurrent. A continuous assignment uses the
reserved word assign to assign data objects of any of the net data types. A task cannot be called
concurrently.

Sequential Statements

Sequential statements are statements that are executed depending upon the procedural flow of constructs
that surround them.

Sequential statements reside in an always statement. that may, or may not, contain sequential begin-
end procedurak blocks. The assigned objects are of type reg or integer.
simvision db1.shm/db1.trn

Data Types & Data Objects

Models in Verilog pass data from one point to another using data objects. Each data object has a collection
of possible values known as a value set. A data type defines this values set.

Data Types

Verilog defines a single base data type which has the following four values,

0 - represents a logic zero or false condition

1 - represents a logic one or true condition
X - represents an unknown logic value
Z - represents high-impedance state

Data objects of this type are declared in a model to have a single element, or any array of elements. For
example,
 wire W1;
wire [31:0] W2;

Data Objects

Net and Register data objects. If a net (wire, wand, and wor), or register (reg) data objects are declared
withput a range. By default, they are one bit wide and referred to as a scalar. If a range is declared, it has
multiple bits and is known as a vector. A vector may be referenced in its entirety, in part, or each individual
bit as desired.

Net: represents and models the physical connection of signals. A net object must always be assigned using
a continuous assignemtn statement. An assignment assigns values to net and register data types. A
continuous assignemtn statement assigns values to any of the net data types and makes a connection to an
actual wire in the inferref circuit.

wire:
Models a wire ehich structurally connects two signals together.
wor:
Models a wired OR of several drivers driving the same net. An OR gate will be synthesized.
wand:
Models a wired AND of several drivers driving the same net. An AND gate will be synthesised.

Register: the register (reg) data object holds its value from one procedural assignment statement to the next
and means it holds its value over simulation data cycles. No physical registers will be synthesized. A
procedural assignment stores a value in a register data type and is held until the next procedural assignment
to that register data type.

reg [3:0] Y1, Y2;

Parameter: a parameter data object defines a constant. Only integer (and not real) parameter constants
should be used with synthesis.

parameter A=4'b1011, B=4'b1000;

 parameter small=1, medium=2, large=3;

Integer: integer data objects are used to declare general purpose variables for use in loops. They have no
direct hardware intent and hold numerical values. No range is specified when an integer object is declared.
Integers are signed and produce 2's complement results.

integer N;

Operands

An expression comprises of operators and operands. Data objects form the operands of an expression and
it is their value that is used by operators in an expression.

Literals
Identifiers
function calls
Index and Slice Name

examples of each operands

Operators

Operators perform an opeation on one or more operands within an expression. An expression combines
operands with appropriate operators to produce the desired functional expression.

Groups of Verilog operators are shown on the left. The table shows the operators in descending order of
precedence. Operators with equal precedence are shown grouped.

examples of each operators

 Verilog HDL Operands

Literals

string (bit & character)

Numeric
real

Character string literals:

These are sequences of characters and are useful when designing simulatable test harnesses around a
synthesizable model. For example, "ABC".

Numeric Literals:
Numeric literals are simple constant numbers that may be specified in binary, octal, decimal or
hexadecimal. The specification of its size is optional as Verilog calsulates size based on the longest operand
value in an expression, and corresponding assigned value in an assignment. Examples are shown below.

12'b0011_0101_1100 12-bit sized binary constant number

2'O57 2 digit octal number
3_14159 default decimal number
4'h9FDE 4 digit hexadecimal number

module Literals (A1, A2, B1, B2, Y1, Y2);

input A1, A2, B1, B2;

output [7:0] Y1;
output [5:0] Y2;

parameter CST=4'b1010;
parameter twentyfive=25; //numeric literal
reg [7:0] Y1;
reg [5:0] Y2;

always @(A or A2 or B1 or B2 or Y1 or Y2)

begin
 //parenthesis are needed to be syntatically correct
if (A1==1)
Y1={CST,4'b0101}; //bit string literal
else if (A2==1)
Y1={CST,4'b0111}; //bit string literal
else
Y1={CST,4'b1111}; //bit string literal
if (B==0)
Y2=10; //integer literal
else if (B2==1)
Y2=15; //integer literal
else
Y2=twentyfive+10+15; //integer literal end
endmodule

Identifiers

Module
Parameter
Wire
Register
macros (text substitutions)

An identifier is used to give a name to a data object so that it may be easily referenced in a model. They are
the most commonly used type of operand. The value of the named object is returned as the operand value.
Verilog is case sensitive, so upper and lower case identifier names are treated as being different identifiers.

module Identifier (A, B, C, D, E, Y1, Y2);

input A, B, C, D; //identifiers
input [7:0] E;
output Y1, Y2;
reg F, Y1, Y2; //identifiers
 function AND_OR_Bits;
input [7:0] A;
begin
AND_OR_Bits=(A[7] & A[6] & A[5] & A[4]) & (A[3] | A[2] | A[1] |
A[0]);
end
endfunction

always @(A or B or C or D or E)
begin
F=A&B&AND_OR_Bits(E);
Y1=C&F;
Y2=D|F;
end
endmodule

Function calls

Function calls, which must reside in an expression, are operands. The single value returned from a function
is the operand value used in the expression.

module Functional_Calls (A1, A2, A3, A4, B1, B2, Y1, Y2);

input A1, A2, A3, A4, B1, B2;

output Y1, Y2;
reg Y1, Y2;

function function1;
input F1, F2, F3, F4;
begin
function1=(F1 & F2) | (F3 & F4);
end
endfunction
 always @(A1 or A2 or A3 or A4 or B1 or B2)
begin
Y1=function1(A1,A2,A3,A4)|B1|B2;
Y2=B1||B2||function1(A1,A2,A3,A4);
end
endmodule

Index and Slice Name

An index named operand specifies a single element of an array. For synthesis the array may be of type
constant, variable, or signal. A slice named operand is a sequence of elements within an arraty and is
identified Verilog using the colon ":".

module Index_Slice_Name (A, B, Y);

input [5:0] A, B;
output [11:0] Y;
parameter C=3'b100; reg [11:0] Y;

always @(A or B)
begin
Y[2:0]=A[0:2]; //swap bits
Y[3]=A[3]&B[3]; //single index
Y[5:4]={A[5]&B[5],A[4]|B[4]};
Y[8:6]=B[2:0]; //3-bit slice
Y[11:9]=C;
end
endmodule
 Verilog HDL Operators

Verilog Operator Name Functional Group

[] bit-select or part-select

() parenthesis

! logical negation logical

~ negation bit-wise
& reduction AND reduction
| reduction OR reduction
~& reduction NAND reduction
~| reduction NOR reduction
^ reduction XOR reduction
~^ or ^~ reduction XNOR reduction

+ unary (sign) plus arithmetic

- unary (sign) minus arithmetic

{} concatenation concatenation

{{ }} replication replication

* multiply arithmetic
/ divide arithmetic
% modulus arithmetic

+ binary plus arithmetic

- binary minus arithmetic

<< shift left shift

>> shift right shift

> greater than relational

>= greater than or equal to relational
< less than relational
<= less than or equal to relational
 == case equality equality
!= case inequality equality

& bit-wise AND bit-wise

^ bit-wise XOR bit-wise
| bit-wise OR bit-wise

&& logical AND logical

|| logical OR logical

?: conditional conditional

Arithmetic

There are five arithmetic operators in Verilog.

module Arithmetic (A, B, Y1, Y2, Y3, Y4, Y5);

input [2:0] A, B;
output [3:0] Y1;
output [4:0] Y3;
output [2:0] Y2, Y4, Y5;
reg [3:0] Y1;
reg [4:0] Y3;
reg [2:0] Y2, Y4, Y5;

always @(A or B)
begin
Y1=A+B;//addition
Y2=A-B;//subtraction
Y3=A*B;//multiplication
Y4=A/B;//division
Y5=A%B;//modulus of A divided by B
end
endmodule
Sign

These operators simply assign a positive "+" or negative "-" sign to a singular operand. Usually no sign
operators is defined, in which case the default "+" is assumed.

module Sign (A, B, Y1, Y2, Y3);

input [2:0] A, B;
output [3:0] Y1, Y2, Y3;
reg [3:0] Y1, Y2, Y3;

always @(A or B)
begin
Y1=+A/-B;
Y2=-A+-B;
Y3=A*-B;
end
endmodule

Relational

Relational operators compare two operands and returns an indication of whether the compared relationship
is true or false. The result of a comparison is either 0 or 1. It is 0 if the comparison is false and 1 is the
comparison is true.

module Relational (A, B, Y1, Y2, Y3, Y4);

input [2:0] A, B;
output Y1, Y2, Y3, Y4;
reg Y1, Y2, Y3, Y4;

always @(A or B)
begin
Y1=A<B;//less than
 Y2=A<=B;//less than or equal to
Y3=A>B;//greater than
if (A>B)
Y4=1;
else
Y4=0;
end
endmodule

Equality and inequality

Equality and inequality operators are used in exactly the same way as relational operators and return a true
or false indication depending on whether any two operands are equivalent or not.

module Equality (A, B, Y1, Y2, Y3);

input [2:0] A, B;
output Y1, Y2;
output [2:0] Y3;
reg Y1, Y2;
reg [2:0] Y3;
always @(A or B)
begin
Y1=A==B;//Y1=1 if A equivalent to B
Y2=A!=B;//Y2=1 if A not equivalent to B
if (A==B)//parenthesis needed
Y3=A;
else
Y3=B;
end
endmodule
Logical

Logical comparison operators are used in conjuction with relational and equality operators as described in
the relational operators section and equality and inequality operators section. They provide a means to
perform multiple comparisons within a a single expression.

module Logical (A, B, C, D, E, F, Y);

input [2:0] A, B, C, D, E, F;
output Y;
reg Y;

always @(A or B or C or D or E or F)
begin
if ((A==B) && ((C>D) || !(E<F)))
Y=1;
else
Y=0;
end
endmodule

Bit-wise

Logical bit-wise operators take two single or multiple operands on either side of the operator and return a
single bit result. The only exception is the NOT operator, which negates the single operand that follows.
Verilog does not have the equivalent of NAND or NOR operator, their funstion is implemented by negating
the AND and OR operators.

module Bitwise (A, B, Y);

input [6:0] A;
input [5:0] B;
output [6:0] Y;
reg [6:0] Y;
 always @(A or B)
begin
Y(0)=A(0)&B(0); //binary AND
Y(1)=A(1)|B(1); //binary OR
Y(2)=!(A(2)&B(2)); //negated AND
Y(3)=!(A(3)|B(3)); //negated OR
Y(4)=A(4)^B(4); //binary XOR
Y(5)=A(5)~^B(5); //binary XNOR
Y(6)=!A(6); //unary negation
end
endmodule

Shift

Shift operators require two operands. The operand before the operator contains data to be shifted and the
operand after the operator contains the number of single bit shift operations to be performed. 0 is being
used to fill the blank positions.

module Shift (A, Y1, Y2);

input [7:0] A;
output [7:0] Y1, Y2;
parameter B=3; reg [7:0] Y1, Y2;

always @(A)
begin
Y1=A<<B; //logical shift left
Y2=A>>B; //logical shift right
end
endmodule
Concatenation and Replication

The concatenation operator "{ , }" combines (concatenates) the bits of two or more data objects. The objects
may be scalar (single bit) or vectored (muliple bit). Mutiple concatenations may be performed with a
constant prefix and is known as replication.

module Concatenation (A, B, Y);

input [2:0] A, B;
output [14:0] Y;
parameter C=3'b011;
reg [14:0] Y;

always @(A or B)
begin
Y={A, B, (2{C}}, 3'b110};
end
endmodule

Reduction

Verilog has six reduction operators, these operators accept a single vectored (multiple bit) operand,
performs the appropriate bit-wise reduction on all bits of the operand, and returns a single bit result. For
example, the four bits of A are ANDed together to produce Y1.

module Reduction (A, Y1, Y2, Y3, Y4, Y5, Y6);

input [3:0] A;
output Y1, Y2, Y3, Y4, Y5, Y6;
reg Y1, Y2, Y3, Y4, Y5, Y6;

always @(A)
 begin
Y1=&A; //reduction AND
Y2=|A; //reduction OR
Y3=~&A; //reduction NAND
Y4=~|A; //reduction NOR
Y5=^A; //reduction XOR
Y6=~^A; //reduction XNOR
end
endmodule

Conditional

An expression using conditional operator evaluates the logical expression before the "?". If the expression
is true then the expression before the colon (:) is evaluated and assigned to the output. If the logical
expression is false then the expression after the colon is evaluated and assigned to the output.

module Conditional (Time, Y);

input [2:0] Time;

output [2:0] Y;
reg [2:0] Y;
parameter Zero =3b'000;
parameter TimeOut = 3b'110;

always @(Time)
begin
Y=(Time!=TimeOut) ? Time +1 : Zero;
end
endmodule