CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY (A)

ANALOG AND DIGITAL CIRCUITS LAB

(22EVC03)
B.E (EVL)
SEMISTER-III

CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY(A)

(Autonomous Institution under UGC, Affiliated to Osmania University)
Department of Electronics and Communication Engineering
Accredited by NBA and NAAC-UGC
Chaitanya Bharathi (Post), Gandipet, Hyderabad–500075
CHAITANYA BHARATHI INSTITUTE OF TECHNOLOGY (A)
OUR MOTTO: SWAYAM TEJASWIN BHAVA

Institute
To be a Centre of excellence in technical education and research.
Vision
Institute
To address the emerging needs through quality technical education and advanced research.
Mission

Department Vision:
To cultivate technical and innovative proficiency by fostering collaborative learning in Cutting edge Integrated
Circuit technologies to excel in global challenges
Department Mission:
M1:
To foster analytical thinking, creativity and technical expertise through theoretical foundation and hands-on
experience in cutting edge technologies/tools.

M2:
To nurture a collaborative learning environment and promote research excellence through industry interaction.

M3:
To inculcate good practices that emphasizes critical thinking, and ethical practices for the betterment of the society.

PEOS
PEO1:
Graduates will have a strong foundation in electronics principles with specialized knowledge in VLSI design and
related tools, enabling them to solve complex engineering problems in the domain of microelectronics (foundation
in engineering)

PEO2:
Graduates will be successful in their professional careers by exhibiting the ethical standards, leadership skills and
effective communication. (successful career and professionalism / professional ethics)

PEO3:
Graduates will engage in lifelong learning adapting to technological advancements, pursuing higher education,
research and professional development in emerging fields of VLSI.(innovation and lifelong learning)

PEO4:
Graduates will contribute to sustainable solutions for real time societal problems by collaborating across multi-
disciplinary teams/approaches (problem solving/interdisciplinary collaboration/social responsibility/ sustainablility).

PSOs
PSO1:
Ability to apply the acquired knowledge for electronic system design using Integrated Circuit technologies.

PSO 2:
Analyze and solve the complex Electronic System Design problems using software and hardware tools.

PSO3:
Will be competent enough to carry research and contribute to the societal needs.
CBIT (A) Revised AICTE Model Curriculum with effect from AY 2024-25 R-22 (A)

Program Outcomes of BE (Electronics Engineering – VLSI Design and Technology)

Program

Apply the knowledge of mathematics, science, engineering fundamentals, and

1. Engineering Knowledge an engineering specialization for the solution of complex engineering
problems.
Identify, formulate, research literature, and analyze complex engineering
2. Problem Analysis problems reaching substantiated conclusions using first principles of
mathematics, natural sciences, and engineering sciences.
Design solutions for complex engineering problems and design system
3. Design/Development of components or processes that meet the specified needs with appropriate
Solutions consideration for public health and safety, and cultural, societal, and
environmental considerations.
Use research-based knowledge and research methods including design of
4. Conduct Investigations
experiments, analysis and interpretation of data, and synthesis of the
of Complex Problems
information to provide valid conclusions.
Create, select, and apply appropriate techniques, resources, and modern
5. Modern Tool Usage engineering and IT tools, including prediction and modelling to complex
engineering activities, with an understanding of the limitations.
Apply reasoning informed by the contextual knowledge to assess societal,
6. The Engineer and the world health, safety, legal and cultural issues and the consequent responsibilities
relevant to the professional engineering practice.

Apply ethical principles and commit to professional ethics, diversity,

7. Ethics
behaviourand norms of the engineering practice.

8. Individual and Collaborative Function effectively as an individual, and as a member or leader in diverse
Team Work teams, and in multidisciplinary settings.

Communicate effectively on complex engineering activities with the

engineering community and with the society at large, such as, being able to
9. Communication
comprehend and write effective reports and design documentation, make
effective presentations, and give and receive clear instructions.

Demonstrate knowledge and understanding of the engineering and

10. Project Management and
management principles and apply these to one’s own work, as a member and
Finance
leader in a team, to manage projects and in multidisciplinary environments.
Recognize the need for and have the preparation and ability to engage in
11. Life-long Learning independent and life-long learning in the broadest context of technological
change.
 Chaitanya Bharathi Institute of Technology (A)

22EV03
ELECTRONICS ENGINEERING (VLSI Design and Technology)
ANALOG AND DIGITAL CIRCUITS LAB

Instruction 2PHours per Week

Duration of SEE 3 Hours
SEE 50 Marks
CIE 50 Marks
Credits 1

Prerequisite: Student should have knowledge on Electronic Devices lab and Network lab.

COURSE OBJECTIVES:
This course aims to:
1. The Understand the design of biasing and amplifiers.
2. AnalysisofBJT&FETinvariousconfigurationsusingsmallsignalequivalentmodelsandtheir
frequency response.
3. Know the concept of logic gates and ICs.

COURSE OUTCOMES:
Upon completion of this course, students will be able to:
1. Design of BJT/FET biasing circuits.
2. Experiment with single and multi-stage amplifiers.
3. Compare different performance of different oscillators.
4. Compare and contrast different types logic gates operation.
5. Implement different logic functions using different ICs.

Course Articulation Matrix

PO/PSO PO PO PO PO PO PO PO PO PO PO PO PSO PSO PSO

CO 1 2 3 4 5 6 7 8 9 10 11 1 2 3
CO 1 3 3 3 1 1 1 1 3 2 1 1 3 2 2
CO 2 3 3 3 1 1 1 1 3 2 1 1 3 2 2
CO 3 3 3 3 1 1 1 1 3 2 1 1 3 2 2
CO 4 3 3 3 1 1 1 1 3 2 1 1 3 2 2
CO 5 3 3 3 1 1 1 1 3 2 1 1 3 2 2

List of experiments
1. Design of a Common Emitter BJT amplifier and study of its frequency response.
2. Frequency response of two stage RC - Coupled Common Source FET amplifier
3. Design of a voltage shunt amplifier and study of its frequency response.
4. Design of current series amplifier and study of its frequency response.
5. Design and implementation of RC Oscillator.
6. Design and implementation of LC Oscillator
7. Design of Class-B power amplifier.
8. Functional verification of logic gates using ICs.
9. Implementation of logic function using decoder IC.
10. Implementation of logic function using Multiplexer IC.
11. Implementation of code converter.
12. Implementation of BCD Adder.
➢ Structured enquiry: Design a Frequency Divider Circuit using ICs
➢ Open-ended Enquiry: Design and implement a classroom sound monitoring system
using BJTs and a 0.5W speaker.
 EXPERIMENT - 01
Common Emitter BJT amplifier and study of its frequency response

AIM: To design a BJT common emitter amplifier using voltage divider bias and determine the
gain-bandwidth product from its frequency response.

APPARATUS:
1. CRO
2. Power Supply
3. Function Generator
4. Breadboard, Transistors, Resistors, and Capacitors
5. Decade Resistance Box and Connecting wires.
CIRCUIT DIAGRAM:

Fig.1. Single stage Common Emitter BJT amplifier

PROCEDURE:
1. Connect the circuit as shown in the Fig.1.
2. Find the maximum signal handling capacity. For this keep the frequency of input signal
at 1kHz and increase the amplitude of input signal till the output gets distorted. Then that
maximum value of input signal is maximum signal handling capacity (Vimax).
3. Now keep the amplitude of input signal less than the maximum signal handling capacity
(Vi=Vimax/2) and vary its frequency in the range 20 Hz to 1 MHz and for each and every
frequency note down the corresponding output voltage and calculate the voltage gain.
4. Make a plot of gain in dB Vs frequency and the plot is called Frequency response curve.
5. Find the bandwidth from the graph.

FORMULAE:
Bandwidth (BW) = fH–fL.

EXPECTED GRAPH:
A graph is plotted between f on X–axis and 20 log V0 / VI on Y-axis. It will be as shown in
Fig.2.
BW =fH – f L

Fig :2 Frequency Response of BJT CE Amplifier

OBSERVATIONS:
(1) Max. signal handling capacity (Vimax) =
(2) Amplitude of input signal applied Vi =
(Maintained Constants for all input frequency settings.
Frequency Response:
Sl.No. Frequency O/P voltage Gain (V0/ VI) Gain in dB
f (Hz) V0(V) 20 log (V0 / VI)

RESULT:
1. Mid-band gain (dB) =
2. Bandwidth (KHz)=
3. Gain-Bandwidth product (dBKHz) =

PRE-LAB QUESTIONS:
1. Explain the importance of DC biasing in the common emitter amplifier circuit. What
is the purpose of establishing a proper quiescent operating point?
2. Why is the circuit called Single Stage RC coupled Amplifier?
3. In which frequency range this circuit is used?
4. Indicate the bypass capacitor and coupling capacitor in the circuit?
VIVA-VOCE QUESTIONS:

5. Why the gain of the circuit decreases in low frequency region and high
frequency region?
6. What is the -3 dB bandwidth of an amplifier, and how is it related to its
frequency response?
7. How does the common emitter amplifier amplify AC signals while maintaining the
DC biasing point?
8. Explain the significance of emitter bypass capacitor.
 EXPERIMENT – 02
Frequency response of Two RC - Coupled CS FET amplifier

AIM
To calculate the voltage gain and to obtain the frequency response characteristics of a
single stage and two stage R-C coupled amplifier using FET.

APPARATUS
1. DC power supply
2. Signal generator
3. Dual trace oscilloscope
4. Patch cords
5. FET- BFW10/ BFW11
6. Resistors and Capacitors.

CIRCUIT DIAGRAM

Fig.1 Two stage RC coupled FET Amplifier

PROCEDURE
1. Connect the circuit as shown in the Fig.1.
2. Find the maximum signal handling capacity. For this keep the frequency of input signal
at 1KHz and vary its amplitude till the output gets distorted, then that value of input
signal is called maximum signal handling capacity Vi(max).
3. Now, keeping the input signal amplitude less than maximum signal handling capacity,
vary its frequency in the range 20Hz to 1MHz, and for every frequency, note down output
voltages V01 and V02, and calculate the voltage gain.
4. Now plot frequency response curves and find the bandwidth.

OBSERVATIONS:

1. Max. Signal handling capacity V(imax) =

2. Amplitude of input signal applied Vi =

Sl. Frequency Vo1 Vo2 AV1=V01/ AV2=V02/ Gain in dB Gain in dB

No. (Hz) (V) (V) VI VI 20 log10 AV1 20 log10 AV2
1 20
2 40
3 60
4 80
5 100
6 500
7 1K
8 5K
9 10K
10 40K
11 80K
12 100K
13 200K
 14 400K
15 600K
16 800K
17 1M

EXPECTED GRAPH:

A graph is plotted between by taking frequency (f) on X –axis and magnitude ( 20* log10 V0 /Vi )
on the Y axis. It will be as shown in the Fig.2.
BW = fH– f L

RESULT:

Maximum voltage gain of first stage amplifier is

Maximum voltage gain of Two stage amplifier is
The bandwidth of single stage amplifier is
The bandwidth of two stage amplifier is
PRE-LAB QUESTIONS:
1. What is the need for coupling?

2. What are the different types of coupling in amplifiers?

3. Compare RC and Transformer coupling.

4. What is the effect of cascading on the overall lower and upper 3dB frequencies?

5. What are the advantages of R-C coupling?

6. Give the difference between BJT & FET R-C coupling.

VIVA-VOCE QUESTIONS:

7. What are the parameters that will affect the low frequency and high frequency response

in RC coupled amplifier.

8. Why frequency falls at low and high frequencies.

9. How does the number of RC stages affect the frequency response of the amplifier?

10. Compare single, multistage amplifiers interms of gain, bandwidth, and G-BW product.
 EXPERIMENT –03
VOLTAGE SHUNT FEEDBACK AMPLIFIER

AIM: To find the frequency response and calculate the bandwidth of Voltage Shunt feedback.
amplifier circuit with and without feedback.
APPARATUS:
1. CRO
2. Power Supply - (0-30)V
3. Function Generator
4. Breadboard
5. BJT
6. Resistors
7. Capacitors
8. Connecting wires

CIRCUIT DIAGRAM:

Fig.1 Voltage shunt feedback amplifier

PROCEDURE:
1. Connect the circuit as shown in Fig.1.
2. In order to find the maximum signal handling capacity, set the frequency of input signal at
1 kHz and increase the amplitude of input signal till the output gets distorted. Then that
maximum value of input signal is Maximum signal handling capacity (Vimax).
3. Now keep the amplitude of input signal less than the maximum signal handling capacity,
vary its frequency in the range 20Hz to 1MHz, and for every frequency, measure the
corresponding output voltage and calculate the voltage gain. Using this procedure calculate
the voltage gain for the circuit with and without feedback. (with feedback: closed switch;
without feedback: open switch).
4. Draw the frequency response graph (gain(dB) vs frequency) as shown in Fig.2 and find the
bandwidth.

CALCULATIONS:
1. Bandwidth:
Without feedback (KHz) = F2 – F1
With feedback (KHz) = F2* – F1*
2. Gain bandwidth product:
Without Feedback (KHzdB) = Av * BW
With Feedback (KHzdB) = Av’ * BW’

OBSERVATIONS:
1. Max. signal handling capacity (Vimax)=
2. Amplitude of input signal applied (Vi) =
S.N Frequency Vo Vof AV1=V0/Vi AVf=V0f/Vi Gain in dB Gain in dB
o. (V) (V) 20 log10 AV1 20 log10 AVf

1 20

2 40

3 60

4 80

5 100

6 500

7 1K

8 5K

9 10K

10 40K

11 80K

12 100K

13 200K

14 400K

15 600K

16 800K

17 1M
 MODEL GRAPH:

Fig.2 Frequency response of Voltage shunt feedback amplifier with and without feedback
RESULT:
With Feedback Without Feedback
Gain
Bandwidth
Gain Bandwidth Product

PRE-LAB QUESTIONS:

1. Explain why this circuit is an example of voltage shunt feedback.

2. Identify the feedback path in this circuit.
3. What is the effect of applying voltage shunt feedback on input and output
impedances of circuit?
4. Explain how this feedback circuit is different from other types of circuits.
VIVA-VOCE QUESTIONS
5. Explain the principle behind voltage shunt feedback in amplifiers.
6. What are the advantages of using voltage shunt feedback in amplifier circuits?
7. Discuss the impact of voltage shunt feedback on the input and output impedance
of the amplifier.
8. How does voltage shunt feedback affect the gain of the amplifier?
 EXPERIMENT-04
CURRENT SERIES FEEDBACK AMPLIFIER
AIM: Obtain the frequency response of current series feedback amplifier circuit with and
without feedback and compare the gain bandwidth products.
APPARATUS:

1. CRO
2. Power Supply
3. Function Generator
4. Breadboard, Transistors, Resistors, and Capacitors
5. Decade Resistance Box and Connecting wires.

CIRCUIT DIAGRAM:

Fig.1 Current Series Feedback Amplifier

PROCEDURE:

1. Connect the circuit as shown in Figure.

2. For the given Current-Series feedback amplifier, find the maximum signal handling
capacity. For this keep the frequency of input signal at 1 kHz and increase the amplitude
of input signal till the output gets distorted. Then the maximum value of input signal is
maximum signal handling capacity (Vimax).
3. Now keep the amplitude of input signal less than the maximum signal handling capacity
and vary its frequency in the range 20 Hz to 1 MHz. And for every frequency find the
corresponding output voltage and calculate the voltage gain. Using this procedure calculate
the voltage gain for the circuit with and without feedback.
4. If terminal 1 is connected to terminal 2, then it is without feedback (without feedback:
closed switch; with feedback: open switch).
5. Make a plot of gain in dB Vs frequency and the plot is called the frequency response curve.
6. Find the bandwidth from the Fig.2.

CALCULATIONS:

1. BW Without Feedback=FH - FL
2. BW With Feedback= FH* - FL *
3. Gain bandwidth product
Without Feedback = Av * (BW)
With Feedback = Avf * (BWf)

OBSERVATIONS:

1. Max. Signal handling capacity (Vimax) =

2. Amplitude of input signal applied (Vi ) =

S.No. Frequency Vo Vof AV1=V0/Vi AVf=V0f/Vi Gain in dB Gain in dB
(V) (V) 20 log10 AV1 20 log10 AVf

1 20

2 40

3 60

4 80

5 100

6 500

7 1K

8 5K

9 10K

10 40K

11 80K

12 100K

13 200K

14 400K

15 600K

16 800K

17 1M
 Frequency Response Curve:

Fig.2 Frequency response of Current Series Feedback Amplifier with and without feedback

Graphs are plotted between f on X – axis and 20 log V0/ VI on Y axis for both with and without
feedback.

RESU
LT:
1. Frequency response curves are plotted.
2. Bandwidths (with feedback) =
(Without feedback) =
3. Gain (with feedback) =
(Without feedback) =
PRE-LAB QUESTIONS:

1. What is the effect of current series feedback on input and output impedances?
2. By applying negative feedback what happens to input and output impedances of
circuit?
3. What happens to Bandwidth and gain of the circuit if negative feedback is
applied?
4. How the voltage gain of an amplifier is stabilized by applying negative feedback?
VIVA-VOCE QUESTIONS:

5. What measures can be taken to increase or decrease the amount of feedback in a

current series feedback amplifier?
6. Describe the stability criteria for current series feedback amplifiers.
7. How does current series feedback impact the bandwidth and frequency response
of the amplifier?
8. Discuss the effect of current series feedback on the distortion and linearity of the
amplifier.
 EXPERIMENT -05

RC PHASE SHIFT OSCILLATOR

AIM: To verify the frequency of oscillation theoretically and practically for the given RC phase
shift oscillator.

APPARATUS:

1. Resistors (equal value) 5Nos

2. Capacitors (equal value) 5Nos
3. Variable resistor 1No
4. CRO 1Nos
5. Transistor 1Nos
6. CRO Probes 1Nos
7. Connecting Cables as required

CIRCUIT DIAGRAM:

Fig.1 RC phase shift oscillator

PROCEDURE:

1. Connect the circuit as shown in Fig.1 and switch on the DC power supply (25V )
to the circuit.
2. Now observe the period of oscillation in CRO and calculate the corresponding
frequency.
3. Verify with theoretical value using the formulae:
 fo=1/(2πRC√(6+4K)) where K = Rc/R

4. With the data obtained above, verify conditions for oscillations.

EXPECTED GRAPH:

RESULT:

The frequency of oscillation for the given RC phase shift oscillator has been computed
theoretically and is found to be Hz. The practical frequency is Hz.

PRE-LAB QUESTIONS:
1. What is the difference between amplifier and oscillator?
2. What are the key components of a phase-shift oscillator, and how do they contribute to
oscillation?
3. Explain the principle behind the RC phase-shift oscillator. How does it generate
oscillations?
4. What is the significance of the phase-shift network in the RC phase-shift oscillator?

VIVA-VOCE QUESTIONS:

5. What is an oscillator, and what is its primary function in electronic circuits?

6. Explain the Barkhausen criterion for oscillation to occur in an electronic circuit.
7. What are the main types of oscillators, and how do they differ in their operation?
8. What is the range of frequencies that the RC phase shift oscillator can generate?
 EXPERIMENT- 6(A)

DESIGN OF COLPITTS OSCILLATOR

AIM:
To design a Colpitt’s oscillator and measure its frequency of oscillation.
APPARATUS:

i) CRO
ii) Power Supply
iii) Bread board , Transistors ,Resistors and Capacitors
iv) Decade Capacitance Box ,Decade Inductance Box and Connecting wires
DESIGN:
1
Given Frequency f = ------------ =
2 LC
L = 5 mH then C = ------------ where C = (C1 C2)/( C1 + C2)
Let C1 = - - - - -------- Then C2 = - - - - - - - --

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in figure.

 2. Observe the output signal from CRO and find the frequency of the signal.

3. Compare the practical frequency with theoretical frequency. Inspect for frequency
values above 100 kHz.

4. By varying the values of C1 and C2 repeat the steps 1 to 4.

OBSERVATIONS:
Sl.No. Condition Frequency of Oscillations

C1 C2 C L Theoretical Practical Amplitude

1 T F=1/T V
2 LC
1.

2.

3.

EXPECTED GRAPH:

FORMULAE:
1
Given Frequency fth =
2 LC
where C = C1 C2
C1 + C2
RESULT: The functioning of Colpitt’s oscillator is verified and the frequency of oscillations
generated is found to be ______________ Hz.

VIVA VOCE:
1. What is meant by frequency stability of oscillator?

2. For generating which frequencies, this circuit is used?

3. What is the difference between amplifier and oscillator?

4. What are relaxation oscillators?

 EXPERIMENT-6(B)

DESIGN OF HARTLEY OSCILLATOR

AIM:
To design a Hartley oscillator and measure its frequency of oscillation.

APPARATUS:
i) CRO
ii) Power Supply
iii) Bread board , Transistors ,Resistors and Capacitors
iv) Decade Capacitance Box ,Decade Inductance Box and Connecting wires

CIRCUIT DIAGRAM:

PROCEDURE:

1. Connect the circuit as shown in figure.

2. Observe the output signal from CRO.
3. Find the frequency of the signal. Inspect for frequency values above 100 kHz.
4. Compare the practical frequency with theoretical frequency.
5. By varying the values of L1 and L2 repeat the steps 1 to 4.
OBSERVATION:
Condition Frequency Oscillations Amplitude
L1 L2 C L1 + L2 Theoretical Practical (volts)

EXPECTED GRAPH:

FORMULAE:
1
Given Frequency fth =
2 LC
where L= L1+L2

RESULT: The Hartley oscillator has been verified and the frequency of oscillations generated is
found to be ______________ Hz.
VIVA VOCE:
1. Give the conditions for oscillations in Hartley Oscillator?
2. What is meant by frequency stability of oscillator?
3. Which component is responsible, for the feedback in the circuit of Hartley
Oscillator ?
4. What is the difference between amplifier and oscillator?
5. What is the frequency range that can be generated using the above circuit?
 EXPERIMENT-07
CLASS - B POWER AMPLIFIER

Aim: To design a Class – B power amplifier and determine its efficiency at optimum load.
APPARATUS:
i) CRO
ii) Power Supply
iii) Breadboard , Transistors ,Resistors and Capacitors
iv) Audio Frequency power output meter
v) Decade Resistance Box and Connecting wires
CIRCUIT DIAGRAM:

Fig. Class B Amplifier

PROCEDURE:
1. Connect the circuit as shown in figure and supply the DC voltage Vcc (6V) to the circuit.
2. Connect CRO across input and output.
3. Feed the signal (Vs) at the input from a signal generator and adjust its frequency to 1 KHz.
 4. Increase the input voltage till the output wave starts showing distortion.
Measure the value of the input signal voltage. This gives the maximum signal handling
capacity of the circuit.
5. Connect the audio power meter across RL. By varying the impedance of the power meter,
note down the readings of power.
6. Plot a graph between output power and impedance. For a particular value of impedance,
the power observed is maximum. This is the value of optimum load for the circuit.
7. With the optimum load connected to the circuit, read the DC current Ide from ammeter and
calculate the power consumed as follows.
8. Calculate the efficiency of the amplifier (n)
η= (Pac / Pdc) X 100% = π Vm /4 VCC

OBSERVATIONS:
SL.No Load Output Input power n = (Pac / Pdc)
impedance Power X100%

EXPECTTED GRAPH
 RESULTS:
1. The optimum load for the circuit is ..........................
2. Efficiency of the amplifier is......................... %

PRE-LAB QUESTIONS:
1. What are the different classes of amplifiers?
2. Explain the operation of class B amplifier.
3. Compare the efficiencies of different amplifiers.
4. What are the disadvantages of class B amplifiers?
5. What is distortion?

VIVA-VOCE QUESTIONS:
6. What are the typical applications of Class B power amplifiers in electronic systems?
7. What measures can be taken to minimize crossover distortion in Class B power
amplifiers?
8. Compare and contrast Class A and Class B power amplifiers in terms of
efficiency, distortion, and linearity.
 EXPERIMENT - 8
Logic Gates using ICs
Aim:-
Introduction to digital ICs, and verification of the truth tables of logic gates using ICs.

Apparatus Required:-
Digital lab kit, single strand wires, breadboard, TTL IC’s

Gates IC NO.

AND 7408

OR 7432

NAND 7400

NOR 7402

NOT 7404

XOR 74136

Theory:-
Logic gates are idealized or physical devices implementing a Boolean function, which it
performs a logical operation on one or more logical inputs and produce a single output.
Depending on the context, the term may refer to an ideal logic gate, one that has for
instance zero rise time and unlimited fan out or it may refer to anon-ideal physical device.

The main hierarchy is as follows:-

1. Basic Gates

2. Universal Gates

3. Advanced Gates
Basic Gates
1. AND gate: - Function of AND gate is to give the output true when both the inputs
are true. In all the other remaining cases output becomes false. Following table
justifies the statement:-

Input A Input B Output

1 1 1

1 0 0

0 1 0

0 0 0

IC 7408

2. OR gate: - Function of OR gate is to give output true when one of the either inputs
are true .In the remaining case output becomes false. Following table justify the
statement:-

Input A Input B Output

0 0 0

0 1 1

1 0 1

1 1 1
 IC 7432

3. NOT gate: -Function of NOR gate is to reverse the nature of the input .It
converts true input to false and vice versa. Following table justifies the statement :-

Input Output

1 0

0 1

IC 7404
Universal Gates
1. NAND gate: -Function of NAND gate is to give true output when one of the two
provided input are false. In the remaining output is true case .Following table
justifies the statement :-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 1

IC 7400

2. NOR gate: - NOR gate gives the output true when both the two provided input
are false. In all the other cases output remains false. Following table justifies the
statement :-

Input A Input B Output

1 1 0

1 0 0

0 1 0

0 0 1
 IC 7402

Advanced Gates
1. XOR gate: - The function of XOR gate is to give output true only when both the
inputs are true. Following table explain this:-

Input A Input B Output

1 1 0

1 0 1

0 1 1

0 0 0

IC 74136
 Procedure:-
• Place the breadboard gently on the observation table.
• Fix the IC which is under observation between the half shadow line of
breadboard, so there is no shortage of voltage.
• Connect the wire to the main voltage source (Vcc) whose other end is connected
to last pin of the IC (14 place from the notch).
• Connect the ground of IC (7th place from the notch) to the ground terminal
provided on the digital lab kit.
• Give the input at any one of the gate of the ICs i.e. 1st, 2nd, 3rd, 4th gate by using
connecting wires.(In accordance to IC provided).

• Connect output pins to the led on digital lab kit.

• Switch on the power supply.

• If led glows red then output is true, if it glows green output is false, which is
numerically denoted as 1 and 0 respectively. The Color can change based on the
IC manufacturer it’s just verification of the Truth Table not the color change.

Result:-

Precautions:-
• All connections should be made neat and tight.
• Digital lab kits and ICs should be handled with utmost care.
• While making connections main voltage should be kept switched off.
• Never touch live and naked wires.

Pre Experiment Questions:-

1. What is a logic gate?

Ans: Logic gate is a physical device implementing a Boolean function and performs

Logical operation on one or more logic inputs and produces a single logic output.

2. What are universal gates?

Ans: NAND and NOR gates are called universal gates as any type of logic gates or logic

Functions can be implemented by these gates.

 3. What are basic gates?

Ans: AND, OR, Not are called basic gates.

4. State De-Morgan’s theorem.

Ans: (x+y)l = xlyl (xy)l = xl + yl

5. What is the primary motivation for using Boolean algebra to simplify logic expressions?

Ans: (1) Boolean algebra reduces the number of inputs required.

(2) It will reduce number of gates

(3) It makes easier to understand the overall function of the circuit.

Post Experiment Questions:-

1. Which of the logical operations is represented by the + sign in Boolean algebra? Ans: OR gate

2. Which of the two input logic gate can be used to implement an inverter circuit? Ans: Ex-NOR

gate

3. Which are the logic gates whose all output entries are logic 1 except for one entry there is logic
0?

Ans: NAND and NOR gate

4. TTL operates from a 5 volt supply.

5. When the output of a NOR gate is high?

Ans : If all the inputs are low

 Experiment No. 9
Logic function Implementations using Decoder.
Aim:
To verify logic functions using 3:8 Decoder (IC74ALS138)
Apparatus:
1. IC 74ALS138 1no
2. IC7400 2no
3. Trainer Board 1no
4. Regulated Power supply 1no
5. Single strand wires

Pin Diagram:
IC 74ALS 138

Logic Diagram

IC 7400 IC 7432
Circuit Diagrams:
Logic Function F1= Σ m (2,3,5,7)

Fig.2.1 Logic Function Implementation F1 using 74ALS 138

Logic Function F2= Σ m (0,2,3,5)

Fig.2.2 Logic Function Implementation F2 using 74ALS 138

Functional Verification tables:

 Theory:
A decoder is a logic circuit that accepts a set of inputs that represents a binary number and activates
only the output that corresponds to that input number. In other words, a decoder circuit looks at its inputs,
determines which binary number is present there, and activates the one output that corresponds to that
number; all other outputs remain inactive. The diagram for a general decoder is with N inputs and M
outputs. Because each of the N inputs can be 0 or 1, there are possible input combinations or codes. For each
of these input combinations, only one of the M outputs will be active (HIGH); all the other outputs are
LOW. Many decoders are designed to produce active-LOW outputs, where only the selected output is LOW
while all others are HIGH. This situation is indicated by the presence of small circles on the output lines in
the decoder diagram.

Some decoders do not utilize all of the possible input codes but only certain ones. For example, a BCD-to-
decimal decoder has a four-bit inputcode and ten output lines that correspond to the ten BCD code groups
0000 through 1001. Decoders of this type are often designed so that if any of
the unused codes are applied to the input, none of the outputs will be activated.
This decoder can be referred to in several ways. It can be called a 3-lineto- 8-line decoder because it has
three input lines and eight output lines. It can also be called a binary-to-octal decoder or converter because
it takes a three bit binary input code and activates one of the eight (octal) outputs corresponding to that code.
It is also referred to as a 1-of-8 decoder because only 1 of the 8 outputs is activated at one time.
ENABLE Inputs
Some decoders have one or more ENABLE inputs that are used to control the operation of the
decoder. For example, refer to the decoder and visualize having a common ENABLE line connected to a
fourth input of each gate. With this ENABLE line held HIGH, the decoder will function normally, and the
A, B, C input code will determine which output is HIGH. With ENABLE held LOW, however, all of the
outputs will be forced to the LOW state regardless of the levels at the A, B, C inputs. Thus, the decoder is
enabled only if ENABLE is HIGH.
By examining the logic diagram of 74ALS138 decoder carefully, we can determine exactly how this
decoder functions. First, notice that it has NAND gate outputs, so its outputs are active-LOW. Another
indication is the labeling of the outputs as O7,O6,O5 and so on; the over bar indicates active-LOW outputs.
The input code is applied atA2,A1 andA0 , where A2 is the MSB. With three inputs and eight outputs, this is
a 3-to-8 decoder or, equivalently, a 1-of-8 decoder.
Inputs ̅̅̅̅
𝐸1 , ̅̅̅̅
E2 and E3 are separate enable inputs that are combined in the AND gate. In order to enable
the output NAND gates to respond to the input code at A2A1A0, this AND gate output must be HIGH. This
̅̅̅̅= E2
will occur only when 𝐸1 ̅̅̅̅= 0 and E3 = 1.In other words, ̅̅̅̅
𝐸1 and ̅̅̅̅
𝐸2are active-LOW, E3 is active-
HIGH, and all three must be in their active states to activate the decoder outputs. If one or more of the
enable inputs is in its inactive state, the AND output will be LOW, which will force all NAND outputs to
their inactive HIGH state regardless of the input code. This operation is summarized in the truth table in
Figure 9-3(b). Recall that x represents the don’t-care condition. The logic symbol for the 74ALS138 is
shown in Figure 9-3(c). Note how the active-LOW outputs are represented and how the enable inputs are
represented. Even though the enable AND gate is shown as external to the decoder block, it is part of the
IC’s internal circuitry. The 74HC138 is the high-speed CMOS version of this decoder.

Procedure:
1. Using the 3:8 Decoder(IC74ALS 138) with NAND gate IC 7400 and OR gate IC7432 Connect the
circuit as shown in the fig 2.1and 2.2
2. Connect the data inputs as per the truth tables.
3. Tabulate the outputs of the logic function F1 and F2 in the observation table.
4. Also verify the truth tables of logic functions using Boolean algebraic expressions.
 Precautions:
1. Connect the circuit properly without any loose connections and ensure the proper ground
connections.
2. Make sure that power supply should not exceed more than +5V

Result:
The Logic functions are designed & realized using 3:8 decoder 74ALS138 & their truth tables are
verified.

Discussion Questions:
1. Explain the importance of decoders?
2. Implement 4X16 and 5X32 decoders by using 74ALS 138IC.
3. Explain the various applications of decoders?
4. Write the differences between decoder, encoder and priority encoder?
 Experiment No. 9
Logic function Implementation using Multiplexers
Aim:
To verify full adder and full Subtractor using 8:1 MUX (IC74LS151) and 4:1 MUX (IC74LS153)
Apparatus:

1. IC 74LS151 1no
2. IC74LS153 1 no
3. IC7404 1no
4. Trainer Board 1no
5. Regulated Power supply 1no
6. Single strand wires

Pin Diagram:
IC 74151

IC 74153

Circuit Diagrams:
Full adder using 8:1 MUX
Fig.3.1 FA- Sum output circuit by using 74151 Fig.3.2 FA- Carry output circuit by using 74151

Full Subtractor using 8:1 MUX

Fig.3.3 FS- Difference output circuit by using 74151 Fig.3.4 FS- Borrow output circuit by using 74151
Full adder using 4:1 MUX
 Fig.3.5 FA- Sum and carry output circuit by using 74153

Full Subtractor using 4:1 MUX

Fig.3.6 FS- Difference and Borrow output circuit by using 74153

Truth tables:

Theory:
Multiplexer is a digital switch. It allows digital information from several sources to be routed onto a single
output line. The basic multiplexer has several data input lines and a single output line. The selection of a
particular input line is controlled by a s set of selection lines. Normally, there are 2 n input lines and n select lines
whose bit combinations determine which input is selected. Therefore, multiplexer is ‘many into one’ and it
provides the digital equivalent of an analog selector switch.
A full –adder is a combinational circuit that forms the arithmetic sum of three input bits. It consists of three
inputs and two outputs. The outputs are designated by symbol ‘S’ for sum and ‘C’ for carry. The truth table of the
full adder is shown in the table 1. A full subtractor is a combinational circuit that performs a subtraction between
two bits, taking into account that a 1 may have been borrowed by a lower significant stage. This circuit has three
inputs and two outputs. The two outputs D and B represent the difference and output borrows respectively.
In implementation these circuits by using the multiplexers, we choose the required order of the multiplexer
based on the inputs and if the input value is ‘1’ those are connected to the VCC and if the input are ‘0’ are given to
ground. By the proper selection of input we will get the corresponding outputs.

Procedure:
1. Using the 8:1 MUX(IC74151) Connect the circuit as shown in the fig 3.1, 3.2 , 3.3 and 3.4
2. Connect the data inputs as per the truth tables of select inputs.
3. Tabulate the output result of sum (S), carry (C), difference (D) and borrow (B) in the observation table.
4. Also verify the truth tables of full adder / Subtractor using 4:1 MUX (IC74153) as shown in fig 3.5 and 3.6.

Precautions:
1. Connect the circuit properly without any loose connections and ensure the proper ground connections.
2. Make sure that power supply should not exceed more than +5V

Result:

The Full Adder and Full Subtractor are designed & realized using 8:1 MUX (IC74151) and 4:1 MUX (IC74153)
& their truth tables are verified

Discussion Questions:

1. What is a multiplexer and de-multiplexer?

2. What are the applications of multiplexer and de-multiplexer?
3. Write the difference between
i. MUX & DEMUX
ii. Encoder and Decoder
iii. PLA &PAL
4. Realize m(1,3,4,5,6,8,9,12,14,15) using
iv. One 8:1 MUX
v. Two 8:1 MUX and OR gate
vi. One 4:1 MUX

5. Write the importance of STROBE input.

6. Implement 64:1 MUX by using the 4:1 MUX
7. Implement 1:32 DEMUX by using the 1:4 DEMUX
 Experiment No: 11
Code Conversion
Aim: To Design and implement the circuit for the following 4-bit Code conversion.
i) Binary to Gray Code
ii) Gray to Binary Code
iii) BCD to Excess – 3 Code
iv) Excess-3 to BCD Code
Hardware & software requirements:
Digital Trainer Kit, IC 7404, IC 7432, IC 7408, IC 7486, Patch Cord, + 5V Power Supply

Theory:
There is a wide variety of binary codes used in digital systems. Some of these codes are binary-
coded- decimal (BCD), Excess-3, Gray, octal, hexadecimal, etc. Often it is required to convert
from one code to another. For example the input to a digital system may be in natural BCD and
output may be 7-segment LEDs. The digital system used may be capable of processing the data
in straight binary format. Therefore, the data has to be converted from one type of code to
another type for different purpose. The various code converters can be designed using gates.

1) Binary Code:

It is straight binary code. The binary number system (with base 2) represents values using two
symbols, typically 0 and 1.Computers call these bits as either off (0) or on (1). The binary code
are made up of only zeros and ones, and used in computers to stand for letters and digits. It is
used to represent numbers using natural or straight binary form.

It is a weighted code since a weight is assigned to every position. Various arithmetic operations
can be performed in this form. Binary code is weighted and sequential code.

2) Gray Code:

It is a modified binary code in which a decimal number is represented in binary form in such a
way that each Gray- Code number differs from the preceding and the succeeding number by a
single bit. (E.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101.
These two codes differ by only one bit position i. e. third from the left.) Whereas by using binary
code there is a possibility of change of
all bits if we move from one number to other in sequence (e.g. binary code for 7 is 0111 and
for 8 it is 1000). Therefore it is more useful to use Gray code in some applications than binary
code.

The Gray code is a nonweighted code i.e. there are no specific weights assigned to the bit

positions. Like binary numbers, the Gray code can have any no. of bits. It is also known as

reflected code.

Applications:

1. Important feature of Gray code is it exhibits only a single bit change from one code word to the next in
sequence. This property is important in many applications such as Shaft encoders where error
susceptibility increases with number of bit changes between adjacent numbers in sequence.

2. It is sometimes convenient to use the Gray code to represent the digital data converted from the analog
data (Outputs of ADC).

3. Gray codes are used in angle-measuring devices in preference to straight forward binary encoding.

4. Gray codes are widely used in K-map

The disadvantage of Gray code is that it is not good for arithmetic operation

Binary to Gray Conversion

In this conversion, the input straight binary number can easily be converted to its Gray code equivalent.

1. Record the most significant bit as it is.

2. EX-OR this bit to the next position bit, record the resultant bit.
3. Record successive EX-ORed bits until completed.
4. Convert 0011 binary to Gray.

0 0 1 1 Binary code

+ + +

0 0 1 0 Gray code
(MSB) (LSB)

Fig. 1 Binary to Gray Conversion

Gray to Binary Conversion

1. The Gray code can be converted to binary by a reverse process.

2. Record the most significant bit as it is.
3. EX-OR binary MSB to the next bit of Gray code and record the resultant bit.
4. Continue the process until the LSB is recorded.
5. Convert 1011 Gray to Binary code.

1 0 1 1 Gray code

+ + +

1 1 0 1 Binary code
(MSB) (LSB)
Fig. 2 Gray to Binary Conversion

3) BCD Code:

Binary Coded Decimal (BCD) is used to represent each of decimal digits (0 to 9) with a 4-bit
binary code. For example (23)10 is represented by 0010 0011 using BCD code rather than
(10111)2 This code is also known as 8-4-2-1 code as 8421 indicates the binary weights of
four bits(23, 22, 21, 20). It is easy to convert between BCD code numbers and the familiar
decimal numbers. It is the main advantage of this code. With four bits, sixteen numbers (0000 to
1111) can be represented, but in BCD code only 10 of these are used. The six code combinations
(1010 to 1111) are not used and are invalid.

Applications: Some early computers processed BCD numbers. Arithmetic operations can be
performed using this code. Input to a digital system may be in natural BCD and output may be 7-
segment LEDs.

It is observed that more number of bits are required to code a decimal number using BCD code
than using the straight binary code. However in spite of this disadvantage it is very convenient
and useful code for input and output operations in digital systems.
4) EXCESS-3 Code:

Excess-3, also called XS3, is a non weighted code used to express decimal numbers. It can be
used for the representation of multi-digit decimal numbers as can BCD.The code for each
decimal number is obtained by adding decimal 3 and then converting it to a 4-bit binary number.
For e.g. decimal 2 is coded as 0010
+ 0011 = 0101 in Excess-3 code.

This is self complementing code which means 1‘s complement of the coded number yields 9‘s
complement of the number itself. Self complementing property of this helps considerably in
performing subtraction operation in digital systems, so this code is used for certain arithmetic
operations.

BCD To Excess – 3 Code Conversions:

Convert BCD 2 i. e. 0010 to Excess – 3 codes

For converting 4 bit BCD code to Excess – 3, add 0011 i. e. decimal 3 to the respective code
using rules of binary addition.

0010 + 0011 = 0101 – Excess – 3 code for BCD 2

Excess – 3 Code To BCD Conversion:

The 4 bit Excess-3 coded digit can be converted into BCD code by subtracting decimal value 3
i.e. 0011 from 4 bit Excess-3 digit.

e.g. Convert 4-bit Excess-3 value 0101 to equivalent BCD code.

0101-0011= 0010- BCD for 2

Design:
A) Binary to Gray Code Conversion:

1) Truth Table:

Table 1 Binary to Gray Code Conversion

INPUT (BINARY CODE) OUTPUT (GRAY CODE)

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 0 0 0 1 1

0 0 1 1 0 0 1 0

0 1 0 0 0 1 1 0

0 1 0 1 0 1 1 1

0 1 1 0 0 1 0 1

0 1 1 1 0 1 0 0

1 0 0 0 1 1 0 0

1 0 0 1 1 1 0 1

1 0 1 0 1 1 1 1

1 0 1 1 1 1 1 0

1 1 0 0 1 0 1 0

1 1 0 1 1 0 1 1

1 1 1 0 1 0 0 1

1 1 1 1 1 0 0 0
2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 4 K-Map for Reduced Boolean Expressions of Each Output (Gray Code)
3) Circuit Diagram:

Fig. 5 Logical Circuit Diagram for Binary to Gray Code Conversion

B) Gray to Binary Code Conversion:

1) Truth Table:

Table 2 Gray to Binary Code Conversion

INPUT (GRAY CODE) OUTPUT (BINARY CODE)

G3 G2 G1 G0 B3 B2 B1 B0

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 0 1 1 0 0 1 0

0 0 1 0 0 0 1 1
Digital Electronics Lab (Pattern 2015)

0 1 1 0 0 1 0 0

0 1 1 1 0 1 0 1

0 1 0 1 0 1 1 0

0 1 0 0 0 1 1 1

1 1 0 0 1 0 0 0

1 1 0 1 1 0 0 1

1 1 1 1 1 0 1 0

1 1 1 0 1 0 1 1

1 0 1 0 1 1 0 0

1 0 1 1 1 1 0 1

1 0 0 1 1 1 1 0

1 0 0 0 1 1 1 1
Digital Electronics Lab (Pattern 2015)

2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 6 K-Map for Reduced Boolean Expressions of Each Output (Binary Code)

G1G0G2G3 00 01 11 10

00 0 11 0 1
1 1 Note:-Use this k-map instead one that
01 1 0 1 0 is given above.
1 1

11 0 0 1
1 1
10 1 0 1 0
1 1

B0 = G3 X-OR G2 X-OR G1 X-OR G0

Digital Electronics Lab (Pattern 2015)

3) Circuit Diagram:

Fig. 7 Logical Circuit Diagram for Gray to Binary Code Conversion

Digital Electronics Lab (Pattern 2015)

C) BCD to Excess-3 Code Conversion:

1) Truth Table:

Table 3 BCD to Excess-3 Code Conversion

INPUT (BCD CODE) OUTPUT (EXCESS-3 CODE)

B3 B2 B1 B0 E3 E2 E1 E0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x x
Digital Electronics Lab (Pattern 2015)

2) K-Map for Reduced Boolean Expressions of Each Output:

Fig. 8 K-Map for Reduced Boolean Expressions Of Each Output (Excess-3 Code)

3) Circuit Diagram:

BCD TO EXCESS-3 CONVERTER

Digital Electronics Lab (Pattern 2015)

Fig.9 Logical Circuit Diagram for BCD to Excess-3 Code Conversion

D) Excess-3 to BCD Conversion:

1) Truth Table:

Table 4 Excess-3 To BCD Conversion

INPUT (EXCESS-3 CODE) OUTPUT (BCD CODE)

E3 E2 E1 E0 B3 B2 B1 B0

0 0 0 0 X X X X

0 0 0 1 X X X X

0 0 1 0 X X X X

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

1 1 0 1 X X X X

1 1 1 0 X X X X

1 1 1 1 X X X X
2) K-Map for Reduced Boolean Expressions of Each Output:

Fig 10 K-Map For Reduced Boolean Expressions of Each Output (BCD Code)
3) Circuit Diagram:

EXCESS-3 TO BCD CONVERTER

Fig.11 Logical Circuit Diagram for Excess-3 to BCD Conversion

Outcome:
Thus, we studied different codes and their conversions including

applications. The truth tables have been verified using IC 7486, 7432,

7408, and 7404.

FAQ’s with answers:

Q.1) What is the need of code converters?

There is a wide variety of binary codes used in digital systems. Often it is required to convert
from one code to another. For example the input to a digital system may be in natural BCD and
output may be 7- segment LEDs. The digital system used may be capable of processing the data
in straight binary format. Therefore, the data has to be converted from one type of code to
another type for different purpose.

Q.2) What is Gray code?

It is a modified binary code in which a decimal number is represented in binary form in such a
way that each Gray- Code number differs from the preceding and the succeeding number by a
single bit.

(e.g. for decimal number 5 the equivalent Gray code is 0111 and for 6 it is 0101. These two
codes differ by only one bit position i. e. third from the left.) It is non weighted code.

Q.3) What is the significance of Gray code?

Important feature of Gray code is it exhibits only a single bit change from one code word to the
next in sequence. Whereas by using binary code there is a possibility of change of all bits if we
move from one number to other in sequence (e.g. binary code for 7 is 0111 and for 8 it is 1000).
Therefore it is more useful to use Gray code in some applications than binary code.

Q.4) What are applications of Gray code?

1. Important feature of Gray code is it exhibits only a single bit change from one code word to the next in
sequence. This property is important in many applications such as Shaft encoders where error
susceptibility increases with number of bit changes between adjacent numbers in sequence.
2. It is sometimes convenient to use the Gray code to represent the digital data converted from
the analog data (Outputs of ADC).

3. Gray codes are used in angle-measuring devices in preference to straight forward binary encoding.

4. Gray codes are widely used in K-map

Q.5) What are weighted codes and non-weighted codes?

In weighted codes each digit position of number represents a specific weight. The codes
8421, 2421, and 5211 are weighted codes.

Non weighted codes are not assigned with any weight to each digit position i.e. each
digit position within the number is not assigned a fixed value. Gray code, Excess-3 code
are non-weighted code.

Q.6) Why is Excess-3 code called as self-complementing code?

Excess-3 code is called self-complementing code because 9‘s complement of a coded

number can be obtained by just complementing each bit.

Q.7) What is invalid BCD?

With four bits, sixteen numbers (0000 to 1111) can be represented, but in BCD code only
10 of these are used as decimal numbers have only 10 digits fro 0 to 9. The six code
combinations (1010 to 1111) are not used and are invalid.
 Experiment No.12
Binary Parallel Adder & Subtractor, BCD Adder using ICs

Aim:
a) To design controllable binary parallel Adder & Sub tractor using IC 7483
b) To design BCD adder using two 4-bit binary parallel adder IC 7483 and AND/OR gates

Apparatus:

1. Trainer board 1no

2. IC 7483 ,7408,7432,7486 each 1no
3. Regulated Power Supply 1no
4. Connecting wires

Pin Diagram of 7483:

Circuit Diagram:
a) Controllable Binary Parallel Adder/Sub tractor

Fig.4.1 Binary Parallel adder & Sub tractor Circuit

b) BCD Adder Circuit Diagram:

Fig 4.2 BCD adder Circuit diagram

Theory:
4-bit Binary Parallel Adder
IC7483 is a 4-bit full adder. It has 16 pins, out of which 4 are used as inputs A, another 4 as inputs B. The
sum is available in 4 pins. There is Carry –in, Carry-out pins.Fig15.1 shows pin diagram.
• A input -10, 8, 3, 1
• B input - 11,7, 4, 16
• Sum - 9, 6 ,2, 15
• Carry-in -13
• Carry –out – 14
• Vcc -5
• GND -12
In the controllable binary parallel adder and Subtractor circuit is controlled by the control input ‘M’. If
M=0 the parallel adder will perform the addition operation for the given two inputs and if M=1 the parallel
adder will perform the subtraction operation for the given two inputs

Full Adder:
A full Adder should be able to add 2 binary digits plus a carry from the preceding addition. Therefore it must
have three inputs. The output however is the sum and carry.
The Boolean expressions are
Sum - A  B  C
Carry - AB+BC+AC
The difference of A& B input.

BCD Adder:
The 4-bit binary adder IC7483 can be used to perform the addition of BCD numbers. In this, if the 4 bit sum
output is not valid BCD digit or if carry C3 is generated then decimal 6 (110 binary) is to be added to the sum
to get the correct result. Fig shows a 1 –digit BCD adder. BCD address can be cascaded to add numbers with
several digits long by connecting the carry - out of a stage to the carry –in of the next stage.
Procedure:
a) Full Adder/ Subtractor
1. Connect the circuit as shown in the fig.4. 1
2. Connect a 4-bit word (say 0101) to A input & other word (say 0110) to B.
3. Set M to 0. So that it will function as an Adder. Connect the output of Adder S to LED
display to observe the output
4. Find the output in S and carry out. The answer should be the sum of A and B inputs ( in this case
sum=1011)
 5. Try for other combinations
6. Set M to 1 so that the circuit function as 4 – bit Subtarctor
7. Find the output in S & borrow out. The answer should be 0101.
8. Tabulate the results in table.

b) For BCD Adder:

1. Connect the circuit in trainer kit as per the circuit diagram shown in fig 4. 2.
2. Apply input A and input B
3. Check the output of S0, S1, S2, S3, for different values of A and B.
4. Tabulate the readings in table

Observations:
M=0 M=1 BCD adder
S.No A B
Sum Carry Difference Borrow Sum Carry

Precautions:
1. Circuit must be connected without loose connection and with proper ground connections.
2. Make sure that power supply should not exceed more than +5V

Results:
The Arithmetic Circuits 4-bit binary parallel Adder & Sub tractors, BCD Adder are verified
practically.

Discussion Questions:

1. Construct a Full adder from Two half adders

2. Differentiate between serial adder, Parallel adder and Carry look adhead adder.
3. What is a controlled inverter?
4. Design a full Subtractor with NOR gates only and form the Truth Table.
5. Design the Half Adder and Full adder with NAN D gates only.
6. Design a BCD Subtractor circuit using 9’s & 10’s complements.
7. Design a 1’s and 2’s complement circuits to get true magnitude output.
 Structured enquiry-1

VOLTAGE SERIES FEEDBACK AMPLIFIER

AIM: To design a Voltage Series feedback amplifier circuit using FET and to determine the
mid-band gain and bandwidth, with and without feedback.

1. CRO
2. Power Supply
3. Function Generator
4. Breadboard, Transistors, Resistors and Capacitors
5. Decade Resistance Box and Connecting wires.

CIRCUIT DIAGRAM:

Fig.1 Voltage series feedback amplifier

S.N Frequency Vo Vof AV1=V0/VI AVf=V0f/VI Gain in dB Gain in dB
(V) (V) 20 log10 AV1 20 log10 AVf
o.

1 20

2 40

3 60

4 80

5 100

6 500

7 1K

8 5K

9 10K

10 40K

11 80K

12 100K

13 200K

14 400K

15 600K

16 800K

17 1M
Frequency Response Curve:

Graphs are plotted between f on X–axis and 20 log V0/ Vi on Y axis for both with and without
feedback.
 Structured enquiry-2

DESIGN AND DEVELOPMENT OF ASTABLE MULTIVIBRATOR

AIM: To design an Astable multivibrator and study the output waveforms at the Base and Collector
terminals of the Transistors (collector coupled).
APPARATUS:
1. C.R.O
2. Power Supply
3. Transistors, Resistors and Capacitors
4. Connecting wires.

CIRCUIT DIAGRAM :

+Vcc
10V

4.7Kohm R1 R2 4.7Kohm
100Kohm 100Kohm

C1
C2
0.01uF
.002uF
B1 B2 2N2369
T1
2N2369 T2

Astable Multivibrator (fig .1)

DESIGN:
Device ratings: Design equations:
IC (max) = 20mA. RC = ( VCC -- VCE (sat) ) / IC
 > 40 R1= ( Vcc -- VBE (sat) ) / IB
VCC = 10v IB = 1.5 x IB(min)
IC=2.5mA IB(min) = Ic / hFE
Vce sat= 0.2V R1 = R2= R
Calculate C: f = 1 / T = 1 / 1.38RC
PROCEDURE:

1. Make the connections as shown in the circuit diagram of Fig.1

2. Using Oscilloscope note down the waveforms at the points B1, B2, and C1 & C2.
3. Note down the frequency of oscillations of the square wave at the Collector
circuit from CRO.
4. Calculate the theoretical frequency and compare it with the observed value.
5. fth = 1/(0.69R1C1 + 0.69R2C2).

OUTPUT WAVEFORMS:

Output waveforms of Astable Multivibrator

 Structured enquiry-3
DESIGN AND DEVELOPMENT OF MONOSTABLE MULTIVIBRATOR
Aim: Design a Monostable Multivibrator using BJT and study its operation.
APPARATUS:
1. C.R.O
2. Function Generator
3. Power Supply
4. Bread board, Transistors, Resistors, Diode and Capacitors.
5. Connecting wires.
DESIGN:
Device ratings: Design Equations:
IC (max) = 20mAmps Calculate for the time period TP=2.5ms
 > 40 RC= (VCC - VCE(Sat) ) / IC
VCC = 10v RB= (VCC – VBE(Sat) ) / IB
IC=2.5ma IB = 1.5 x IB(min)
Vce sat= 0.3v IB (min) = IC / hFE
TP= 0.69RTCT,
Caculate C :
Input Trigger Frequency (Tg) = TP/ 50
R1 & C1 are components of Differentiator circuit
CIRCUIT DIAGRAM:

Monostable Multivibrator
PROCEDURE:
1. Connect the circuit as shown in the figure 1.
2. Without applying the trigger input check d.c conditions (VBE,VCE).
3. Apply a square wave of 8v(p-p),20KHz as input form a signal generator
4. Observe Vout at the collector of transistor2 and measure pulse width (Tp) .Verify it with theoretical
value of 0.69RC.
5. Note down the waveforms at Collector and Base of transistors T1 and T2. Draw the relevant graphs
with the time scale.

OUTPUT WAVEFORMS: