LOGIC CIRCUITS AND DESIGN

Module 9: Synchronous Sequential Logic

By: Engr. Irene F. Salvador, MSME, MSCpE(AR)

Logic Circuits and Devices
Module 9: Synchronous Sequential Logic
values of their inputs. Sequential circuits, however, act
TOPIC as storage elements and have memory. They can store,
retain, and then retrieve information when needed at a
OUTLINE later time. Our treatment will distinguish sequential
logic from combinational logic.

A. Sequential Circuits
B. Storage Elements
Sequential Circuits
C. Analysis of Clocked Sequential Circuits
D. Design Procedure
A block diagram of a sequential circuit is shown in
E. Finaite State Machines (FSM) figure 1 It consists of a combinational circuit to which
storage elements are connected to form a feedback
path. The storage elements are devices capable of
storing binary information. The binary information
LEARNING stored in these elements at any given time defines the
OBJECTIVES state of the sequential circuit at that time. The
sequential circuit receives binary information from
At the end of this module, you should be able to: external inputs that, together with the present state of
the storage elements, determine the binary value of the
1. Understand and differentiate sequential logic with outputs.
combinational logic circuit.
2. Design of synchronous sequential circuits with an
example.
3. Construction of state diagrams and state tables/
4. Translation of State transition table into excitation
table.
Figure 1: Block Diagram if Sequential Circuit
5. Logic diagram construction of a synchronous se-
quential circuit
These external inputs also determine the condition for
changing the statein the storage elements. The block
diagram demonstrates that the outputs in a sequential
circuit are a function not only of the inputs, but also of
OVERVIEW the present state of the storage elements. The next
state of the storage elements is also a function of
external inputs and the present state. Thus, a
Hand-held devices, cell phones, navigation receivers, sequential circuit is specified by a time sequence of
personal computers, digital cameras, personal media inputs, outputs, and internal states . In contrast, the
players, and virtually all electronic consumer products outputs of combinational logic depend only on the
have the ability to send, receive, store, retrieve, and present values of the inputs.
process information represented in a binary format.
The technology enabling and supporting these devices
is critically dependent on electronic components that Types of Sequential Circuits
can store information, i.e., have memory.

This module examines the operation and control of There are two main types of sequential circuits, and
these devices and their use in circuits and enables you their classification is a function of the timing of their
to better understand what is happening in these devices signals.
when you interact with them. The digital circuits
considered thus far have been combinational—their 1. A synchronous sequential circuit is a system
output depends only and immediately on their whose behavior can be defined from the knowledge
inputs—they have no memory, i.e., dependence on past of its signals at discrete instants of time. employs

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signals that affect the storage elements at only B. Negative Level Triggering- In negative
discrete instants of time. Synchronization is level triggering, the signal with Logic
achieved by a timing device called a clock Low occurs. So, in this triggering, the
generator, which provides a clock signal having the circuit is operated with such type of
form of a periodic train of clock pulses . The clock clock signal. Below is the diagram of
signal is commonly denoted by the identifiers clock Negative level triggering:
and clk . The clock pulses are distributed
throughout the system in such a way that storage
elements are affected only with the arrival of each
pulse. In practice, the clock pulses determine when ii. Edge Triggering
computational activity will occur within the circuit, A. Positive Edge triggering- The
and other signals (external inputs and otherwise) transition from Logic Low to Logic
determine what changes will take place affecting High occurs in the clock signal of
the storage elements and the outputs. positive edge triggering. So, in
positive edge triggering, the circuit is
operated with such type of clock
Clock Signals and Triggering
signal. The diagram of positive edge
triggering is given below.
(a) Clock- A clock signal is a periodic signal in
which ON time and OFF time need not be the
same. When ON time and OFF time of the
clock signal are the same, a square wave is
used to represent the clock signal. Below is a B. Negative Edge triggering- The
diagram which represents the clock signal: transition from Logic High to Logic
low occurs in the clock signal of
negative edge triggering. So, in
negative edge triggering, the circuit is
operated with such type of clock
signal. The diagram of negative edge
triggering is given below.

A clock signal is considered as the square

wave. Sometimes, the signal stays at logic, 2. Asynchronous sequential circuit is a system
either high 5V or low 0V, to an equal amount whose behavior can be defined from the
of time. It repeats with a certain time period, knowledge of its signals at discrete instants of
which will be equal to twice the ’ON time’ or time. The behavior of an asynchronous sequential
’OFF time’. circuit depends upon the input signals at any
(b) Triggering- there are two types of triggering: instant of time and the order in which the inputs
change. The storage elements commonly used in
i. Level triggering
asynchronous sequential circuits are time-delay
The logic High and logic Low are the two
devices. The storage capability of a time-delay
levels in the clock signal. In level
device varies with the time it takes for the signal to
triggering, when the clock pulse is at a
propagate through the device. In practice, the
particular level, only then the circuit is
internal propagation delay of logic gates is of
activated. There are the following types
sufficient duration to produce the needed delay, so
of level triggering:
that actual delay units may not be necessary. In
A. Positive level triggering- in a positive gate-type asynchronous systems, the storage
level triggering, the signal with Logic elements consist of logic gates whose propagation
High occurs. So, in this triggering, the delay provides the required storage. Thus, an
circuit is operated with such type of asynchronous sequential circuit may be regarded
clock signal. Below is the diagram of as a combinational circuit with feedback. Because
positive level triggering: of the feedback among logic gates, an
asynchronous sequential circuit may become
unstable at times. The instability problem imposes
many difficulties on the designer.

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Module 9: Synchronous Sequential Logic

clock pulses.

Storage Elements Storage elements that operate with signal levels (rather
than signal transitions) are referred to as latches; those
controlled by a clock transition are flip-flops. Listed
The storage elements (memory) used in clocked below are types of storage elements.
sequential circuits are called flipflops. A flip-flop is a
binary storage device capable of storing one bit of
information. In a stable state, the output of a flip-flop is 1. The D flip flop is the most important flip flop from
either 0 or 1. A sequential circuit may use many other clocked types. It ensures that at the same
flip-flops to store as many bits as necessary. The block time, both the inputs, i.e., S and R, are never equal
diagram of a synchronous clocked sequential circuit is to 1. The Delay flip-flop is designed using a gated
shown in Figure 2 . The outputs are formed by a SR flip-flop with an inverter connected between the
combinational logic function of the inputs to the circuit inputs allowing for a single input D(Data).
or the values stored in the flip-flops (or both).

This single data input, which is labeled as "D" used

in place of the "Set" input and for the
complementary "Reset" input, the inverter is used.
Thus, the level-sensitive D-type or D flip flop is
constructed from a level-sensitive SR flip flop.

Figure 2: Storage Element

The value that is stored in a flip-flop when the clock

pulse occurs is also determined by the inputs to the
circuit or the values presently stored in the flip-flop (or
both). The new value is stored (i.e., the flip-flop is
updated) when a pulse of the clock signal occurs. Prior
to the occurrence of the clock pulse, the combinational
logic forming the next value of the flip-flop must have
reached a stable value. Consequently, the speed at In D flip flop, the single input "D" is referred to as
which the combinational logic circuits operate is the "Data" input. When the data input is set to 1, the
critical. If the clock (synchronizing) pulses arrive at a flip flop would be set, and when it is set to 0, the
regular interval, as shown in the timing diagram in flip flop would change and become reset. The
Figure 2 , the combinational logic must respond to a "CLOCK" or "ENABLE" input is used to avoid this for
change in the state of the flip-flop in time to be updated isolating the data input from the flip flop’s latching
before the next pulse arrives. Propagation delays play circuitry. When the clock input is set to true, the D
an important role in determining the minimum interval input condition is only copied to the output Q.
between clock pulses that will allow the circuit to
operate correctly.

A change in state of the flip-flops is initiated only by a

clock pulse transition—for example, when the value of
the clock signals changes from 0 to 1. When a clock
pulse is not active, the feedback loop between the value
stored in the flip-flop and the value formed at the input
to the flip-flop is effectively broken because the flipflop 2. The SR (Set-Reset) flip-flop is one of the simplest
outputs cannot change even if the outputs of the sequential circuits and consists of two gates
combinational circuit driving their inputs change in connected as shown in Fig. 5.2.1. Notice that the
value. Thus, the transition from one state to the next output of each gate is connected to one of the
occurs only at predetermined intervals dictated by the inputs of the other gate, giving a form of positive

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feedback or ‘cross-coupling’.

The circuit has two active low inputs marked S and

R, ‘NOT’ being indicated by the bar above the letter,
as well as two outputs, Q and Q. Table shows what
happens to the Q and Q outputs when a logic 0 is
applied to either the S or R inputs.
4. The JK Flip-flop is also called a programmable
flip-flop because, using its inputs, J, K, S and R, it
can be made to mimic the action of any of the
other flip-flop types.

As a starting point, assume that both J and K are at

logic 1 and the outputs Q = 0 and Q = 1, this will
cause NAND 1 to be enabled, as it has logic 1 on
two (J and Q) of its three inputs, requiring only a
3. The Clocked SR Flip-flop. By adding two extra logic 1 on its clock input to change its output state
NAND gates, the timing of the output changeover to logic 0. At the same time, NAND 2 is disabled,
after a change of logic states at S and R can be because it only has one of its inputs (K) at logic 1,
controlled by applying a logic 1 pulse to the clock its feedback input is at logic 0 because of the
(CK) input. feedback from Q.

Note that the inputs are now labelled S and R On the arrival of a clock pulse, the output of NAND 1
indicating that the inputs are now ‘high activated’. therefore becomes logic 0, and causes the flip-flop
This is because the two extra NAND gates are to change state so that Q = 1 and Q = 0. This action
disabled while the CK input is low, therefore the enables NAND 2 and disables NAND 1. As this
outputs are completely isolated from the inputs change of state at the outputs occurs however,
and so retain any previous logic state, but when the there is a problem. If the clock pulse is still high, or
CK input is high (during a clock pulse) the input in its thold period when the flip-flop changes state,
NAND gates act as inverters. Then for example, a the output of NAND 2 will instantly go to logic 0
logic 1 applied to S becomes a logic 0 applied to and the flip-flop will reset back to its original state.
the S input of the active low SR flip-flop second This can then set up a situation where the flip-flop
stage circuit. will rapidly oscillate between its two states.

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Logic Circuits and Devices
Module 9: Synchronous Sequential Logic

the sequential circuit. Another algebraic representation

is introduced for specifying the logic diagram of
sequential circuits. Examples are used to illustrate the
various procedures.

State Equation

The behavior of a clocked sequential circuit can be

described algebraically by means of state equations. A
state equation (also called a transition equation )
specifies the next state as a function of the present
state and inputs. Consider the sequential circuit shown.
Analysis of Clocked
Sequential Circuits

Analysis describes what a given circuit will do under

certain operating conditions. The behavior of a clocked
sequential circuit is determined from the inputs, the
outputs, and the state of its flip-flops. The outputs and
the next state are both a function of the inputs and the
present state. The analysis of a sequential circuit
consists of obtaining a table or a diagram for the time State Table
sequence of inputs, outputs, and internal states. It is
also possible to write Boolean expressions that
The state table of a sequential circuit with D -type
describe the behavior of the sequential circuit. These
flip-flops is obtained by the same procedure outlined in
expressions must include the necessary time
the previous example. In general, a sequential circuit
sequence, either directly or indirectly.
with m flipflops and n inputs needs 2m+n rows in the
state table. The binary numbers from 0 through
2m + n − 1 are listed under the present-state and input
columns. The next-state section has m columns, one
for each flip-flop. The binary values for the next state
are derived directly from the state equations. The
output section has as many columns as there are
output variables. Its binary value is derived from the
circuit or from the Boolean function in the same
manner as in a truth table.

A logic diagram is recognized as a clocked sequential

circuit if it includes flip-flops with clock inputs. The
flip-flops may be of any type, and the logic diagram may
or may not include combinational logic gates. In this
section, we introduce an algebraic representation for
specifying the next-state condition in terms of the It is sometimes convenient to express the state table in
present state and inputs. A state table and state a slightly different form having only three sections:
diagram are then presented to describe the behavior of present state, next state, and output. The input

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conditions are enumerated under the next-state and with additional logic, it can implement the behavior of
output sections. JK and T flip-flops. In fact, designers generally do not
concern themselves with the type of flip-flop; rather,
their focus is on correctly describing the sequential
State Diagram functionality that is to be implemented by the synthesis
tool. Here we will illustrate manual methods using D,
JK, and T flip-flops.
The information available in a state table can be
represented graphically in the form of a state diagram. The procedure for designing synchronous sequential
In this type of diagram, a state is represented by a circuits can be summarized by a list of recommended
circle, and the (clock-triggered) transitions between steps:
states are indicated by directed lines connecting the
circles. The state diagram provides the same
information as the state table and is obtained directly 1. The design of sequential circuit starts with verbal
from state table above. The binary number inside each specifications of the problem
circle identifies the state of the flip-flops. The directed
lines are labeled with two binary numbers separated by
a slash. The input value during the present state is
labeled first, and the number after the slash gives the
output during the present state with the given input.

2. The next step is to derive the state table of the

sequential circuit. A state table represents the
verbal specifications in a tabular form.

For example, the directed line from state 00 to 01 is 3. In certain cases state table can be derived directly
labeled 1/0, meaning that when the sequential circuit is from verbal description of the problem.
in the present state 00 and the input is 1, the output is 0.
4. In other cases, it is easier to first obtain a state
After the next clock cycle, the circuit goes to the next
diagram from the verbal description and then
state, 01. If the input changes to 0, then the output
obtain the state table from the state diagram.
becomes 1, but if the input remains at 1, the output
stays at 0. This information is obtained from the state 5. A state diagram is a graphical representation of the
diagram along the two directed lines emanating from sequential circuit.
the circle with state 01. A directed line connecting a
circle with itself indicates that no change of state 6. In the next step, we proceed by simplifying the
occurs. state table by minimizing the number of states and
obtain a reduced state table.

7. The states in the reduced state table are then

assigned binary-codes. The resulting table is called
Design Procedure output and state transition table.

8. From the state transition table and using flip-flop’s

Design procedures or methodologies specify hardware excitation tables, flip-flops input equations are
that will implement a desired behavior. The design derived. Furthermore, the output equations can
effort for small circuits may be manual, but industry readily be derived as well.
relies on automated synthesis tools for designing
massive integrated circuits. The sequential building 9. Finally, the logic diagram of the sequential circuit is
block used by synthesis tools is the D flip-flop. Together constructed.

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10. An example will be used to illustrate all these

concepts.

Finite State Machines(FSM)

FSMs are an important class of sequential circuits,

which are widely used in control functions. They diagram.
describe a series of states in which the circuit can
reside, and prescribe under what conditions the circuit 2. Determine the state diagram of the given state
can advance from one state to another. Depending on
what state the FSM is in, certain signals are taken high
or low, which serve as the control inputs that drive other
parts of the system, such as enabling or disabling a
combinational element. There are two widely used
models for FSMs, the Mealy model and the Moore
model. Block diagrams of both models are shown:

table.
3. Determine the state table of the given state

In the Mealy model, the output is a function of both the diagram.

present state and the input. In the Moore model, the
output is a function of only the present state. A circuit
may have both types of outputs. The two models of a
sequential circuit are commonly referred to as a finite
state machine, abbreviated FSM. The Mealy model of a REFERENCES
sequential circuit is referred to as a Mealy FSM or
Mealy machine. The Moore model is referred to as a
Moore FSM or Moore machine. References

[1] https://www.tutorialspoint.com/digital_circuits/digital_circuits_q
[2] https://seis.bristol.ac.uk/ eei-
ACTIVITY dbp/courses/ECAD/sequential.htm
[3] https://www.learnabout-
Answer the following problems. Show youe complete electronics.org/Digital/dig53.php
solution.
[4] https://technobyte.org/parallel-adder-subtractor/
[5] https://www.geeksforgeeks.org/4-bit-binary-adder-
1. Derive the state equation of the given circuit subtractor/

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Logic Circuits and Devices
Module 9: Synchronous Sequential Logic

Prepared by:
ENGR. IRENE F. SALVADOR, CPE, MSME, MSCpE(AR)
Faculty, Computer Engineering Department
College of Engineering and Architecture

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