Course Tittle: Digital Electronics and Pulse Techniques

Course Code: CSE 233

Course Teacher

Md. Sadi Rifat

Lecturer

Department of CSE, Prime University

Sequential Circuits
In our previous sections, we learned about combinational circuit and their
working. The combinational circuits have set of outputs, which depends only on
the present combination of inputs. Below is the block diagram of the
synchronous logic circuit.

The sequential circuit is a special type of circuit that has a series of inputs and
outputs. The outputs of the sequential circuits depend on both the combination
of present inputs and previous outputs. The previous output is treated as the
present state. So, the sequential circuit contains the combinational circuit and its
memory storage elements. A sequential circuit doesn't need to always contain a
combinational circuit. So, the sequential circuit can contain only the memory
element.
Difference between the combinational circuits and sequential circuits are given
below:

Combinational Circuits Sequential Circuits

1) The outputs of the combinational The outputs of the sequential circuits

circuit depend only on the present depend on both present inputs and
inputs. present state(previous output).

2) The feedback path is not present The feedback path is present in the
in the combinational circuit. sequential circuits.

3) In combinational circuits, memory In the sequential circuit, memory elements

elements are not required. play an important role and require.

4) The clock signal is not required for The clock signal is required for sequential
combinational circuits. circuits.

5) The combinational circuit is simple It is not simple to design a sequential

to design. circuit.

Types of Sequential Circuits

Asynchronous sequential circuits

The clock signals are not used by the Asynchronous sequential circuits. The
asynchronous circuit is operated through the pulses. So, the changes in the
input can change the state of the circuit. The asynchronous circuits do not use
clock pulses. The internal state is changed when the input variable is changed.
The un-clocked flip-flops or time-delayed are the memory elements of
asynchronous sequential circuits. The asynchronous sequential circuit is similar
to the combinational circuits with feedback.
Synchronous sequential circuits

In synchronous sequential circuits, synchronization of the memory element's

state is done by the clock signal. The output is stored in either flip-flops or
latches(memory devices). The synchronization of the outputs is done with either
only negative edges of the clock signal or only positive edges.

Clock Signal and Triggering

Clock signal

A clock signal is a periodic signal in which ON time and OFF time need not be
the same. When ON time and OFF time of the clock signal are the same, a
square wave is used to represent the clock signal. Below is a diagram which
represents the clock signal:

A clock signal is considered as the square wave. Sometimes, the signal stays at
logic, either high 5V or low 0V, to an equal amount of time. It repeats with a
certain time period, which will be equal to twice the 'ON time' or 'OFF time'.

Types of Triggering

These are two types of triggering in sequential circuits:

Level triggering

The logic High and logic Low are the two levels in the clock signal. In level
triggering, when the clock pulse is at a particular level, only then the circuit is
activated. There are the following types of level triggering:

Positive level triggering

In a positive level triggering, the signal with Logic High occurs. So, in this
triggering, the circuit is operated with such type of clock signal. Below is the
diagram of positive level triggering:
Negative level triggering

In negative level triggering, the signal with Logic Low occurs. So, in this
triggering, the circuit is operated with such type of clock signal. Below is the
diagram of Negative level triggering:

Edge triggering

In clock signal of edge triggering, two types of transitions occur, i.e., transition
either from Logic Low to Logic High or Logic High to Logic Low.

Based on the transitions of the clock signal, there are the following types of
edge triggering:

Positive edge triggering

The transition from Logic Low to Logic High occurs in the clock signal of positive
edge triggering. So, in positive edge triggering, the circuit is operated with such
type of clock signal. The diagram of positive edge triggering is given below.
Negative edge triggering

The transition from Logic High to Logic low occurs in the clock signal of negative
edge triggering. So, in negative edge triggering, the circuit is operated with such
type of clock signal. The diagram of negative edge triggering is given below.

Latches

Latches are basic storage elements that operate with signal levels (rather than
signal transitions). Latches controlled by a clock transition are flip-flops. Latches
are level-sensitive devices. Latches are useful for the design of
the asynchronous sequential circuit. Latches are sequential circuit with two
stable states. These are sensitive to the input voltage applied and does not
depend on the clock pulse. Flip flops that do not use clock pulse are referred to
as latch.

SR (Set-Reset) Latch – They are also known as preset and clear states. The
SR latch forms the basic building blocks of all other types of flip-flops.

SR Latch is a circuit with:

(i) 2 cross-coupled NOR gate or 2 cross-coupled NAND gate.

(ii) 2 input S for SET and R for RESET.

(iii) 2 output Q, Q’.

Q Q’ STATE

1 0 Set

0 1 Reset
Under normal conditions, both the input remains 0. The following is the RS
Latch with NAND gates:

Case-1:S’=R’=1 (S=R=0) –
If Q = 1, Q and R’ inputs for 2nd NAND gate are both 1.

If Q = 0, Q and R’ inputs for 2nd NAND gate are 0 and 1 respectively.

Case-2: S’=0, R’=1 (S=1, R=0) –
As S’=0, the output of 1st NAND gate, Q = 1(SET state). In 2nd NAND gate, as
Q and R’ inputs are 1, Q’=0.

Case-3: S’= 1, R’= 0 (S=0, R=1) –

As R’=0, the output of 2nd NAND gate, Q’ = 1. In 1st NAND gate, as Q and S’
inputs are 1, Q=0(RESET state).

Case-4: S’= R’= 0 (S=R=1) –

When S=R=1, both Q and Q’ becomes 1 which is not allowed. So, the input
condition is prohibited.

The SR Latch using NOR gate is shown below:

Flip Flop-

A Flip Flop is a memory element that is capable of storing one bit of information.

A flip flop has two outputs as shown-

A flip flop can maintain a binary state for an unlimited period of time as long as-

 Power is supplied to the circuit.

 Or until it is directed by an input signal to switch states.

A flip flop is also called as Bistable Multivibrator because it has two stable
states either 0 or 1.

Flip Flops Types-

Flip flops are of different types depending on how their inputs and clock pulses
cause transition between two states.
There are 4 basic types of flip flops-

1. SR Flip Flop

2. JK Flip Flop

3. D Flip Flop

4. T Flip Flop

SR Flip Flop-

 SR flip flop is the simplest type of flip flops.

 It stands for Set Reset flip flop.

 It is a clocked flip flop.

Construction of SR Flip Flop-

There are following two methods for constructing a SR flip flop-

1. By using NOR latch

2. By using NAND latch

1. Construction of SR Flip Flop By Using NOR Latch-

This method of constructing SR Flip Flop uses-

 NOR latch

 Two AND gates

Logic Circuit-

The logic circuit for SR Flip Flop constructed using NOR latch is as shown
below-
2. Construction of SR Flip Flop By Using NAND Latch-

This method of constructing SR Flip Flop uses-

 NAND latch

 Two NAND gates

Logic Circuit-

The logic circuit for SR Flip Flop constructed using NAND latch is as shown
below-

Logic Symbol-

The logic symbol for SR Flip Flop is as shown below-

Truth Table-

The truth table for SR Flip Flop is as shown below-

INPUTS OUTPUTS

Qn Qn+1
S R
(Present State) (Next State)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 Indeterminate

1 1 1 Indeterminate
Truth Table

The above truth table may be reduced as-

INPUTS OUTPUTS REMARKS

Qn
Qn+1
S R (Present States and Conditions
(Next State)
State)

Hold State condition S = R =

0 0 X Qn
0

Reset state condition S = 0 ,

0 1 X 0
R=1

Set state condition S = 1 , R

1 0 X 1
=0

Indeterminate state
1 1 X Indeterminate
condition S = R = 1

Characteristic Equation-

Draw a k map using the above truth table-

From here-

Qn+1 = ( SR + SR’ ) ( Qn + Q’n ) + Qn ( S’R’ + SR’ )

Qn+1 = S + QnR’

Excitation Table-

The excitation table of any flip flop is drawn using its truth table.

What is excitation table?

For a given combination of present state Qn and next state Qn+1, excitation
table tell the inputs required.

Qn Qn+1 S R

0 0 0 X

0 1 1 0

1 0 0 1

1 1 X 0

JK Flip Flop-

JK flip flop is a refined & improved version of SR Flip Flop

that has been introduced to solve the problem of indeterminate state

that occurs in SR flip flop when both the inputs are 1.

In JK flip flop,

 Input J behaves like input S of SR flip flop which was meant to set the flip
flop.

 Input K behaves like input R of SR flip flop which was meant to reset the
flip flop.

Construction of JK Flip Flop-

There are following two methods for constructing a JK flip flop-

1. By using SR flip flop constructed from NOR latch

2. By using SR flip flop constructed from NAND latch

1. Construction of JK Flip Flop By Using SR Flip Flop Constructed From

NOR Latch-

This method of constructing JK Flip Flop uses-

 SR Flip Flop constructed from NOR latch

 Two other connections

Logic Circuit-

The logic circuit for JK Flip Flop constructed using SR Flip Flop constructed
from NOR latch is as shown below-

2. Construction of JK Flip Flop By Using SR Flip Flop Constructed From

NAND Latch-

This method of constructing JK Flip Flop uses-

 SR Flip Flop constructed from NAND latch

 Two other connections

Logic Circuit-

The logic circuit for JK Flip Flop constructed using SR Flip Flop constructed
from NAND latch is as shown below-
Logic Symbol-

The logic symbol for JK Flip Flop is as shown below-

Truth Table-

The truth table for JK Flip Flop is as shown below-

INPUTS OUTPUTS

Qn Qn+1
J K
(Present State) (Next State)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0
 Truth Table

The above truth table may be reduced as-

INPUTS OUTPUTS REMARKS

Qn Qn+1 States and

J K
(Present State) (Next State) Conditions

Hold State condition J

0 0 X Qn
=K=0

Reset state condition J

0 1 X 0
=0,K=1

Set state condition J =

1 0 X 1
1,K=0

Toggle state condition

1 1 X Q’n
J=K=1

Characteristic Equation-

Draw a k map using the above truth table-

 From here-

Qn+1 = Q’n (JK + JK’) + Qn (J’K’ + JK’)

Qn+1 = Q’nJ + QnK’

Excitation Table-

The excitation table of any flip flop is drawn using its truth table.

What is excitation table?

For a given combination of present state Qn and next state Qn+1, excitation table tell the inputs
required.

Qn Qn+1 S R

0 0 0 X

0 1 1 X

1 0 X 1

1 1 X 0

SR Flip Flop Vs JK Flip Flop-

Both JK flip flop and SR flip flop are functionally same.

The only difference between them is-

 In JK flip flop, indeterminate state does not occur.

 In JK flip flop, instead of indeterminate state, the present state toggles.

 In other words, the present state gets inverted when both the inputs are 1.
D Flip Flop

In SR NAND Gate Bistable circuit, the undefined input condition of SET = "0"
and RESET = "0" is forbidden. It is the drawback of the SR flip flop. This state:

1. Override the feedback latching action.

2. Force both outputs to be 1.

3. Lose the control by the input, which first goes to 1, and the other input
remains "0" by which the resulting state of the latch is controlled.

We need an inverter to prevent this from happening. We connect the inverter

between the Set and Reset inputs for producing another type of flip flop circuit
called D flip flop, Delay flip flop, D-type Bistable, D-type flip flop.

The D flip flop is the most important flip flop from other clocked types. It ensures
that at the same time, both the inputs, i.e., S and R, are never equal to 1. The
Delay flip-flop is designed using a gated SR flip-flop with an inverter connected
between the inputs allowing for a single input D(Data).

This single data input, which is labeled as "D" used in place of the "Set" input
and for the complementary "Reset" input, the inverter is used. Thus, the level-
sensitive D-type or D flip flop is constructed from a level-sensitive SR flip flop.

So, here S=D and R= ~D(complement of D)

Block Diagram

Circuit Diagram
We know that the SR flip-flop requires two inputs, i.e., one to "SET" the output
and another to "RESET" the output. By using an inverter, we can set and reset
the outputs with only one input as now the two input signals complement each
other. In SR flip flop, when both the inputs are 0, that state is no longer possible.
It is an ambiguity that is removed by the complement in D-flip flop.

In D flip flop, the single input "D" is referred to as the "Data" input. When the
data input is set to 1, the flip flop would be set, and when it is set to 0, the flip
flop would change and become reset. However, this would be pointless since
the output of the flip flop would always change on every pulse applied to this
data input.

The "CLOCK" or "ENABLE" input is used to avoid this for isolating the data input
from the flip flop's latching circuitry. When the clock input is set to true, the D
input condition is only copied to the output Q. This forms the basis of another
sequential device referred to as D Flip Flop.

When the clock input is set to 1, the "set" and "reset" inputs of the flip-flop are
both set to 1. So it will not change the state and store the data present on its
output before the clock transition occurred. In simple words, the output is
"latched" at either 0 or 1.

Truth Table for the D-type Flip Flop

Symbols ↓ and ↑ indicates the direction of the clock pulse. D-type flip flop
assumed these symbols as edge-triggers.
T Flip Flop

In T flip flop, "T" defines the term "Toggle". In SR Flip Flop, we provide only a
single input called "Toggle" or "Trigger" input to avoid an intermediate state
occurrence. Now, this flip-flop work as a Toggle switch. The next output state is
changed with the complement of the present state output. This process is
known as "Toggling"'.

We can construct the "T Flip Flop" by making changes in the "JK Flip Flop". The
"T Flip Flop" has only one input, which is constructed by connecting the input
of JK flip flop. This single input is called T. In simple words, we can construct
the "T Flip Flop" by converting a "JK Flip Flop". Sometimes the "T Flip Flop" is
referred to as single input "JK Flip Flop".

Block diagram of the "T-Flip Flop" is given where T defines the "Toggle input",
and CLK defines the clock signal input.

T Flip Flop Circuit

There are the following two methods which are used to form the "T Flip Flop":

o By connecting the output feedback to the input in "SR Flips Flop".

o We pass the output that we get after performing the XOR operation of T
and QPREV output as the D input in D Flip Flop.
Construction

The "T Flip Flop" is designed by passing the AND gate's output as input to
the NOR gate of the "SR Flip Flop". The inputs of the "AND" gates, the present
output state Q, and its complement Q' are sent back to each AND gate. The
toggle input is passed to the AND gates as input. These gates are connected to
the Clock (CLK) signal. In the "T Flip Flop", a pulse train of narrow triggers are
passed as the toggle input, which changes the flip flop's output state. The circuit
diagram of the "T Flip Flop" using "SR Flip Flop" is given below:

The "T Flip Flop" is formed using the "D Flip Flop". In D flip - flop, the output
after performing the XOR operation of the T input with the output "QPREV" is
passed as the D input. The logical circuit of the "T-Flip Flop" using the "D Flip
Flop" is given below:

The simplest construction of a D Flip Flop is with JK Flip Flop. Both the inputs of
the "JK Flip Flop" are connected as a single input T. Below is the logical circuit
of the T Flip Flop" which is formed from the "JK Flip Flop":
Truth Table of T Flip Flop

The upper NAND gate is enabled, and the lower NAND gate is disabled when
the output Q To is set to 0. make the flip flop in "set state(Q=1)", the trigger
passes the S input in the flip flop.

The upper NAND gate is disabled, and the lower NAND gate is enabled when
the output Q is set to 1. The trigger passes the R input in the flip flop to make
the flip flop in the reset state(Q=0).

Operations of T-Flip Flop

The next sate of the T flip flop is similar to the current state when the T input is
set to false or 0.

o If toggle input is set to 0 and the present state is also 0, the next state will
be 0.

o If toggle input is set to 0 and the present state is 1, the next state will be
1.
The next state of the flip flop is opposite to the current state when the toggle
input is set to 1.

o If toggle input is set to 1 and the present state is 0, the next state will be
1.

o If toggle input is set to 1 and the present state is 1, the next state will be
0.

The "T Flip Flop" is toggled when the set and reset inputs alternatively changed
by the incoming trigger. The "T Flip Flop" requires two triggers to complete a full
cycle of the output waveform. The frequency of the output produced by the "T
Flip Flop" is half of the input frequency. The "T Flip Flop" works as the
"Frequency Divider Circuit."

In "T Flip Flop", the state at an applied trigger pulse is defined only when the
previous state is defined. It is the main drawback of the "T Flip Flop".

The "T flip flop" can be designed from "JK Flip Flop", "SR Flip Flop", and "D Flip
Flop" because the "T Flip Flop" is not available as ICs. The block diagram of "T
Flip Flop" using "JK Flip Flop" is given below:
Master-Slave JK Flip Flop

In "JK Flip Flop", when both the inputs and CLK set to 1 for a long time, then Q
output toggle until the CLK is 1. Thus, the uncertain or unreliable output
produces. This problem is referred to as a race-round condition in JK flip-flop
and avoided by ensuring that the CLK set to 1 only for a very short time.

Explanation

The master-slave flip flop is constructed by combining two JK flip flops. These
flip flops are connected in a series configuration. In these two flip flops, the 1st
flip flop work as "master", called the master flip flop, and the 2nd work as a
"slave", called slave flip flop. The master-slave flip flop is designed in such a
way that the output of the "master" flip flop is passed to both the inputs of the
"slave" flip flop. The output of the "slave" flip flop is passed to inputs of the
master flip flop.

In "master-slave flip flop", apart from these two flip flops, an inverter or NOT
gate is also used. For passing the inverted clock pulse to the "slave" flip flop, the
inverter is connected to the clock's pulse. In simple words, when CP set to false
for "master", then CP is set to true for "slave", and when CP set to true for
"master", then CP is set to false for "slave".
Working:

o When the clock pulse is true, the slave flip flop will be in the isolated state,
and the system's state may be affected by the J and K inputs. The
"slave" remains isolated until the CP is 1. When the CP set to 0, the
master flip-flop passes the information to the slave flip flop to obtain the
output.

o The master flip flop responds first from the slave because the master flip
flop is the positive level trigger, and the slave flip flop is the negative level
trigger.

o The output Q'=1 of the master flip flop is passed to the slave flip flop as
an input K when the input J set to 0 and K set to 1. The clock forces the
slave flip flop to work as reset, and then the slave copies the master flip
flop.

o When J=1, and K=0, the output Q=1 is passed to the J input of the slave.
The clock's negative transition sets the slave and copies the master.

o The master flip flop toggles on the clock's positive transition when the
inputs J and K set to 1. At that time, the slave flip flop toggles on the
clock's negative transition.

o The flip flop will be disabled, and Q remains unchanged when both the
inputs of the JK flip flop set to 0.
Timing Diagram of a Master Flip Flop:

o When the clock pulse set to 1, the output of the master flip flop will be
one until the clock input remains 0.

o When the clock pulse becomes high again, then the master's output is 0,
which will be set to 1 when the clock becomes one again.

o The master flip flop is operational when the clock pulse is 1. The slave's
output remains 0 until the clock is not set to 0 because the slave flip flop
is not operational.

o The slave flip flop is operational when the clock pulse is 0. The output of
the master remains one until the clock is not set to 0 again.

o Toggling occurs during the entire process because the output changes
once in the cycle.
Counter in Digital Electronics

A counter is a digital circuit that can be used to keep track of the number of
events or clock cycles that have occurred. Counters can be classified into
different types based on their counting sequence and the number of bits they
can count. Some common types of counters include binary counters, decade
counters, and up/down counters.

A binary counter is a type of counter that counts in binary, and the number of
bits it uses determines its maximum count. For example, a 4-bit binary counter
can count up to 15 (in decimal), and a 8-bit binary counter can count up to 255
(in decimal).

A decade counter is a type of counter that counts in decimal, and it has 10

states. Decade counters are often used in digital displays, where they can be
used to drive the digits of a 7-segment display.

An up/down counter is a type of counter that can count up or down, depending

on the control signals. Up/down counters are often used in digital systems
where both counting up and down are required.

In digital electronics, counters are often implemented using flip-flops, and they
play a crucial role in many digital systems, such as timers, digital clocks, and
frequency counters.
Register in Digital Electronics

A register in digital electronics is a group of flip-flops that can be used to store

binary data. Registers are often used to hold intermediate results in digital
systems, or to store the state of a system for a period of time.

The number of flip-flops in a register determines the size of the register, and the
size of the register determines the number of bits that can be stored in the
register. For example, a 4-bit register can store a 4-bit binary number, while an
8-bit register can store an 8-bit binary number.

Registers can be used in many different applications, including memory

systems, arithmetic logic units (ALUs), and input/output (I/O) interfaces. In
addition, registers can be used in combination with counters to form larger
memory systems, such as RAM and ROM.

The operation of a register is typically controlled by a set of control signals, such

as load, shift, and enable signals. The load signal is used to transfer data into
the register, while the shift signal is used to shift the data within the register. The
enable signal is used to control the operation of the register, and it can be used
to enable or disable the register.