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ANALOG ELECTRONIC
CIRCUITS
ICE 2121 [3 1 0 4] [4-Credit]

MUKUND KUMAR MENON

Assistant Professor (Sr. Scale),
Dept. of I&CE,
MIT-MAHE, Manipal

COURSE LEARNING OUTCOMES:

At the end of the course, the students will be able to

CO1 Understand the operation of field effect transistors (FET)

CO2 Analyze various biasing and amplifier topologies of FET

CO3 Realize differential amplifiers using FET

CO4 Analyze frequency response of FET amplifiers

CO5 Design of various feedback amplifiers and power amplifiers

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Chapter 1 MOS Transistor [ 4 Lecture Hours]

• Structure and operation of MOSFET

• I-V Characteristics
• Channel-Length Modulation
• Transconductance
• MOS Device Models
• Large-Signal and Small-Signal Model
• PMOS Transistor.
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https://chemtutorial.wordpress.com/wp-content/uploads/2016/05/images.png?w=604

https://blogmedia.testbook.com/blog/wp-content/uploads/2023/02/depiction-of-s-p-
and-d-atomic-orbitals-8cef44bf.png

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Ref: R. L. Boylestad

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Ref: R. L. Boylestad

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Ref: R. L. Boylestad

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Ref: R. L. Boylestad
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Introduction to Field Effect Transistor (FET)

• Field-Effect Transistor (FET)  3-terminal device  similar to
Bi-polar Junction Transistor (BJT).

• BJT vs FET
BJT  current-controlled device
FET  voltage-controlled device

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Introduction to Field Effect Transistor (FET)

FETs …
• Have a high input impedance than BJTs  an essential
characteristic in the design of linear AC amplifier systems  (i.e.
≈1 to several hundred MΩ) due to the SiO2 layer (… an Insulator)

• Have more temperature stability than BJTs

• Are smaller (usually) than BJTs

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Types of FETs

1. Junction field-effect transistor (JFET)

2. Metal–oxide–semiconductor field-effect transistor (MOSFET), and

3. Metal–semiconductor field-effect transistor (MESFET).

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MOSFET Classification

N- Channel MOSFET P- Channel MOSFET

(NMOS) (PMOS)

Enhancement Enhancement
Type Type

Depletion Type Depletion Type

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MOSFET Structure Analysis: Strategy

Consider a device shown below:

Is it correct to realize that the above setup can act as a capacitor?

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MOSFET Structure Analysis: Strategy Contd..

Now, let us apply a potential difference as shown:

• Positive charge  attracts electrons from the piece of silicon

• Causes a creation of a “channel” of free electrons  between insulator
and Si
• Potentially serving  a good conductive path if the electron density is
sufficiently high.
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MOSFET Structure Analysis: Strategy Contd..

NOTE that the density of electrons in the channel varies

with V1, as evident from Q = CV, where C denotes the

capacitance between the two plates.

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MOSFET Structure Analysis: Strategy Contd..

• Now suppose  an electron flow between left and right is allowed through the
silicon material

• V1  controls the current by adjusting the resistivity of the channel of electrons.

• Flow of charges  primarily via the channel rather than through the entire body of
silicon (due to the path of least resistance)
• This will serve our objective of building a voltage-controlled current source.
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MOSFET Structure : Actual Scenario

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MOSFET Structure : Actual Scenario

• Components - Terminals: Source, Drain and Gate.
• Substrate (p type or n type) and
• SiO2 layer as insulator.

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Fig. N-Channel Depletion type MOSFET 19

Practical Dimensions of MOSFET Design

[Razavi.cls v. 2006]
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MOSFET Classification

N- Channel MOSFET P- Channel MOSFET

(NMOS) (PMOS)

Enhancement Type Enhancement Type

Depletion Type Depletion Type

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P-MOS

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N-MOS

• L represents Channel region length and W represents Channel region width

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• W/L is called the aspect ratio of MOSFET 23

Assuming MOSFET as a simple switch,

OP TYPE MOSFET VGS = VG - Vs VDS

TYPE VGS = 0 VGS = + Vthreshold VGS = - Vthreshold (typ.)
Enhancement N-MOS OFF ON OFF >0
P-MOS OFF ON <0
Depletion N-MOS ON ON OFF >0
P-MOS OFF ON <0
Charge conduction ?? https://www.circuitbread.com/tutorials/nmos-vs-pmos-
and-enhancement-vs-depletion-mode-mosfets
ON Y
OFF N
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Enhancement type N-MOS: Working Principle

• L represents Channel region length and W represents Channel region width

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Enhancement type N-MOS: Working Principle

Case 1: Application of Zero Gate Voltage
Case 2: Both S and D grounded; G supplied with positive voltage
Case 3: VGS > Vt and with a small VDS applied
Case 4: VGS > Vt and VDS increased while keeping VDS < VOV
Case 5: VGS > Vt and VDS ≥ VOV

VOV = VGS – Vt
Effective Voltage (or, Overdrive Voltage)
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Case 1: Application of Zero Gate Voltage

1. With zero voltage applied to the gate, two back-to-back diodes exist in
series between drain and source.
2. These back-to-back diodes prevent current conduction from drain to
source when a voltage VDS is applied.

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Case 2: S and D grounded and Gate supplied with positive voltage

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Case 2: S and D grounded and Gate supplied with positive voltage

• Channel Creation

 Here, both S and D  Grounded  0 V

 VGS  Gate voltage appearing (in effect) between G and S

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Case 2: S and D grounded and Gate supplied with positive voltage

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Case 2: S and D grounded and Gate supplied with positive voltage

• Case 2: Channel Creation
1. + VGS  Free holes in p-substrate  repelled from the channel region
2. These holes  pushed downward into the substrate, leaving behind a carrier-depletion region.
3. Depletion region  populated by the bound -ve charge assoc. w/ acceptor atoms
4. These charges  “uncovered” because the neutralizing holes  been pushed downward
(explained).
5. + VGS  attracts electrons from both the n+ source and drain regions into the channel region
6. When a sufficient number of electrons accumulate near the surface of the substrate under the
gate  an n- region is created  connecting the source and drain regions.
7. With S and D grounded  MOSFET is OFF.
8. If VDS is applied  current flows through this induced n-region (i.e. carried by the mobile
electrons) [Case #3]
9. This induced n-region  forms a channel for current flow from drain to source. [Case #3]
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Case 2: S and D grounded and Gate supplied with positive voltage

• Case 2: Important Points

1) An n-channel MOSFET (NMOS) is formed in a p-type substrate.

2) The channel is created by inverting the substrate surface from p-type to n-type. Hence the
induced channel is also called an inversion layer.
3) The value of VGS at which a sufficient number of mobile electrons accumulate in the channel
region to form a conducting channel is called the threshold voltage and is denoted Vt.
4) Obviously, Vt for an n-channel FET is positive. The value of Vt typically lies in the range of 0.3
V to 1 V.
5) The gate and the channel region of the MOSFET form a parallel-plate capacitor, with the oxide
layer acting as the capacitor dielectric. An electric field thus develops in the vertical direction.
6) It is this electric field that controls the amount of charge in the channel and, in turn, the
current that will flow through the channel when a voltage VDS is applied. That’s why it is
called a “Field-Effect Transistor” (FET).
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Case 2: S and D grounded and Gate supplied with positive voltage

• Case 2: Important Points

 The voltage across the induced parallel-plate capacitor [i.e., the voltage across the metal-oxide]
must exceed a voltage to form a channel.
 The excess of VGS over Vt is termed as the effective voltage or the overdrive voltage (vov) and it is
the parameter that determines the charge in the channel.
 Oxide capacitance, COX , is the capacitance of the parallel-plate capacitor per unit gate area (in
units of F/m2), given by  𝝐
𝑪𝒐𝒙 = 𝒐𝒙 , where 𝝐𝒐𝒙 is the permittivity of SiO2
𝒕𝒐𝒙

 One can express the magnitude of the total electron charge in the channel by  𝑸 = 𝑪𝒐𝒙 𝑾𝑳 𝒗𝑶𝑽
where,
 Total capacitance between gate and channel is given by:
C = Cox . (WL)
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Case 3: VGS > Vt and with a small VDS applied

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Case 3: VGS > Vt and with a small VDS applied

 The voltage VDS causes a current ID to flow through the induced n channel.
Current is carried by free electrons travelling from source to drain. Thus, the
current in the channel, ID, will be from drain to source.
Calculation of Drain Current ID
Charge per unit channel length:

Electric field established by VDS :

Because of E, electrons drift towards Drain with a velocity:

where μn is the mobility of electrons at surface of channel

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Case 3: VGS > Vt and with a small VDS applied

iD = [Charge per unit channel length] x [Electron Drift velocity]

Thus, for small VDS the channel behaves as a linear resistance whose
value is controlled by the overdrive voltage which in turn is
determined by VGS

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Case 3: VGS > Vt and with a small VDS applied

The conductance gDS of the channel (from D to S):

MOSFET Transconductance parameter, kn

Process Transconductance parameter, 𝒌𝒏

𝒌𝒏 = 𝝁𝒏 𝑪𝒐𝒙 

Linear resistance of channel,

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Case 3: VGS > Vt and with a small VDS applied

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Case 3: VGS > Vt and with a small VDS applied

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Case 3: VGS > Vt and with a small VDS applied

For increasing VG
VG  constant
VD  constant

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Case 3: VGS > Vt and with a small VDS applied

ID – VDS characteristics for MOS as a resistor

• Resistance is infinite when VGS is less than VT and decreases as VGS goes
beyond VT
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Case 3: VGS > Vt and with a small VDS applied

For different channel lengths

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Case 3: VGS > Vt and with a small VDS applied

For different oxide thicknesses, tOX

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Case 3: VGS > Vt and with a small VDS applied

For different oxide width, W

C = Cox . (WL)
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Case 3: VGS > Vt and with a small VDS applied

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Case 4: VGS > Vt and VDS increased while keeping VDS < VOV

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Case 4: VGS > Vt and VDS increased while keeping VDS < VOV
 Here, VGS = Vt + Vov at the source end
 VGD = VGS – VDS = Vt + Vov – VDS at drain end
Voltage drop along the channel
 Thus, voltage towards the drain decreases along the length
from source to drain.
 Since the channel depth depends on this voltage, the
channel is no longer of uniform depth (as in Case #3).
 i.e. Channel is deepest at the source end and shallowest at
the drain end.
 Charge in the tapered channel  proportional to the
𝟏
channel cross-sectional area  to 𝑽𝒐𝒗 + 𝑽𝒐𝒗 − 𝑽𝑫𝑺 ] ,
𝟐
 The relationship between ID and VDS can be given by
replacing VOV by VOV – ½ VDS:

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Case 5: VGS > Vt and VDS ≥ VOV

 VDS = VOV  VGD = Vt  Channel depth at
drain end reduces to zero (theoretically).
 The zero depth of the channel at the drain
end gives rise to the term channel pinch-off.
 Increasing VDS beyond VOV  no effect on the
channel shape and charge
 The current through the channel remains
constant at the value reached for VDS = VOV
 The drain current thus saturates at the value
found by substituting VDS by VOV

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Case 5: VGS > Vt and VDS ≥ VOV

 Thus, at saturation, drain current

 The Voltage VDS at which saturation occurs is:

 Both the current through the channel and the voltage drop across it remain constant in saturation.
 The ID – VDS curve can be divided into two regions, the non-pinched off region called Triode region and
the saturation region.
 For saturation, the drain current can be finally modelled as:

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Case 5: VGS > Vt and VDS ≥ VOV

ID – VDS characteristics when VGS > Vt

Case #5

Case #4

Case #3

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Summary: Enhancement mode NMOS

https://www.mks.com/n/mosfet-physics
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P-MOS Structure

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P-MOS Structure
• The structure is similar to that of the NMOS device except that here the substrate is n type and the source
and the drain regions are p+ type.

• To induce a channel for current flow between source and drain, a negative voltage is applied to the gate.

• The condition for establishing the p channel is:

• Alternatively,

• Process transconductance parameter for the PMOS device:

• The transistor transconductance parameter:

• With voltages reversed, working is similar to NMOS.

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Circuit Symbols of MOSFET: Type I

Enhancement type MOSFET Symbols Depletion type MOSFET Symbols

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Circuit Symbols of MOSFET: Type II [Simplified]

Simplified versions of Symbols  Simplified versions of Symbols 

N- channel Enhancement type MOSFET Symbols P- channel Enhancement type MOSFET Symbols

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Current-Voltage Characteristics
• These characteristics can be measured at DC or at low frequencies and thus are called static characteristics.

ID-VDS Characteristics of enhancement type NMOS

--------------------------------------------------------------------

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Current-Voltage Characteristics
• These characteristics can be measured at DC or at low frequencies and thus are called static
characteristics.

ID-VGS Characteristics of enhancement type NMOS operating in saturation region

---------------------------------------------------------------------------------------------------------

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Current-Voltage Characteristics : Summary

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Current-Voltage Characteristics
Important point to note

• From the characteristics, MOSFET  in the saturation region as a voltage-controlled

current source

• Note that the current source is ideal, with an infinite output resistance representing

the independence of ID from VDS during saturation.

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Large signal model of MOSFET

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Example Problem 1
• Consider an NMOS transistor design for which tox = 8 nm, 𝛆𝐨𝐱 = 𝟑. 𝟒𝟓 × 𝟏𝟎 𝟏𝟏 𝐅/𝐦, μn = 450
cm2/V⋅ s, and Vt = 0.7 V.

a) If for the above MOSFET, (W/L) = 8 μm Ú 0.8 μm, calculate the values of overdrive voltage, VGS
and minimum value of VDS required to operate the transistor in saturation with DC current ID =
100 μA.
b) For the same device, find overdrive voltage and VGS required to cause the device to operate as a
1000 Ω resistor for very small VDS.
Solution:

First, let’s find 𝑘

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Example Problem 1
• Consider an NMOS transistor design for which tox = 8 nm, 𝛆𝐨𝐱 = 𝟑. 𝟒𝟓 × 𝟏𝟎 𝟏𝟏 𝐅/𝐦, μn = 450
cm2/V⋅ s, and Vt = 0.7 V.

a) If for the above MOSFET, (W/L) = 8 μm Ú 0.8 μm, calculate the values of overdrive voltage, VGS
and minimum value of VDS required to operate the transistor in saturation with DC current ID =
100 μA.
b) For the same device, find overdrive voltage and VGS required to cause the device to operate as a
1000 Ω resistor for very small VDS.
Solution:

Next, for the device to be in saturation region,

Since ID is 100 μA,

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Example Problem 1
• Consider an NMOS transistor design for which tox = 8 nm, 𝛆𝐨𝐱 = 𝟑. 𝟒𝟓 × 𝟏𝟎 𝟏𝟏 𝐅/𝐦, μn = 450
cm2/V⋅ s, and Vt = 0.7 V.

a) If for the above MOSFET, (W/L) = 8 μm Ú 0.8 μm, calculate the values of overdrive voltage, VGS
and minimum value of VDS required to operate the transistor in saturation with DC current ID =
100 μA.
b) For the same device, find overdrive voltage and VGS required to cause the device to operate as a
1000 Ω resistor for very small VDS.
Solution:

Thus, as per operation

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Example Problem 1
• Consider an NMOS transistor design for which tox = 8 nm, 𝛆𝐨𝐱 = 𝟑. 𝟒𝟓 × 𝟏𝟎 𝟏𝟏 𝐅/𝐦, μn = 450
cm2/V⋅ s, and Vt = 0.7 V.

a) If for the above MOSFET, (W/L) = 8 μm Ú 0.8 μm, calculate the values of overdrive voltage, VGS
and minimum value of VDS required to operate the transistor in saturation with DC current ID =
100 μA.
b) For the same device, find overdrive voltage and VGS required to cause the device to operate as a
1000 Ω resistor for very small VDS.
Solution:

Now, for the device in triode region with small VDS

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Channel Length Modulation

• A change in the drain-to-source voltage (VDS) causes a zero change in ID, which implies that the
incremental resistance looking into the drain of a saturated MOSFET is infinite. But that’s the ideal
picture.
• It is based on the premise that once the channel is pinched off at the drain end, further increases in VDS
has no effect on the channel’s shape.
• Practically, as VDS is increased, the channel pinch-off point is moved slightly away from the drain,
toward the source.
• We note that the voltage across the channel remains constant at VOV, and the additional voltage applied
to the drain appears as a voltage drop across the narrow depletion region between the end of the
channel and the drain region.

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Channel Length Modulation

• This voltage accelerates the electrons that reach the drain end of the channel and sweeps them
across the depletion region into the drain.
• However, with depletion-layer widening, the channel length is in effect reduced, from L to L - ∆L, a
phenomenon known as channel-length modulation.
• Now, since ID is inversely proportional to the channel length (L), ID increases with VDS. (Practically)

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Finite Output resistance in saturation

• The channel length modulation effect can be addressed by modifying the ID equation in saturation as:

where λ is a device parameter having the units of reciprocal volts (V-1) and is inversely proportional to L

• The observed linear dependence of ID on VDS in the saturation region is represented by the factor (1 + λ VDS).

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Finite Output resistance in saturation

• We observe that when the straight-line ID–VDS characteristics are extrapolated, they intercept the VDS axis at
the point, VDS = −VA, where VA is a positive voltage.
• From the previous eqn, we see that ID = 0 at VDS = -1/ λ which follows: 𝑉 = where VA is usually
λ
referred to as the Early voltage, after J. M. Early, who discovered a similar phenomenon for the BJT.
• Thus, for a given VGS, a change ΔVDS yields a corresponding change ΔID in the drain current ID. It follows that
the output resistance of the current source representing ID in saturation is no longer infinite.

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Finite Output resistance in saturation

• One can modify the equivalent circuit (Large signal model) as shown below:

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Finite Output resistance in saturation

Finite output resistance is defined as:

which can be re-written as:

where ID is the drain current without channel-length modulation

with channel-length modulation

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MOS Transconductance (gm)

• As a voltage-controlled current source, a MOS transistor can be characterized by its transconductance:

• This quantity serves as a measure of the “strength” of the device: a higher value corresponds to a greater
change in the drain current for a given change in VGS.

• For saturation region,

(1)

• Replacing (VGS - VTH) in terms of ID we get: [Using ID eq. for saturation]

(2)
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MOS Transconductance (gm)

Another equation holds true if we divide eq. (1) by ID equation in saturation

(3)

Various dependencies of gm : Summary Table

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MOS Transconductance : Review Question

• For a MOSFET operating in saturation, how do gm and VGS − VTH change if both W/L and ID are
doubled?

Solution:

1. From transconductance eq. (2), clearly gm gets doubled.

2. Overdrive voltage remains constant.

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Body Effect
• In the MOS designs so far, it is assumed that both the source and the substrate (also called the “body”)
are tied to ground.
• However, this condition need not hold in all circuits. For example, if the source terminal rises to a
positive voltage while the substrate is at zero, then the source-substrate junction remains reverse-biased
and the device still operates properly.
• Consider the case below:

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Body Effect
• The source terminal is tied to a potential VS with respect to ground while the substrate is grounded
through a p+ contact. The voltage difference between the source and the substrate (the body) is denoted
by VSB.
• As the source-substrate potential difference departs from zero, the threshold voltage of the device
changes.
• Specifically, as the source becomes more positive with respect to the substrate, VTH increases. This
phenomenon is called “body effect”.

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Body Effect: An Equivalent scenario of PMOS

transistor
• The PMOS transistor equations are written in a way that emphasizes physical intuition and avoids the
confusion of negative signs.
• Thus, while Vtp is by convention negative, we use |Vtp| , and the voltages VSG and VSD are positive.
• Accordingly, the Drain current (iD) equation in saturation region (with channel length modulation) is
given by:

where λ and VA are by convention negative, so we take modulus to make them positive.

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Current-Voltage Characteristics for PMOS

Summary

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PMOS transistor Problem

• In the circuit of Fig. shown below, determine the region of operation of M1 as V1 goes from VDD to zero.
Assume VDD = 2.5 V and |VTH| = 0.5V.

Analysis:
1. For V1 = VDD, VSG = 0 and M1 is off.
2. As V1 falls and approaches from 2.5 V to VDD − |VTH| = 2 V, VSG > Vtp , turning the device on.
3. At this point,VG = +2 V while VD = +1 V; that means VSD > Vov i.e., M1 is saturated.
4. When V1 = 0.5 V, M1 is at the edge of triode region, As V1 goes below 0.5 V, the transistor enters the triode
region further.
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DC Analysis of MOSFET
Problem 1:
For the MOSFET circuit shown, determine
the values of RD and RS, so that the transistor
operates at ID = 0.4 mA and VD = +0.5 V.
The NMOS transistor has Vt = 0.7 V, μnCox =
100 μA/V2, L = 1 μm, and W = 32 μm.
Neglect the channel-length modulation effect
(i.e., assume that λ = 0).

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DC Analysis of MOSFET
Problem 1: For the MOSFET circuit shown, determine the values of RD and RS, so that the transistor operates at
ID = 0.4 mA and VD = +0.5 V. The NMOS transistor has Vt = 0.7 V, μnCox = 100 μA/V2, L = 1 μm, and W = 32
μm. Neglect the channel-length modulation effect (i.e., assume that λ = 0).

Solution:

To establish a dc voltage of +0.5 V at the drain, applying KVL, we must

select RD as follows:

What’s the region of operation of this NMOS transistor?

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DC Analysis of MOSFET
Problem 1: For the MOSFET circuit shown, determine the values of RD and RS, so that the transistor operates at
ID = 0.4 mA and VD = +0.5 V. The NMOS transistor has Vt = 0.7 V, μnCox = 100 μA/V2, L = 1 μm, and W = 32
μm. Neglect the channel-length modulation effect (i.e., assume that λ = 0).

Solution:

We can see that VG = 0 V (Grounded) and VD = 0.5 V

Analysis: For saturation  we know that VDS > VGS – Vt , or, VDS > VOV

Here, VD > VG  VD > VG – Vt

So, it can be concluded that the NMOS transistor is in saturation

The current ID therefore is,  VOV = 0.5 V

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DC Analysis of MOSFET
Problem 1: For the MOSFET circuit shown, determine the values of RD and RS, so that the transistor operates at
ID = 0.4 mA and VD = +0.5 V. The NMOS transistor has Vt = 0.7 V, μnCox = 100 μA/V2, L = 1 μm, and W = 32
μm. Neglect the channel-length modulation effect (i.e., assume that λ = 0).

Solution: Therefore,

VGS = VG – VS= 0 – VS = 1.2 V which implies VS = – 1.2

V
RS can be determined by applying KVL as:

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DC Analysis of MOSFET
Problem 2: For the MOSFET circuit
shown, determine the value of RD to
establish a drain voltage of 0.1 V.

The NMOS transistor has Vtn = 1 V,

𝑘 =1 . Neglect the channel-
length modulation effect (i.e., assume
that λ = 0).

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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit
shown, determine the values of ID and
terminal voltages VS and VD.

The NMOS transistor has Vtn = 1 V,

𝑘 =1 . Neglect the channel-
length modulation effect (i.e., assume
that λ = 0).

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DC Analysis of MOSFET
Problem 2: For the MOSFET circuit shown, determine the value of RD to establish a drain voltage of 0.1 V.
The NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume
that λ = 0).

Solution:
What is the region of operation of this MOSFET ?
Analysis: Here, VS = 0 V, VG = VDD = 5 V , VD = 0.1 V that means VDS = 0.1 V < 5 (VGS) – 1 (Vt)

So, the transistor is in Triode region implying the current ID is given by:

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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit shown, determine the values of ID and terminal voltages VS and VD. The
NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume that λ
= 0).

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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit shown, determine the values of ID and terminal voltages VS and VD. The
NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume that λ
= 0).

Solution: Since the gate current is zero, the voltage at the gate is simply determined by the voltage divider
formed by the two 10-MΩ resistors,

Analysis:
• With this positive voltage at the gate, the NMOS transistor will be turned on, So, it cannot be in cut-off
region.
• We do not know, however, whether the transistor will be operating in the saturation region or in the
triode region.
• We shall assume saturation-region operation, solve the problem and check for it’s validity later on.

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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit shown, determine the values of ID and terminal voltages VS and VD. The
NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume that λ
= 0).

Solution: VG = 5V and VS = 6 ID , hence VGS = 5 – 6 ID

Considering saturation region,

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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit shown, determine the values of ID and terminal voltages VS and VD. The
NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume that λ
= 0).

Solution: Solving the quadratic equation, we get two values of ID , which are 0.89 mA and 0.5 mA

Analysis:
• If ID = 0.89 mA, then what is VS ?
VS = 6 ID = 6 x 0.89 mA = 5.34 V

Do you think this value of VS is possible?

• If VS = 5.34 V, then VGS = 5 – 5.34 < Vtn which will take the device to cut-off, but
we have discarded this case before.
• Hence, this value of VS is unacceptable and so ID = 0.89 mA must be discarded
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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit shown, determine the values of ID and terminal voltages VS and VD. The
NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume that λ
= 0).

Solution: So, the correct value of ID appears to be 0.5 mA

For this case,

Validity check: VD > VG – Vtn , so the transistor is indeed in saturation.

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DC Analysis of MOSFET
Problem 3: For the MOSFET circuit shown, determine the values of ID and terminal voltages VS and VD. The
NMOS transistor has Vtn = 1 V, 𝑘 =1 . Neglect the channel-length modulation effect (i.e., assume that λ
= 0).

Solution: Let us first identify the node voltages and associated network equations

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MOS Device models: Intro

• Based on the study of MOS I-V characteristics, we consider two models that can be used
in circuit analysis and design, namely Large Signal Model and Small signal model.
• Large Signal Model is based on the DC analysis of the MOS Transistor which is used to
check the region of operation of MOS. It is also applicable for biasing (to be discussed
later).
• If the bias currents and voltages of a MOSFET are only slightly disturbed by signals, the
nonlinear, large-signal models can be reduced to linear, small-signal representations. In
such scenarios we use small signal model.

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Comparison of BJT and MOSFET

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MOS Large Signal Model

• In the saturation region, the transistor acts as a voltage-controlled current source, lending itself to the model
shown in Fig. (a). Fig. (b) still represents voltage-controlled current source in triode region but in (c) it
represents voltage controlled resistor
• In all three cases, the gate remains an open circuit to represent the zero gate current.

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MOS Small Signal Model

• Viewing the transistor as a voltage controlled current source, we draw the basic model as in Fig. (a), where
iD = gmvGS and the gate remains open.

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MOS Small Signal Model

• To represent channel-length modulation, i.e., variation of iD with vDS, we add a resistor as: [Fig. (b)]

• Since channel-length modulation is relatively small,

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MOSFET Structural Details

• To allow current flow through the silicon material, two contacts are attached to the substrate through two
heavily-doped n-type regions because direct connection of metal to the substrate would not produce a good
“ohmic” contact. These two terminals are called “source” (S) and “drain” (D) to indicate that the former can
provide charge carriers and the latter can absorb them.

• Called the “gate” (G), the top conductive plate resides on a thin dielectric (insulator) layer, which itself is
deposited on the underlying p-type silicon “substrate.”

• n+  called source/drain “diffusion,” referring to a fabrication method used in the early days of
microelectronics

• The device is symmetric with respect to S and D; i.e., depending on the voltages applied to the device, either
of these two terminals can drain the charge carriers from the other.

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Case 1: Application of Zero Gate Voltage

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MOSFET: Introductory points

• Acronym stands for Metal Oxide Semiconductor Field Effect Transistor.

• It is a Voltage controlled device.

• MOSFETs have higher input impedance than BJTs due to SiO2 layer (Insulator).

• The MOSFET category is further broken down into depletion and enhancement types.

• The MOSFET transistor has become one of the most important devices used in the design
and construction of integrated circuits for digital computers. Its thermal stability and other
general characteristics make it extremely popular in computer circuit design.

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Current-Voltage Characteristics: Review Question

• Sketch the ID -VG and ID-VD characteristics for (a) different channel lengths, and (b) different oxide
thicknesses.

Solution: (a)

 As the channel length increases, so does the on-resistance. The drain current begins with lesser values as the
channel length increases.
 Similarly, ID exhibits a smaller slope as a function of VD

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Current-Voltage Characteristics: Review Question

• Sketch the ID -VG and ID-VD characteristics for (a) different channel lengths, and (b) different oxide
thicknesses.

Solution: (b)

 As oxide thickness increases, the capacitance between the gate and the silicon substrate decreases.
 Thus, from Q = CV, we note that a given voltage results in less charge on the gate and hence a lower electron
density in the channel.
 Consequently, the device suffers from a higher on-resistance, producing less drain current for a given gate voltage
or drain voltage

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Velocity Saturation
• At high electric fields, carrier mobility degrades, eventually leading to a constant velocity (vsat).
• Owing to their very short channels (e.g., 0.1 μm), modern MOS devices experience velocity saturation even
with drain-source voltages as low as 1 V. As a result, the I/V characteristics no longer follow the square-law
behavior.
• We can write ID equation as:
• Thus, ID shows linear dependence on VGS – VTH and no dependence on L
• Also, transconductance, gm can be written as:

• Thus, gm is independent of L and ID.

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Thank You
End of Unit I

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