UNIT: 1 &2 (Assignment)
Part A. Short Answer Questions
1. Write Verilog code for a 2-input OR gate using gate-level modeling.
2. What is the difference between wire and reg in Verilog? Give one example for each.
3. Write a Verilog always block to describe a D latch.
4. Write Verilog code for a half-subtractor using behavioral modeling.
5. Define RTL design. Why is it important in the design hierarchy?
6. What is the difference between a primitive and a user-defined primitive in Verilog?
7. Give one difference between functional verification and synthesis.
8. Write Verilog code for a 2-input AND gate using gate-level modeling.
9. What is the difference between #5 a = b; and a = #5 b; in Verilog?
10. Explain the difference between intra-assignment delay and inter-assignment delay
with examples.
Part B: Medium Answer Questions
1. Write behavioral Verilog code for a 4:1 multiplexer using the case statement.
2. Explain the importance of blocking (=) and non-blocking (<=) assignments with a
Verilog example showing incorrect and correct modeling of a sequential circuit.
3. Write Verilog code for a simple finite state machine (FSM) with two states: IDLE and
RUN.
4. What are gate-level primitives in Verilog? Demonstrate with Verilog code for a 2-
input XOR gate.
5. Write Verilog code for a 2-bit binary counter using behavioral modeling and explain
its operation.
6. Explain the key features that make Verilog suitable for digital circuit design
compared to traditional schematic methods.
7. What are gate-level primitives in Verilog? Demonstrate with an example circuit (like
a half-adder).
8. Describe the role of functional verification in the design flow. Why is it important
before synthesis?
9. Explain building blocks of Verilog design. Discuss modules, ports, and instantiation
briefly with an example.
10. Explain the difference between Verilog operators and operands. Classify operators
and give an example for unary and binary operands.
11. What is zero-delay (#0) in Verilog and when is it used?
12. What is a testbench in Verilog? Explain its importance.
13. Write Verilog code for a 2-state FSM (IDLE and RUN). The FSM enters RUN when
start=1 and returns to IDLE when stop=1.
14. What are the main components of a Verilog testbench? Write a simple testbench for
a 2-input AND gate.
15. Design a finite state machine that outputs HIGH whenever the binary input received so far is
divisible by 3. Draw the state diagram and state table.
16. Show the state diagram and state transition table for a modulo-4 counter FSM.
Part C: Long Answer Questions
1. Explain the role of functional verification in the design flow. Write a Verilog
testbench for a 2:1 multiplexer and explain how simulation validates the design.
2. What are user-defined primitives (UDP)? Write Verilog code for a UDP-based 2-input
NAND gate and explain its structure.
3. Discuss system and logic design abstractions. For each abstraction level (behavioral,
RTL, gate), write one Verilog code example of a half adder.
4. Explain the synthesis process in the digital design flow. Write Verilog RTL code for a
4-bit register with synchronous reset and discuss how it is synthesized into
hardware.
5. Explain the complete digital design flow in VLSI/HDL design. Discuss the role of RTL
design, functional verification, and synthesis with a neat diagram.
6. What are procedural blocks in Verilog? Explain initial and always blocks with
examples, highlighting their importance in modeling.
7. Differentiate between blocking and non-blocking assignments in Verilog. Explain
with suitable code examples showing execution order and race conditions.
8. Explain the different types of timing control in Verilog.
9. Compare blocking and non-blocking assignments with respect to timing control.
Write Verilog codes showing race conditions caused by = and how <= resolves them.
10. Write a Verilog code to implement a pulse generator where the output goes high for
10 time units after every 50 time units. Explain how timing control is applied.
11. Write Verilog code for a traffic light controller FSM (RED → GREEN → YELLOW) and
explain the state transition diagram and RTL implementation.
12. Compare Mealy and Moore FSMs with suitable examples. Write Verilog code (and
explain FSM diagram) for a Mealy machine that outputs 1 whenever two consecutive
1’s are detected in the input.
13. Write Verilog code for a vending machine FSM that dispenses an item after receiving
15 units (coin inputs of 5 and 10). Write a testbench to verify the design.
14. Draw the state diagram and Verilog code for a sequence detector that detects “1101” using
a FSM.
15. Explain compiler directives in Verilog. Discuss commonly used directives such as
`define, `include, `timescale with examples of their usage.
