EC792 HPCA

More combinational circuit examples

Combinational circuits
 As a set of interconnected components
◦ Structure
 As a set of concurrent assignment statements
◦ dataflow
 As a set of sequential statements
◦ behaviour

Jan 2025 HPCA 2

Dept of E&C, NITK Surathkal 1

 EC792 HPCA

Combinational circuits
Include all variables read in the always statement in the event list

always @(b) synthesizes to a AND gate

c = a & b; functional mismatch

A variable declared within an always statement holds a temporary

value and does not necessarily infer a unique wire in hardware
• If/case statement generates hardware that is conditionally controlled.
• When a variable is not assigned in all branches of an if/case statement
then a latch is inferred in synthesis

always @(a,b)
If a=0, previous value of c is retained using latch
if (a)
c = b+1;

Jan 2025 HPCA 3

Combinational circuits
 Ensure that outputs are defined for all possible input
combinations
◦ Set all outputs to default values during initialisation and
subsequently override them
 If a variable is used before it is assigned in an
incompletely specified conditional statement then latch
is inferred
 Avoid combinational logic feedback loops (A<=A+B) as
it leads to asynchronous loops which is not supported
in synthesis

Jan 2025 HPCA 4

Dept of E&C, NITK Surathkal 2

 EC792 HPCA

Count the number of 1s in a 8 bit number

module ones_count(
input [7:0] data,
output reg [4:0] count );
assign count = data[0] + data[1]+ data[2] + data[3] + data[4] +
data[5] + data[6]+ data[7] ;
endmodule

module ones_count(input [7:0] data, output reg [4:0] count);

integer k;
always @(data)
begin
count = 0;
for (k=0; k < 8; k=k+1)
count = count + data[k];
end
endmodule

Jan 2025 HPCA 5

Count the number of 1s in a 8 bit number

module count1_4(data,count);
input [3:0] data; output reg [2:0] count;
always @(data)
case (data)
1, 2, 4, 8 : count = 1;
3, 5, 6, 9, 10, 12 : count =2;
7, 11, 12, 13, 14 : count =3;
15 : count =4;
default : count = 0;
endcase;
endmodule
module ones_count(
input [7:0] data,
output reg [4:0] count );
wire [2:0] count1, count2;
count1_4 u1 (data[7:4],count1),
u2 (data[3:0],count2);
assign count = count1 + count2;
endmodule
Jan 2025 HPCA 6

Dept of E&C, NITK Surathkal 3

 EC792 HPCA

Delays
 Inter statement delay
◦ statements execution is delayed
sum = a^b;
#4 t1 = a & cin;
 Intra statement delay
◦ Delay between RHS computation and LHS assignment
sum = # 3 a^b;

Jan 2025 HPCA 7

Test bench

Dept of E&C, NITK Surathkal 4

 EC792 HPCA

Testbench

Generate test stimulus (waveform generation)

Apply this stimulus to module under test and collect output responses
Compare output responses with desired values

Jan 2025 HPCA 9

Option 1
module fulladder_tb;
reg pa, pb, pcin;
wire psum, pcout;
// instantiate the fulladder module
fulladder uut(pa, pb, pcin, psum, pcout);
initial
begin: blk_only_once
reg [3:0] pa1;

for (pa1=0; pa1 < 8; pa1 = pa1+1)

begin Testbench
{pa, pb, pcin} <= pa1;
#50;
end
end UUT
endmodule i/p
o/p

Jan 2025 HPCA 10

Dept of E&C, NITK Surathkal 5

 EC792 HPCA

Stimulus generation

initial
begin
A=0; B=0; // t=0
#10 A=1; // t=10
#20 A=0; B=1; // t=30
end

initial
begin
D = 3’b000; // t=0
repeat (7);
#10 D = D +3’b001; // D gets incremented by1 7times every 10 time units
end

Jan 2025 HPCA 11

Stimulus generation
initial initial
begin begin
reset = 0; reset = 0;
#100 reset =1; reset = #100 1;
#80 reset =0; reset = #80 0;
#30 reset =1; reset = #30 1;
end end

reset

100 180 210

Jan 2025 HPCA 12

Dept of E&C, NITK Surathkal 6

 EC792 HPCA

Repetitive patterns
parameter RPT_DELAY=35;
integer counter; time counter
always 0 0
begin 7 25
counter =0; 9 5
#7 counter =25; 17 10
#2 counter =5; 23 15
#8 counter =10; 58 0
#6 counter =15; 65 25
#RPT_DELAY; ……
end

Jan 2025 HPCA 13

Clock
module gen_clk(output reg clk)
parameter t_PERIOD =10;

initial
clk =0;

always
#(t_PERIOD/2) clk = ~clk;
end module

Jan 2025 HPCA 14

Dept of E&C, NITK Surathkal 7

 EC792 HPCA

Stimulus module

module test_module_name;
// declare local reg and wire identifiers
// Instantiate the design module under test
// Specify a stopwatch, using $finish to stop simulation
// Generate stimulus using initial and always statements
// Display the output response (text or graphics or both)
endmodule;

Jan 2025 HPCA 15

System tasks and functions

 Display tasks
 Display and write tasks
◦ task_name(format1, arg_list1, format2, arg_list2 ….)
◦ task_name
 $display, $displayb $displayh $displayo (EOL character at end)
 $write, $writeb, $writeh, $writeo (No EOL character at end)
◦ format
 %h, %d, %o, %b, %c, %s, %t …
◦ executed at the time statement is encountered
 Strobe tasks
◦ $strobe, $strobeb, $strobeh, $strobeo
◦ strobe task displays simulation data at end of the time step
 Monitor tasks
◦ $monitor, $monitorb, $monitorh, $monitoro
◦ monitors specified arguments continuously ; whenever there is a change in
value in an argument in the list the entire argument list is displayed

Jan 2025 HPCA 16

Dept of E&C, NITK Surathkal 8

 EC792 HPCA

`timescale 1ns / 1ps module mux_2to1_df(input a0, a1, sel, output

module t_mux_2to1; mout);
wire t_muxout; assign mout = (sel)?a1:a0;
reg t_A0, t_A1; endmodule
reg t_select;
parameter stop_time = 50;
mux_2to1_df u1 (t_A0, t_A1, t_select, t_muxout);
initial #stop_time $finish;
initial
begin
t_select = 1; t_A0 = 1; t_A1 = 0;
#10 t_A0 = 0; t_A1 = 1;
#10 t_select = 0;
#10 t_A0 = 1; t_A1 = 0;
end

initial
begin
//$display(" time Select A1 A0 mux_out");
$monitor("time =", $time, "select = %b A1 = %b A0 = %b mux_out = %b",
t_select, t_A1, t_A0, t_muxout);
end
endmodule
Jan 2025 HPCA 17

File I/O tasks

 Opening and closing files
◦ integer file_pointer = $fopen(file_name, mode)
◦ $fclose(file_pointer)
◦ mode
 r, rb – open file for reading at beginning of file
 w, wb - open file for writing at beginning of file; create if it does not
exist
 a, ab - open file for writing at end of file; create if it does not exist
 r+, r+b, rb+ - open file for reading and writing at beginning of file
 w+, w+b, wb+ - open file for reading and writing at beginning of file;
create if it does not exist
 a+, a+b, ab+ - open file for reading and writing at end of file; create if
it does not exist
 b – binary files

Jan 2025 HPCA 18

Dept of E&C, NITK Surathkal 9

 EC792 HPCA

File I/O tasks

 Writing to file
◦ fdisplay, fwrite, fmonitor, fflush
◦ first argument is file pointer, then list of pairs of format
specifications followed by argument list
 Reading from a text file
◦ $readmemb, $readmemh
 reg [0:3] rx_mem [0:63];
 initial
 readmemb(“rx.vec”, rx_mem)
◦ $fread, $fgetc, $fgets, $fscanf ….

Jan 2025 HPCA 19

Test vectors from a text file

module add3_tb;
parameter BITS =11, WORDS=2;
reg [1:BITS] vmem [1:WORDS];
reg [2:0] a, b, sum_ex; test.vec
reg cin, cout_ex;
integer j;
wire [2:0] sum;
01001001000
wire cout; 01001111100

adder3bit uut (a,b,cin,sum,cout)

initial
begin
$readmemb(“test.vec”,vmem);
for (j=1; j <=WORDS; j=j+1)
begin
{a, b, cin, sum_ex, cout_ex } <= vmem[j];
#10; // wait for circuit output to settle
if ((sum !=sum_ex) || (cout !=cout_ex))
$display (“** mismatch on vector %b **”, vmem[j]);
else
$display (“No mismatch on vector %b”, vmem[j]);
end
end
endmodule
Jan 2025 HPCA 20

Dept of E&C, NITK Surathkal 10

 EC792 HPCA

Writing output to a text file

module add3_tb2;
parameter BITS =11, WORDS=2;
reg [1:BITS] vmem [1:WORDS];
reg [2:0] a, b, sum_ex;
reg cin, cout_ex;
integer j;
wire [2:0] sum;
wire cout;
adder3bit uut (a,b,cin,sum,cout)
initial
begin: init_blk
integer resp_out_file;
resp_out_file = $fopen(“resp.out”,”w”);
$readmemb(“test.vec”,vmem);
for (j=1; j <=WORDS; j=j+1)
begin
{a, b, cin, sum_ex, cout_ex } <= vmem[j];
#10; // wait for circuit output to settle
if ((sum !=sum_ex) || (cout !=cout_ex))
$display (“** mismatch on vector %b **”, vmem[j]);
else
$display (“No mismatch on vector %b”, vmem[j]);
$fdisplay(resp_out_file,”input=%b%b%b, output = %b%b”, a, b, cin, sum, cout);
end
$fclose(resp_out_file);
end
endmodule

Jan 2025 HPCA 21

Dept of E&C, NITK Surathkal 11