The instruction code consists of Opcode and Operand
The basic unit of storage in a computer system is: Byte
The Program Counter (PC) contains The address of the next instruction
The Instruction Register (IR) holds: The currently executing instruction
The Accumulator Register (AC) is used for: Temporary storage of intermediate results
The Opcode field in an instruction specifies: The operation to be performed
Which register stores the address of the next instruction to be fetch Program Counter
The Fetch-Decode-Execute cycle is also called: Instruction Cycle
Memory Reference Instructions include Load, Store, Add, Subtract
Control Unit is responsible for: Fetching and executing instructions
A Micro-operation is: A simple operation performed during the execution
Instruction Cycle consists of: Fetch, Decode, Execute
The control unit generates Control signals
The Register Transfer Language (RTL) describes Operations inside the processor
The memory buffer register (MBR) holds: Data read from or written to memory
Interrupts allow The processor to respond to external events
Interrupt vector table (IVT) stores Addresses of interrupt service routines
The Accumulator is part of the ALU
Direct addressing mode means The operand is stored at the memory address given
Indirect addressing mode means The instruction specifies an address where the actu
The Bus structure in a computer system is used for: Data transfer between CPU, memory, and periphera
The function of the ALU is to Perform arithmetic and logic operations
A status register contains Condition flags like Zero, Carry, Overflow
Jump instructions alter: The sequence of program execution
Hardware interrupts are triggered by: External devices
The Instruction Set Architecture (ISA) defines The complete set of machine instructions for a CPU
A Microprogram controls Execution of machine instructions at the lowest leve
Memory Mapped I/O allows I/O devices to share the memory address space
Pipelining is used to Improve CPU performance by executing multiple in
The design of the accumulator logic determines How arithmetic operations are performed
The purpose of an Instruction Decoder is to Decode the instruction and generate control signals
A Microinstruction is: A low-level control signal that executes part of an in
Instruction Pipelining improves Execution speed by overlapping instruction executi
Hardwired control is A fixed control unit with direct hardware implemen
The Microprogram Counter (MPC) is used in: Microprogrammed control units to fetch microinstr
The Memory Address Register (MAR) holds The address of the memory location being accessed
The Memory Data Register (MDR) holds: Data being read from or written to memory
Clock cycles per instruction (CPI) determines: The number of clock cycles required to execute an
Von Neumann Architecture is characterized by: A single memory for both data and instructions
Harvard Architecture is different from Von Neumann Architecture be Has separate memory for data and instructions
Direct Memory Access (DMA) enables Data transfer between memory and I/O devices wit
The Interrupt Service Routine (ISR) is executed when: An interrupt occurs
Stack Pointer (SP) is used to: Keep track of the top of the stack in memory
The Stack in a computer system follows which data structure princi Last In First Out (LIFO)
Polling is a mechanism used to: Continuously check the status of an I/O device
interrupt-driven I/O is better than polling because: It does not waste CPU cycles while waiting
The Condition Code Register (CCR) stores: Status flags from ALU operations
Instruction Format refers to The layout of an instruction, including opcode and o
The Halt (HLT) instruction is used to Stop the execution of the processor
The basic design of a computer system includes Memory, Processor, Input/Output Devices
The primary function of a control unit is to: Direct the operation of the processor
The instruction cycle is made up of which phases? Fetch, Decode, Execute
Microprogramming is a technique used for: Implementing the control unit of a CPU
Opcode in an instruction defines The operation to be performed
Pipelining is used to Improve instruction execution efficiency
The memory access time is defined as: The time taken to fetch data from memory
Multiprocessing refers to: The use of multiple processors to execute multiple
The condition code flags are used to: Store information about the last ALU operation
The MAR (Memory Address Register) holds The address of the location to be accessed in memo
Memory hierarchy is structured as: Registers → Cache → RAM → Hard Disk
RISC (Reduced Instruction Set Computing) is characterized by: A smaller set of simple instructions
The basic unit of computer memory is Byte
Hardwired control unit is Implemented using fixed logic circuits
Interrupts help in: Managing multitasking efficiently
DMA (Direct Memory Access) bypasses the: CPU for faster data transfer
Bus arbitration is necessary to Resolve conflicts in data transfer
The stack pointer (SP) points to The top of the stack
Von Neumann architecture uses A single memory for both data and instructions
The control signals in a CPU are generated by The control unit
Machine language consists of: Binary instructions that the CPU understands
Immediate addressing mode means The operand is directly specified in the instruction
The Halt (HLT) instruction is used to: Stop the CPU until further instructions
The Fetch phase of instruction execution retrieves The instruction from memory
Cache memory is used to Reduce the time needed to access frequently used d
Accumulator-based systems store Intermediate results in a dedicated register
Opcode and Operand
Register
ext instruction The address of the next instru
ing instruction The currently executing instru
Temporary storage of intermediate results
intermediate results
The operation to be performed
InstructionCycle
Instruction Register
Load, Store, Add, Subtract
ng instructions Fetching
A simple and executing
operation instruc during the execution
performed
erformed during the execution cycle
Fetch, Decode, Execute
Control signals
Operations inside the processo
itten to memory Data read from or written to
ond to external events The processor to respond to ex
t service routines Addresses of interrupt service
ALU
The operand is stored at the memory address given
d at the memory address given in the instruction The instruction specifies an address where the actua
ies an address where the actual operand is stored
n CPU, memory, and peripherals Data transfer between CPU, me
nd logic operations Perform arithmetic and logic
ero, Carry, Overflow Condition flags like Zero, Carr
ram execution The sequence of program execu
External devices
The complete set of machine instructions for a CPU
machine instructions for a CPU Execution of machine instructions at the lowest leve
instructions at the lowest level
the memory address space I/O devices
Improve CPU toperformance
share the memo
by executing multiple ins
mance by executing multiple instructions simultaneously How arithmetic operations are performed
ations are performed Decode the instruction and generate control signals
n and generate control signals A low-level control signal that executes part of an ins
gnal that executes part of an instruction
verlapping instruction execution Execution speed by overlapping
ith direct hardware implementation A fixed control unit with dire
ontrol units to fetch microinstructions Microprogrammed control units
emory location being accessed The address of the memory loc
or written to memory Data being read
The number fromcycles
of clock or writrequired to execute an in
cycles required to execute an instruction
both data and instructions A single memory for both data
y for data and instructions Has separate
Data transfer memory
betweenfor data and I/O devices with
memory
n memory and I/O devices without CPU intervention
An interrupt occurs
of the stack in memory Keep track of the top of the st
Last In First Out (LIFO)
he status of an I/O device Continuously check the status o
cycles while waiting It does not waste CPU cycles wh
Status flagsof
The layout from ALU operatio
an instruction, including opcode and op
uction, including opcode and operands
the processor Stop the execution of the proce
nput/Output Devices Memory, Processor, Input/Out
of the processor Direct the operation of the pro
Fetch, Decode, the
Implementing Execute
control unit of a CPU
ntrol unit of a CPU
The operation to be performed
execution efficiency Improve instruction execution
ch data from memory The time taken to fetch data
rocessors to execute multiple tasks The use of multiple processors
out the last ALU operation Store information about the la
cation to be accessed in memory The address of the location to
RAM → Hard Disk Registers → Cache → RAM → Ha
e instructions A smaller set of simple instruct
Bit
xed logic circuits Implemented using fixed logic
g efficiently Managing multitasking efficien
CPU for faster data transfer
Resolve conflicts in data trans
The top of the stack
both data and instructions A single memory for both data
The control unit
hat the CPU understands Binary instructions that the C
ly specified in the instruction The operand is directly specifie
ther instructions Stop the CPU until further inst
The instruction from memory
ed to access frequently used data Reduce the time needed to acce
n a dedicated register Intermediate results in a dedic
yes Address and Data no Opcode and Register
no Bit no Byte
yes The address of the current inno The data being processed
yes The next instruction to execuno The memory address of the next
yes Storing memory addresses no Holding the next instruction
yes The memory address to fetcno The register being used
no Program Counter yes Accumulator
yes Execution Cycle no Processing Cycle
yes Jump, Compare, Load no Input, Output, Halt
yes Performing arithmetic operatno Managing memory access
yes A complex algorithm for arithno A hardware signal generator
yes Decode, Fetch, Store no Load, Store, Execute
yes Data signals no Memory addresses
Yes External memory operations no Network communication
Yes The program counter value no Status flags
yes The CPU to execute instructi no The computer to turn off unused
yes Data for program execution no ALU results
yes Control Unit no I/O Controller
yes The operand is in a register no The operand is fetched from a se
yes The operand is inside the CPUno The instruction directly contain
yes Managing the processor spe no Connecting only input devices
yes Decode instructions no Manage memory operations
yes Memory addresses no I/O device numbers
yes The CPU clock speed no The ALU operation
yes Software commands no Cache memory
yes The physical layout of a mot no Memory speed and size
yes External hardware interfacesno Network communication
yes Memory to be mapped to diffeno The CPU to bypass RAM for fas
yes Increase memory capacity no Control input and output operati
yes How memory locations are ano How data is transferred between
yes Perform arithmetic operatio no Manage memory access
yes A part of the program writtenno A machine instruction executed
yes Memory size in the system no The number of registers in the C
yes A software-based control me no A cache memory management te
yes Memory management no CPU clock cycle control
yes Data to be stored in memory no The program counter value
yes The address of the next instr no The clock cycle count
yes The number of instructions i no The time taken to fetch an instr
yes Separate memory for instructno No memory unit
yes Uses only registers for execuno Does not allow multitasking
yes Memory management in virtuno Control of multiple CPU cores
yes A program starts execution no The CPU is idle
Yes Store ALU operation results no Manage memory-mapped I/O
yes First In First Out (FIFO) no Random Access
yes Transfer data between memono Control the sequence of instruct
yes It executes instructions faste no It reduces power consumption
Yes The address of the next instr no The opcode of the current instru
yes The process of fetching data no The timing of instruction executi
yes Jump to another instruction no Store data in memory
yes Software, Operating System, no Bus, Power Supply, Cooling Sy
yes Perform arithmetic operationno Control I/O devices
yes Read, Write, Execute no Store, Process, Transfer
yes Enhancing memory access spno Managing multitasking in OS
yes The memory address of data no The next instruction to execute
yes Manage cache memory no Reduce memory access time
yes The time required to execute no The time required to store data in
yes Executing a single instructio no Running multiple operating sys
yes Control memory access no Manage cache memory
yes The data to be written into no The next instruction to be execu
yes Hard Disk → RAM → Registerno RAM → Cache → Registers → Har
yes Complex instruction executiono Variable instruction lengths
no Byte yes Word
yes A software-based control unino Used in virtual memory systems
yes Executing instructions fasterno Reducing CPU power consumpti
Yes Bus system to access memoryno Cache memory for I/O operation
yes Improve CPU speed no Manage virtual memory
yes The bottom of the stack no The next instruction in executio
yes Separate memory for data and no Multiple registers for fast execut
yes The ALU no The registers
yes High-level
The operand programming langno
is stored in memory Human-readable assembly langu
yes no
Transfer control to another program The instruction refers to another
yes no Restart execution at a different
yes The operands for execution no The data from an input device
yes Increase the main memory sino Store instructions permanently
yes Instructions in a queue no Data directly in memory
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