CE 2704 - Digital Logic Design

Dr. Ehsan Ali

Assumption University of Thailand
ehsanali@au.edu

Semester 2/2024
Contents

1 Module 4 - Verilog (Part 1) 2

1.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
1.1.1 Learning Outcomes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 History of Hardware Description Languages . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 HDL Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.4 The Modern Digital Design Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.5 Xilinx ISE Design Suite 14.7 (Obsolete) . . . . . . . . . . . . . . . . . . . . . . . . . . 13
1.6 Xilinx Vivado Design Suite 2018.2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
1.7 Verilog Constructs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7.1 Verilog Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
1.7.1.1 Value Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.7.1.2 Net Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1.7.1.3 Variable Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.7.1.4 Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
1.7.1.5 Arrays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
1.7.1.6 Expressing Numbers Using Different Bases . . . . . . . . . . . . . . 21
1.7.1.7 Assigning Between Different Types . . . . . . . . . . . . . . . . . . . 22
1.7.2 The Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
1.7.2.1 Port Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
1.7.2.2 Signal Declarations . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
1.7.2.3 Parameter Declarations . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7.2.4 Compiler Directives . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
1.7.3 Verilog Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7.3.1 Assignment Operator . . . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7.3.2 Bitwise Logical Operators . . . . . . . . . . . . . . . . . . . . . . . . 26
1.7.3.3 Reduction Logic Operators . . . . . . . . . . . . . . . . . . . . . . . 27
1.7.3.4 Boolean Logic Operators . . . . . . . . . . . . . . . . . . . . . . . . 27
1.7.3.5 Relational Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.3.6 Conditional Operators . . . . . . . . . . . . . . . . . . . . . . . . . . 28
1.7.3.7 Concatenation Operator . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3.8 Replication Operator . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3.9 Numerical Operators . . . . . . . . . . . . . . . . . . . . . . . . . . 29
1.7.3.10 Operator Precedence . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
1.8 Modeling Concurrent Functionality in Verilog . . . . . . . . . . . . . . . . . . . . . . . 31
1.8.1 Continuous Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
1.8.2 Continuous Assignment with Logical Operators . . . . . . . . . . . . . . . . . . 32
1.8.3 Continuous Assignment with Conditional Operators . . . . . . . . . . . . . . . 33
1.8.4 Continuous Assignment with Delay . . . . . . . . . . . . . . . . . . . . . . . . 35

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1.9 Structural Design and Hierarchy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.9.1 Lower-Level Module Instantiation . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.9.1.1 Explicit Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . 38
1.9.1.2 Positional Port Mapping . . . . . . . . . . . . . . . . . . . . . . . . . 39
1.9.2 Gate-Level Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
1.9.3 User-Defined Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
1.9.4 Adding Delay to Primitives . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.10 Overview of Simulation Test Benches . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
1.11 Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

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Chapter 1

Module 4 - Verilog (Part 1)

1.1 Introduction
Based on what we have learned so far, there are a few observations about logic design that are apparent.
First, the size of logic circuitry can scale quickly to the point where it is difficult to design by hand.
Second, the process of moving from a high-level description of how a circuit works (e.g., a truth table) to
a form that is ready to be implemented with real circuitry (e.g., a minimized logic diagram) is straight-
forward and well-defined. Both of these observations motivate the use of computer-aided design (CAD)
tools to accomplish logic design.
This week lecture notes introduces hardware description languages (HDLs) as a means to describe
digital circuitry using a text-based language. HDLs provide a means to describe large digital systems
without the need for schematics, which can become impractical in very large designs. HDLs have
evolved to support logic simulation at different levels of abstraction.
This provides designers the ability to begin designing and verifying functionality of large systems
at a high level of abstraction and postpone the details of the circuit implementation until later in the
design cycle. This enables a top-down design approach that is scalable across different logic families.
HDLs have also evolved to support automated synthesis, which allows the CAD tools to take a func-
tional description of a system (e.g., a truth table) and automatically create the gate-level circuitry to be
implemented in real hardware. This allows designers to focus their attention on designing the behavior
of a system and not spend as much time performing the formal logic synthesis steps that were presented
in previous week.
The intent of this week lessons is to introduce HDLs and their use in the modern digital design flow.
We will cover the basics of designing combinational logic in an HDL and also hierarchical design.
There are two dominant hardware description languages in use today:
• VHDL
• Verilog
VHDL stands for very high-speed integrated circuit hardware description language. Verilog is not
an acronym but rather a trade name. The use of these two HDLs is split nearly equally within the digital
design industry. Once one language is learned, it is simple to learn the other language, so the choice of
the HDL to learn first is somewhat arbitrary. In this course, we will use Verilog to learn the concepts of
an HDL. Verilog is more similar to the programming language C and less strict in its type casting than
VHDL.
Verilog is also widely used in custom integrated circuit design so there is a great deal of documen-
tation and examples readily available online (Google Verilog + ’concept you want to learn more about’
and you will find tons of related articles).

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1.1.1 Learning Outcomes
• Describe the role of hardware description languages in modern digital design.

• Describe the fundamentals of design abstraction in modern digital design.

• Describe the modern digital design flow based on hardware description languages.

• Describe the fundamental constructs of Verilog.

• Design a Verilog model for a combinational logic circuit using concurrent modeling techniques
(continuous signal assignment with logical operators and continuous signal assignment with con-
ditional operators).

• Design a Verilog model for a combinational logic circuit using a structural design approach (gate-
level primitives and user-defined primitives).

• Describe the role of a Verilog test bench.

1.2 History of Hardware Description Languages

The invention of the integrated circuit is most commonly credited to two individuals who filed patents
on different variations of the same basic concept within 6 months of each other in 1959. Jack Kilby filed
the first patent on the integrated circuit in February of 1959 titled "Miniaturized Electronic Circuits"
while working for Texas Instruments. Robert Noyce was the second to file a patent on the integrated
circuit in July of 1959 titled "Semiconductor Device and Lead Structure" while at a company he co-
founded called Fairchild Semiconductor. Kilby went on to win the Nobel Prize in Physics in 2000 for
his invention, while Noyce went on to cofound Intel Corporation in 1968 with Gordon Moore. In 1971,
Intel introduced the first single-chip microprocessor using integrated circuit technology, the Intel 4004.
This microprocessor IC contained 2300 transistors. This series of inventions launched the semiconduc-
tor industry, which was the driving force behind the growth of Silicon Valley and led to 40 years of
unprecedented advancement in technology that has impacted every aspect of the modern world.
Gordon Moore, cofounder of Intel, predicted in 1965 that the number of transistors on an integrated
circuit would double every 2 years. This prediction, now known as Moore’s law, has held true since the
invention of the integrated circuit. As the number of transistors on an integrated circuit grew, so did the
size of the design and the functionality that could be implemented. Once the first microprocessor was
invented in 1971, the capability of CAD tools increased rapidly enabling larger designs to be accom-
plished. These larger designs, including newer microprocessors, enabled the CAD tools to become even
more sophisticated and, in turn, yield even larger designs. The rapid expansion of electronic systems
based on digital integrated circuits required that different manufacturers needed to produce designs that
were compatible with each other. The adoption of logic family standards helped manufacturers ensure
their parts would be compatible with other manufacturers at the physical layer (e.g., voltage and current);
however, one challenge that was encountered by the industry was a way to document the complex behav-
ior of larger systems. The use of schematics to document large digital designs became too cumbersome
and difficult to understand by anyone besides the designer. Word descriptions of the behavior were easier
to understand, but even this form of documentation became too voluminous to be effective for the size
of designs that were emerging. Simultaneously there was a need to begin simulating the functionality of
these large systems prior to fabrication to verify accuracy. Due to the complexity of these systems and
the vast potential for design error, it became impractical to verify design accuracy through prototyping.

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 In 1983, the US Department of Defense (DoD) sponsored a program to create a means to document
the behavior of digital systems that could be used across all of its suppliers. This program was motivated
by a lack of adequate documentation for the functionality of application-specific integrated circuits
(ASICs) that were being supplied to the DoD. This lack of documentation was becoming a critical
issue as ASICs would come to the end of their life cycle and need to be replaced. With the lack of a
standardized documentation approach, suppliers had difficulty reproducing equivalent parts to those that
had become obsolete. The DoD contracted three companies (Texas Instruments, IBM, and Intermetrics)
to develop a standardized documentation tool that provided detailed information about both the interface
(i.e., inputs and outputs) and the behavior of digital systems. The new tool was to be implemented in
a format similar to a programming language. Due to the nature of this type of language-based tool, it
was a natural extension of the original project scope to include the ability to simulate the behavior of a
digital system. The simulation capability was desired to span multiple levels of abstraction to provide
maximum flexibility. In 1985, the first version of this tool, called VHDL, was released. In order to gain
widespread adoption and ensure consistency of use across the industry, VHDL was turned over to the
Institute of Electrical and Electronic Engineers (IEEE) for standardization. IEEE is a professional
association that defines a broad range of open technology standards. In 1987, IEEE released the first
industry standard version of VHDL. The release was titled IEEE 1076-1987. Feedback from the initial
version resulted in a major revision of the standard in 1993 titled IEEE 1076-1993. While many minor
revisions have been made to the 1993 release, the 1076-1993 standard contains the vast majority of
VHDL functionality in use today. The most recent VHDL standard is IEEE 1076-2008.
Also in 1983, the Verilog HDL was developed by Automated Integrated Design Systems as a logic
simulation language. The development of Verilog took place completely independent from the VHDL
project. Automated Integrated Design Systems (renamed Gateway Design Automation in 1985) was ac-
quired by CAD tool vendor Cadence Design Systems in 1990. In response to the popularity of Verilog’s
intuitive programming and superior simulation support, and also to stay competitive with the emerging
VHDL standard, Cadence made the Verilog HDL open to the public. IEEE once again developed the
open standard for this HDL and in 1995 released the Verilog standard titled IEEE 1364-1995. This
release has undergone numerous revisions with the most significant occurring in 2001. It is common
to refer to the major releases as "Verilog 1995" and "Verilog 2001" instead of their official standard
numbers.
The development of CAD tools to accomplish automated logic synthesis can be dated back to the
1970s when IBM began developing a series of practical synthesis engines that were used in the design of
their mainframe computers; however, the main advancement in logic synthesis came with the founding of
a company called Synopsis in 1986. Synopsis was the first company to focus on logic synthesis directly
from HDLs. This was a major contribution because designers were already using HDLs to describe and
simulate their digital systems, and now logic synthesis became integrated in the same design flow. Due
to the complexity of synthesizing highly abstract functional descriptions, only lower levels of abstraction
that were thoroughly elaborated were initially able to be synthesized. As CAD tool capability evolved,
synthesis of higher levels of abstraction became possible, but even today not all functionality that can be
described in an HDL can be synthesized. The history of HDLs, their standardization, and the creation
of the associated logic synthesis tools is key to understanding the use and limitations of HDLs. HDLs
were originally designed for documentation and behavioral simulation. Logic synthesis tools were de-
veloped independently and modified later to work with HDLs. This history provides some background
into the most common pitfalls that beginning digital designers encounter, that being that most any type
of behavior can be described and simulated in an HDL, but only a subset of well-described functionality
can be synthesized.
Beginning digital designers are often plagued by issues related to designs that simulate perfectly but
that will not synthesize correctly. In this course, an effort is made to introduce Verilog at a level that

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provides a reasonable amount of abstraction while preserving the ability to be synthesized. Fig. 1.1
shows a time-line of some of the major technology milestones that have occurred in the past 150 years
in the field of digital logic and HDLs.

Figure 1.1: Major milestones in the advancement of digital logic and HDLs.

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1.3 HDL Abstraction
HDLs were originally defined to be able to model behavior at multiple levels of abstraction. Abstraction
is an important concept in engineering design because it allows us to specify how systems will operate
without getting consumed prematurely with implementation details. Also, by removing the details of
the lower-level implementation, simulations can be conducted in reasonable amounts of time to model
the higher-level functionality. If a full computer system was simulated using detailed models for every
MOSFET, it would take an impracticable amount of time to complete. Fig. 1.2 shows a graphical
depiction of the different layers of abstraction in digital system design.

Figure 1.2: Levels of design abstraction.

The highest level of abstraction is the system level. At this level, behavior of a system is described
by stating a set of broad specifications. An example of a design at this level is a specification such as "the

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computer system will perform 10 Tera Floating Point Operations per Second (10 TFLOPS) on double
precision data and consume no more than 100 Watts of power." Notice that these specifications do not
dictate the lower-level details such as the type of logic family or the type of computer architecture to use.
One level down from the system level is the algorithmic level. At this level, the specifications begin
to be broken down into sub-systems, each with an associated behavior that will accomplish a part of the
primary task. At this level, the example computer specifications might be broken down into sub-systems
such as a central processing unit (CPU) to perform the computation and random-access memory (RAM)
to hold the inputs and outputs of the computation.
One level down from the algorithmic level is the register transfer level (RTL). At this level, the
details of how data is moved between and within sub-systems are described in addition to how the data
is manipulated based on system inputs.
One level down from the RTL level is the gate level. At this level, the design is described using basic
gates and registers (or storage elements). The gate level is essentially a schematic (either graphically or
text-based) that contains the components and connections that will implement the functionality from the
above levels of abstraction.
One level down from the gate level is the circuit level. The circuit level describes the operation of
the basic gates and registers using transistors, wires, and other electrical components such as resistors
and capacitors.
Finally, the lowest level of design abstraction is the material level. This level describes how differ-
ent materials are combined and shaped in order to implement the transistors, devices, and wires from the
circuit level.
HDLs are designed to model behavior at all of these levels with the exception of the material level.
While there is some capability to model circuit level behavior such as MOSFETs as ideal switches
and pull-up/pull-down resistors, HDLs are not typically used at the circuit level. Another graphical
depiction of design abstraction is known as the Gajski and Kuhn’s Y-chart. A Y-chart depicts abstrac-
tion across three different design domains: behavioral, structural, and physical. Each of these design
domains contains levels of abstraction (i.e., system, algorithm, RTL, gate, and circuit). An example
Y-chart is shown in Fig. 1.3.
A Y-chart also depicts how the abstraction levels of different design domains are related to each
other. A top-down design flow can be visualized in a Y-chart by spiraling inward in a clockwise direc-
tion. Moving from the behavioral domain to the structural domain is the process of synthesis. Whenever
synthesis is performed, the resulting system should be compared with the prior behavioral description.
This checking is called verification. The process of creating the physical circuitry corresponding to
the structural description is called implementation. The spiral continues down through the levels of
abstraction until the design is implemented at a level that the geometries representing circuit elements
(transistors, wires, etc.) are ready to be fabricated in silicon. Fig. 1.4 shows the top-down design process
depicted as an inward spiral on the Y-chart.

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 Figure 1.3: Y-chart of design abstraction.

The Y-chart represents a formal approach for large digital systems. For large systems that are de-
signed by teams of engineers, it is critical that a formal, top-down design process is followed to eliminate
potentially costly design errors as the implementation is carried out at lower levels of abstraction.
In-class Question 1: Why is abstraction an essential part of engineering design?

1. Without abstraction all schematics would be drawn at the transistor level.

2. Abstraction allows computer programs to aid in the design process.

3. Abstraction allows the details of the implementation to be hidden while the higher-level systems
are designed. Without abstraction, the details of the implementation would overwhelm the de-
signer.

4. Abstraction allows analog circuit designers to include digital blocks in their systems.

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 Figure 1.4: Y-chart illustrating top-down design approach.

1.4 The Modern Digital Design Flow

When performing a smaller design or the design of fully contained sub-systems, the process can be
broken down into individual steps. These steps are shown in Fig. 1.5. This process is given generically
and applies to both classical and modern digital design. The distinction between classical and modern
is that modern digital design uses HDLs and automated CAD tools for simulation, synthesis, place and
route, and verification.

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 Figure 1.5: Generic digital design flow.

This generic design process flow can be used across classical and modern digital design, although
modern digital design allows additional verification at each step using automated CAD tools. Fig. 1.6
shows how this flow is used in the classical design approach of a combinational logic circuit.

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 Figure 1.6: Classical digital design flow.

The modern design flow based on HDLs includes the ability to simulate functionality at each step of
the process. Functional simulations can be performed on the initial behavioral description of the sys-
tem. At each step of the design process, the functionality is described in more detail, ultimately moving
toward the fabrication step. At each level, the detailed information can be included in the simulation to

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verify that the functionality is still correct and that the design is still meeting the original specifications.
Fig. 1.7 shows the modern digital design flow with the inclusion of simulation capability at each step.

Figure 1.7: Modern digital design flow.

In-class Question 2: Why did digital designs move from schematic-entry to text-based HDLs?

1. HDL models could be much larger by describing functionality in text similar to traditional pro-
gramming language.

2. Schematics required sophisticated graphics hardware to display correctly.

3. Schematics symbols became too small as designs became larger.

4. Text was easier to understand by a broader range of engineers.

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1.5 Xilinx ISE Design Suite 14.7 (Obsolete)
Before we get into the details of Verilog HDL, we need a CAD tool for entering our design examples and
practice the concepts we learn in this course. Xilinx is an American technology and semiconductor com-
pany that primarily supplies programmable logic devices. The company is known for inventing the first
commercially viable field-programmable gate array (FPGA) and creating the first fabless manufacturing
model.
It has many products such as FPGAs, Complex Programmable Logic Devices (CPLDs), etc. The
company offers a design suite (IDE, editor, compiler, simulator, etc.) to allow digital logic designers
to enter their design using an HDL language (either Verilog or VHDL) and upload their design into
programmable chips. In this course we use Xilinx ISE Design Suite 14.7 to program a CPLD that we
have in our digital laboratory.
Students can either download the suite from the official website (registration is required) or get a
VirtualBox image from the instructor and use VirtualBox to run the software. Students also need to
obtain a license from Xilinx to ISE the WebPack version of the software. In case of not being able
to obtain the license please contact the instructor for assistance. Note that all PCs in VME laboratory
(VME0808) are equipped with a licensed version of Xilinx ISE Design Suite 14.7. Fig. 1.8 shows the
main window Project Navigator of the ISE Design Suite 14.7.

Figure 1.8: Xilinx ISE Design Suite 14.7 - Project Navigator.

Task 1: Create a new project in Xilinx ISE Design Suite 14.7 - Project Navigator to target the fol-
lowing CPLD device:

• Family: Automotive CoolRunner 2 (This is the board we have in our lab)

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 • Device: XA2C256

• Package: TQ144

• Speed: -7

• Synthesis Tool: XST (VHDL/Verilog)

• Simulator: ISim (VHDL/Verilog)

• Preferred Language Verilog

Design a simple 2-input AND gate and simulate it using the Xilinx ISim simulator.
Answer:
Design file:
Listing 1.1: simple_AND.v
1 module simple_AND (
2 i n p u t A,
3 input B,
4 output F
5 );
6

7 / / What a p p r o a c h ?
8 / / Gate l e v e l approach !
9

10 and and0 ( F , A, B ) ;
11

12 endmodule
Simulation file:
Listing 1.2: test_simple_AND.v
1 ‘ t i m e s c a l e 1 ns / 1 ps
2

3 module t e s t _ s i m p l e _ A N D ;
4 / / Inputs
5 r e g A;
6 reg B;
7

8 / / Outputs
9 wire F ;
10

11 / / I n s t a n t i a t e t h e U n i t Under T e s t (UUT)
12 simple_AND u u t (
13 . A(A) ,
14 . B(B) ,
15 .F(F)
16 );
17

18 i n i t i a l begin
19 / / I n i t i a l i z e Inputs
20 A = 0; B = 0;

15
21 #100; / / Wait 100 n s f o r g l o b a l r e s e t t o f i n i s h
22 A = 0; B = 0 ; #100
23 A = 0; B = 1 ; #100
24 A = 1; B = 0 ; #100
25 A = 1; B = 1 ; #100
26 A = 0; B = 0;
27 / / Add s t i m u l u s h e r e
28 end
29 endmodule
Simulation waveform:

Figure 1.9: Waveform of the AND gate functional simulation in Xilinx ISIM.

1.6 Xilinx Vivado Design Suite 2018.2

Before we get into the details of Verilog HDL, we need a CAD tool for entering our design examples and
practice the concepts we learn in this course. Xilinx is an American technology and semiconductor com-
pany that primarily supplies programmable logic devices. The company is known for inventing the first
commercially viable field-programmable gate array (FPGA) and creating the first fabless manufacturing
model.
AMD announced its acquisition of Xilinx in October 2020, and the deal was completed on February
14, 2022, through an all-stock transaction worth an estimated $60 billion. Xilinx remained a wholly
owned subsidiary of AMD until the brand was phased out in June 2023, with Xilinx’s product lines now
branded under AMD.
The CAD tools are heavily dependent on the manufacturer and tech companies behind them and they
keep evolving. For example, for years people used Xilinx ISE to design and simulate digital circuit until
the company moved to Vivado Design Suite to support newer FPGA IC chips. That is why I have kept
the Xilinx ISE section intact to show you that while the CAD tools themselves self might change, but
the digital logic design fundamentals won’t.
Xilinx has many products such as FPGAs, Complex Programmable Logic Devices (CPLDs), etc.
The company offers a design suite (IDE, editor, compiler, simulator, etc.) to allow digital logic designers
to enter their design using an HDL language (either Verilog or VHDL) and upload their design into
programmable chips. In this course we use Xilinx Vivado Design Suite 2018.2 to program an FPGA
chip that we have in our digital laboratory.
Students can either download the suite from Xilinx Vivado Design Suite Archive - version 2018.2
(registration is required) or copy the setup files from desktop PC at our lab. The setup files are locate
in D:\Basys3 folder. Students do not need to obtain a license from if select WebPack edition of the
software. Note that all PCs in VME laboratory (VME0808) are equipped with a licensed version of

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 Xilinx Vivado Design Suite version 2018.2. Fig. 1.8 shows the main window Project Navigator of the
Xilinx Vivado Design Suite 2018.2.

Figure 1.10: Xilinx Vivado Design Suite, Version: 2018.2

Task 1: Create a new project in Xilinx Vivado Design Suite to target the following FPGA device that
we have in our lab:

• FPGA Development Board: Basys 3

• FPGA Family: Artix-7

• Device: XC7A35T-1CPG236C

• Simulator: ISim (VHDL/Verilog)

• Preferred Language Verilog

Design a simple 2-input AND gate and simulate it using the Xilinx ISim simulator.
Answer:
Design file:
Listing 1.3: simple_AND.v
1 module simple_AND (
2 i n p u t A,
3 input B,
4 output F
5 );
6

7 / / What a p p r o a c h ?
8 / / Gate l e v e l approach !

17
9

10 and and0 ( F , A, B ) ;
11

12 endmodule
Simulation file:
Listing 1.4: test_simple_AND.v
1 ‘ t i m e s c a l e 1 ns / 1 ps
2

3 module t e s t _ s i m p l e _ A N D ;
4 / / Inputs
5 r e g A;
6 reg B;
7

8 / / Outputs
9 wire F ;
10

11 / / I n s t a n t i a t e t h e U n i t Under T e s t (UUT)
12 simple_AND u u t (
13 . A(A) ,
14 . B(B) ,
15 .F(F)
16 );
17

18 i n i t i a l begin
19 / / I n i t i a l i z e Inputs
20 A = 0; B = 0;
21 #100; / / Wait 100 n s f o r g l o b a l r e s e t t o f i n i s h
22 A = 0; B = 0 ; #100
23 A = 0; B = 1 ; #100
24 A = 1; B = 0 ; #100
25 A = 1; B = 1 ; #100
26 A = 0; B = 0;
27 / / Add s t i m u l u s h e r e
28 end
29 endmodule
Simulation waveform:

Figure 1.11: Waveform of the AND gate functional simulation in Xilinx ISIM.

18
1.7 Verilog Constructs
Now we begin looking at the details of Verilog. The original Verilog standard (IEEE 1364) has been
updated numerous times since its creation in 1995. The most significant update occurred in 2001, which
was titled IEEE 1394-2001. In 2005 minor corrections and improvements were added to the standard,
which resulted in IEEE 1394-2005. The constructs described in course reflect the functionality in the
IEEE 1394-2005 standard. The functionality of Verilog (e.g., operators, signal types, functions, etc.)
is defined within the Verilog standard; thus, it is not necessary to explicitly state that a design is using
the IEEE 1394 package because it is inherent in the use of Verilog. This chapter gives an overview of
the basic constructs of Verilog in order to model simple combinational logic circuits and begin gaining
experience with logic simulations.
A Verilog design describes a single system in a single file. The file has the suffix *.v. Within the file,
the system description is contained within a module. The module includes the interface to the system
(i.e., the inputs and outputs) and the description of the behavior. Fig. 1.12 shows a graphical depiction
of a Verilog file.

Figure 1.12: The anatomy of a Verilog file.

Verilog is case sensitive. Also, each Verilog assignment, definition, or declaration is terminated
with a semicolon (;). As such, line wraps are allowed and do not signify the end of an assignment,
definition, or declaration. Line wraps can be used to make Verilog more readable. Comments in Verilog
are supported in two ways. The first way is called a line comment and is preceded with two slashes (i.e.,
//). Everything after the slashes is considered a comment until the end of the line. The second comment
approach is called a block comment and begins with /* and ends with a */. Everything between /*
and */ is considered a comment. A block comment can span multiple lines. All user-defined names in
Verilog must start with an alphabetic letter, not a number. User-defined names are not allowed to be the
same as any Verilog keyword.

1.7.1 Verilog Data Types

In Verilog, every signal, constant, variable, and function must be assigned a data type. The IEEE 1394-
2005 standard provides a variety of pre-defined data types. Some data types are synthesizable, while
others are only for modeling abstract behavior. The following are the most commonly used data types in
the Verilog language.

19
1.7.1.1 Value Set
Verilog supports four basic values that a signal can take on: 0, 1, X, and Z. Most of the pre-defined data
types in Verilog store these values. A description of each value supported is given in Table 1.1:

Value Description
0 A logic zero, or false condition.
1 A logic one, or true condition.
x or X Unknown or uninitialized.
z or Z High impedance, tri-stated, or floating.
Table 1.1: Verilog baisc values.

In Verilog, these values also have an associated strength. The strengths are used to resolve the value
of a signal when it is driven by multiple sources. The names, syntax, and relative strengths are given in
Table 1.2:

Strength Description Strength level

supply1 Supply drive for VCC 7
supply0 Supply drive for VSS , or GND 7
strong1 Strong drive to logic one 6
strong0 Strong drive to logic zero 6
pull1 Medium drive to logic one 5
pull0 Medium drive to logic zero 5
large Large capacitive 4
weak1 Weak drive to logic one 3
weak0 Weak drive to logic zero 3
medium Medium capacitive 2
small Small capacitive 1
highz1 High impedance with weak pull-up to logic one 0
highz0 High impedance with weak pull-down to logic zero 0
Table 1.2: Verilog values’ strength.

When a signal is driven by multiple drivers, it will take on the value of the driver with the highest
strength. If the two drivers have the same strength, the value will be unknown. If the strength is not
specified, it will default to strong drive, or level 6.

1.7.1.2 Net Data Types

Every signal within Verilog must be associated with a data type. A net data type is one that models an
interconnection (aka., a net) between components and can take on the values 0, 1, X, and Z. A signal
with a net data type must be driven at all times and updates its value when the driver value changes. The
most common synthesizable net data type in Verilog is the wire. The type wire will be used throughout
this course. There are also a variety of other more advanced net data types that model complex digital
systems with multiple drivers for the same net. The syntax and description for all Verilog net data types
are given in Table 1.3:

20
 Type Description
wire A simple connection between components.
wor Wired-OR. If multiple drivers, their values are OR’d together.
wand Wired-AND’d. If multiple drivers, their values are AND’d together.
supply0 Used to model the VSS , (GND), power supply (supply strength inherent).
supply1 Used to model the VCC power supply (supply strength inherent).
tri Identical to wire. Used for readability for a net driven by multiple sources.
trior Identical to wor. Used for readability for nets driven by multiple sources.
triand Identical to wand. Used for readability for nets driven by multiple sources.
tri1 Pulls up to logic one when tri-stated.
tri0 Pulls down to logic zero when tri-stated.
trireg Holds last value when tri-stated (capacitance strength inherent).
Table 1.3: Verilog net data types syntax and description.

Each of these net types can also have an associated drive strength. The strength is used in deter-
mining the final value of the net when it is connected to multiple drivers.

1.7.1.3 Variable Data Types

Verilog also contains data types that model storage. These are called variable data types. A variable
data type can take on the values 0, 1, X, and Z but does not have an associated strength. Variable data
types will hold the value assigned to them until their next assignment. The syntax and description for
the Verilog variable data types are given in Table 1.4.

Type Description
reg A variable that models logic storage. Can take on values 0, 1, X, and Z.
integer A 32-bit, 2’s complement variable representing whole numbers between
−2, 147, 483, 64810 and +2, 147, 483, 64710 .
real A 64-bit, floating point variable representing real numbers between
−(2.2 × 10−308 10 ) and +(2.2 × 10308 10 ).
time An unsigned, 64-bit variable taking on values from 010 to +(9.2×1018 ).
realtime same as time. Just used for readability.
Table 1.4: Verilog variable data types.

1.7.1.4 Vectors
In Verilog, a vector is a one-dimensional array of elements. All of the net data types, in addition to the
variable type reg, can be used to form vectors. The syntax for defining a vector is as follows:
1 < t y p e > [ < MSB_index >: < LSB_index > ] v e c t o r _ n a m e
While any range of indices can be used, it is common practice to have the LSB index start at zero.
Example:
1 w i r e [ 7 : 0 ] Sum ; / / T h i s d e f i n e s an 8− b i t v e c t o r c a l l e d "Sum" o f t y p e
2 // wire .
3 / / MSB i s g i v e n t h e i n d e x 7 w h i l e t h e LSB i s g i v e n
4 // the index 0.
5

6 r e g [ 1 5 : 0 ] Q; / / T h i s d e f i n e s a 16− b i t v e c t o r c a l l e d "Q" o f t y p e

21
7 // reg .
Individual bits within the vector can be addressed using their index. Groups of bits can be accessed
using an index range.
1 Sum [ 0 ] ; / / T h i s i s t h e l e a s t s i g n i f i c a n t b i t o f t h e v e c t o r "Sum"
2 // d e f i n e d above .
3 Q [ 1 5 : 8 ] ; / / T h i s i s t h e u p p e r 8− b i t s o f t h e 16− b i t v e c t o r "Q"
4 / / d e f i n e d above .

1.7.1.5 Arrays
An array is a multidimensional array of elements. This can also be thought of as a "vector of vec-
tors". Vectors within the array all have the same dimensions. To declare an array, the element type and
dimensions are defined first followed by the array name and its dimensions. It is common practice to
place the start index of the array on the left side of the ":" when defining its dimensions. The syntax for
the creation of an array is shown below.
1 < e l e m e n t _ t y p e > [ < MSB_index >: < LSB_index > ] a r r a y _ n a m e [ < a r r a y _ s t a r t _ i n d e x >: <
array_end_index >];
Example:
1 r e g [ 7 : 0 ] Mem[ 0 : 4 0 9 5 ] ; / / D e f i n e s an a r r a y o f 4 0 9 6 , 8− b i t v e c t o r s o f t y p e
2 // reg .
3 i n t e g e r A[ 1 : 1 0 0 ] ; / / D e f i n e s an a r r a y o f 100 i n t e g e r s .
When accessing an array, the name of the array is given first, followed by the index of the element.
It is also possible to access an individual bit within an array by adding appending the index of element.
Example:
1 Mem [ 2 ] ; // T h i s i s t h e 3 r d e l e m e n t w i t h i n t h e a r r a y named "Mem " .
2 // T h i s s y n t a x r e p r e s e n t s an 8− b i t v e c t o r o f t y p e r e g .
3 Mem [ 2 ] [ 7 ] ; // T h i s i s t h e MSB o f t h e 3 r d e l e m e n t w i t h i n t h e a r r a y
4 // named "Mem " .
5 // This syntax r e p r e s e n t s a s i n g l e b i t of type reg .
6 A[ 2 ] ; // T h i s i s t h e 2 nd e l e m e n t w i t h i n t h e a r r a y named "A " .
7 // R e c a l l t h a t A was d e c l a r e d w i t h a s t a r t i n g i n d e x o f 1 .
8 // T h i s s y n t a x r e p r e s e n t s a 32− b i t , s i g n e d i n t e g e r .

1.7.1.6 Expressing Numbers Using Different Bases

If a number is simply entered into Verilog without identifying syntax, it is treated as an integer. However,
Verilog supports defining numbers in other bases. Verilog also supports an optional bit size and sign of a
number. When defining the value of arrays, the "_" can be inserted between numerals to improve read-
ability. The "_" is ignored by the Verilog compiler. Values of numbers can be entered in either upper or
lower case (i.e., z or Z, f or F, etc.). The syntax for specifying the base of a number is as follows:
1 < s i z e _ i n _ b i t s > ’ < b a s e >< v a l u e >
Note that specifying the size is optional. If it is omitted, the number will default to a 32-bit vector
with leading zeros added as necessary. The supported bases are as follows (Table 1.5):

22
 Syntax Description
’b Unsigned binary
’o Unsigned octal
’d Unsigned decimal
’h Unsigned hexadecimal
’sb Signed binary
’so Signed octal
’sd Signed decimal
’sh Signed hexadecimal
Table 1.5: Verilog support number bases.

Example:
1 10 / / T h i s i s t r e a t e d a s d e c i m a l 1 0 , which i s a 32− b i t s i g n e d v e c t o r .
2 4 ’ b1111 / / A 4− b i t number w i t h t h e v a l u e 11112 .
3 8 ’ b1011_0000 / / An 8− b i t number w i t h t h e v a l u e 101100002 .
4 8 ’ hFF / / An 8− b i t number w i t h t h e v a l u e 111111112 .
5 8’ hff / / An 8− b i t number w i t h t h e v a l u e 111111112 .
6 6 ’hA / / A 6− b i t number w i t h t h e v a l u e 0010102 . Note t h a t l e a d i n g z e r o s
7 / / were a d d e d t o make t h e v a l u e 6− b i t s .
8 8 ’ d7 / / An 8− b i t number w i t h t h e v a l u e 000001112 .
9 32 ’ d0 / / A 32− b i t number w i t h t h e v a l u e 0000_000016 .
10 ’ b1111 / / A 32− b i t number w i t h t h e v a l u e 0000_000F16 .
11 8 ’ bZ / / An 8− b i t number w i t h t h e v a l u e ZZZZ_ZZZZ .

1.7.1.7 Assigning Between Different Types

Verilog is said to be a weakly typed (or loosely typed) language, meaning that it permits assignments
between different data types. This is as opposed to a strongly typed language (such as VHDL) where
signal assignments are only permitted between like types. The reason Verilog permits assignment be-
tween different types is because it treats all of its types as just group of bits. When assigning between
different types, Verilog will automatically truncate or add leading bits as necessary to make the assign-
ment work. The following examples illustrate how Verilog handles a few assignments between different
types. Assume that a variable called ABC_TB has been declared as type reg[2:0].
Example:
1 ABC_TB = 2 ’ b00 ; / / ABC_TB w i l l b e a s s i g n e d 3 ’ b000 . A l e a d i n g b i t i s
2 / / a u t o m a t i c a l l y added .
3 ABC_TB = 5 ; / / ABC_TB w i l l be a s s i g n e d 3 ’ b101 . The i n t e g e r i s t r u n c a t e d
4 // t o 3− b i t s .
5 ABC_TB = 8 ; / / ABC_TB w i l l be a s s i g n e d 3 ’ b000 . The i n t e g e r i s t r u n c a t e d
6 // t o 3− b i t s .

1.7.2 The Module

All systems in Verilog are encapsulated inside of a module. Modules can include instantiations of lower-
level modules in order to support hierarchical designs. The keywords module and endmodule signify
the beginning and end of the system description. When working on large designs, it is common practice
to place each module in its own file with the same name.

23
1 / / P r e V e r i l o g −2001:
2 module module_name ( p o r t _ l i s t ) ;
3 // port_definitions
4 / / module_items
5 endmodule
6

7 / / V e r i l o g −2001 and a f t e r :
8 module module_name ( p o r t _ l i s t and p o r t _ d e f i n i t i o n s ) ;
9 / / module_items
10 endmodule

1.7.2.1 Port Definitions

The first item within a module is its definition of the inputs and outputs, or ports. Each port needs to
have a user-defined name, a direction, and a type. The user-defined port names are case sensitive and
must begin an alphabetic character. The port directions are declared to be one of the three types: input,
output, and inout. A port can take on any of the previously described data types, but only wires,
registers, and integers are synthesizable. Port names with the same type and direction can be listed on
the same line separated by commas.
There are two different port definition styles supported in Verilog. Prior to the Verilog-2001 release,
the port names were listed within parentheses after the module name. Then within the module, the
directionality and type of the ports were listed. Starting with the Verilog-2001 release, the port di-
rections and types could be included alongside the port names within the parenthesis after the module
name. This approach mimicked more of an ANSCI-C approach to passing inputs/outputs to a system.
In this course, the newer approach to port definition will be used. Example in Fig. 1.13 shows multiple
approaches for defining a module and its ports.

24
 Figure 1.13: Declaring Verilog module ports.

1.7.2.2 Signal Declarations

A signal that is used for internal connections within a system is declared within the module before its first
use. Each signal must be declared by listing its type followed by a user-defined name. Signal names of
like type can be declared on the same line separated with a comma. All of the legal data types described
above can be used for signals; however, only types wire, reg, and integer will synthesize directly.
The syntax for a signal declaration is as follows:
1 < t y p e > name ;
Example:
1 w i r e node1 ; / / d e c l a r e a s i g n a l named " node1 " o f t y p e w i r e
2 r e g Q2 , Q1 , Q0 ; / / d e c l a r e t h r e e s i g n a l s named "Q2 " , "Q1 " , and "Q0 " , a l l o f
3 // type reg
4 w i r e [ 6 3 : 0 ] b u s 1 ; / / d e c l a r e a 64− b i t v e c t o r named " b u s 1 " w i t h a l l b i t s o f
5 // type wire
6 integer i , j ; / / d e c l a r e two i n t e g e r s c a l l e d " i " and " j "
Verilog supports a hierarchical design approach; thus, signal names can be the same within a sub-
system as those at a higher level without conflict. Fig. 1.14 shows an example of legal signal naming in
a hierarchical design.

25
 Figure 1.14: Verilog signals and systems.

1.7.2.3 Parameter Declarations

A parameter, or constant, is useful for representing a quantity that will be used multiple times in the
architecture. The syntax for declaring a parameter is as follows:
1 parameter <type > constant_name = <value >;
Note that the type is optional and can only be integer, time, real, or realtime. If a type
is provided, the parameter will have the same properties as a variable of the same time. If the type is
excluded, the parameter will take on the type of the value assigned to it.
Example:
1 p a r a m e t e r BUS_WIDTH = 6 4 ;
2 p a r a m e t e r NICKEL = 8 ’ b0000_0101 ;
Once declared, the constant name can be used throughout the module. The following example illus-
trates how we can use a constant to define the size of a vector. Notice that since we defined the constant
to be the actual width of the vector (i.e., 32-bits), we need to subtract one from its value when defining
the indices (i.e., [31:0]).
Example:
1 / / I t i s a c c e p t a b l e t o add a " s p a c e " f o r r e a d a b i l i t y
2 w i r e [BUS_WIDTH− 1 : 0 ] BUS_A ;

1.7.2.4 Compiler Directives

A compiler directive provides additional information to the simulation tool on how to interpret the Ver-
ilog model. A compiler directive is placed before the module definition and is preceded with a backtick
(i.e., ‘). Note that this is not an apostrophe. A few of the most commonly used compiler directives are
as follows (Table 1.6):

26
 Syntax Description
‘timescale <unit>,<precision> Defines the timescale of the delay unit and its smallest precision.
‘include <filename> Includes additional files in the compilation.
‘define <macroname> <value> Declares a global constant.
Table 1.6: Verilog compiler directives.

Example:
1 ‘ t i m e s c a l e 1 ns / 1 ps
2 / / D e c l a r e s t h e u n i t of time i s 1 ns with a p r e c i s i o n of 1 ps .
3 / / The p r e c i s i o n i s t h e s m a l l e s t amount t h a t t h e t i m e c a n
4 / / t a k e on . F o r example , w i t h t h i s d i r e c t i v e t h e number
5 / / 0 . 0 0 1 would be i n t e r p r e t e d a s 0 . 0 0 1 ns , o r 1 p s .
6 / / However , t h e number 0 . 0 0 0 1 would be i n t e r p r e t e d a s 0 s i n c e
7 / / i t i s s m a l l e r t h a n t h e minimum p r e c i s i o n v a l u e .

1.7.3 Verilog Operators

There are a variety of pre-defined operators in the Verilog standard. It is important to note that operators
are defined to work on specific data types and that not all operators are synthesizable.

1.7.3.1 Assignment Operator

Verilog uses the equal sign (=) to denote an assignment. The left-hand side (LHS) of the assignment is
the target signal. The right-hand side (RHS) contains the input arguments and can contain both signals,
constants, and operators.
Example:
1 F1 = A; / / F1 i s a s s i g n e d t h e s i g n a l A
2 F2 = 8 ’hAA ; / / F2 i s an 8− b i t v e c t o r and i s a s s i g n e d t h e v a l u e 101010102

1.7.3.2 Bitwise Logical Operators

Bitwise operators perform logic functions on individual bits. The inputs to the operation are single
bits and the output is a single bit. In the case where the inputs are vectors, each bit in the first vector
is operated on by the bit in the same position from the second vector. If the vectors are not the same
length, the shorter vector is padded with leading zeros to make both lengths equal. Verilog contains the
following bitwise operators (Table 1.7):

Syntax Description
~ Negation
& AND
| OR
^ XOR
~^ or ^~ XNOR
<< Logical shift left (fill empty LSB location with zero)
>> Logical shift right (fill empty MSB location with zero)
Table 1.7: Verilog bitwise logical operators.

27
 Example:
1 ~X // i n v e r t each b i t in X
2 X & Y // AND e a c h b i t o f X w i t h e a c h b i t o f Y
3 X | Y // OR e a c h b i t o f X w i t h e a c h b i t o f Y
4 X ^ Y // XOR e a c h b i t o f X w i t h e a c h b i t o f Y
5 X ~^ Y // XNOR e a c h b i t o f X w i t h e a c h b i t o f Y
6 X << 3 // S h i f t X l e f t 3 t i m e s and f i l l w i t h z e r o s
7 Y >> 2 // S h i f t Y r i g h t 2 t i m e s and f i l l w i t h z e r o s

1.7.3.3 Reduction Logic Operators

A reduction operator is one that uses each bit of a vector as individual inputs into a logic operation and
produces a single bit output. Verilog contains the following reduction logic operators (Table 1.8):

Syntax Description
& AND all bits in the vector together (1-bit result)
~& NAND all bits in the vector together (1-bit result)
| OR all bits in the vector together (1-bit result)
~| NOR all bits in the vector together (1-bit result)
^ XOR all bits in the vector together (1-bit result)
~^ or ^~ XNOR all bits in the vector together (1-bit result)
Table 1.8: Verilog reduction logic operators.

Example:
1 &X // AND a l l b i t s i n v e c t o r X t o g e t h e r
2 ~&X // NAND a l l b i t s i n v e c t o r X t o g e t h e r
3 |X // OR a l l b i t s i n v e c t o r X t o g e t h e r
4 ~ |X // NOR a l l b i t s i n v e c t o r X t o g e t h e r
5 ^X // XOR a l l b i t s i n v e c t o r X t o g e t h e r
6 ~^X // XNOR a l l b i t s i n v e c t o r X t o g e t h e r

1.7.3.4 Boolean Logic Operators

A Boolean logic operator is one that returns a value of TRUE (1) or FALSE (0) based on a logic
operation of the input operations. These operations are used in decision statements (Table 1.9):

Syntax Operation
! Negation
&& AND
|| OR
Table 1.9: Verilog Boolean logic operators.

28
 Example:
1 !X / / TRUE i f a l l v a l u e s i n X a r e 0 , FALSE o t h e r w i s e
2 X && Y / / TRUE i f t h e b i t w i s e AND o f X and Y r e s u l t s i n a l l ones , FALSE
otherwise
3 X | | Y / / TRUE i f t h e b i t w i s e OR o f X and Y r e s u l t s i n a l l ones , FALSE
otherwise

1.7.3.5 Relational Operators

A relational operator is one that returns a value of TRUE (1) or FALSE (0) based on a comparison of
two inputs (Table 1.10).

Syntax Operation
== Equality
!= Inequality
< Less than
> Greater than
<= Less than or equal
>= Greater than or equal
Table 1.10: Verilog relational operators.

Example:
1 X == Y // TRUE if X is e q u a l t o Y, FALSE o t h e r w i s e
2 X != Y // TRUE if X is n o t e q u a l t o Y, FALSE o t h e r w i s e
3 X < Y // TRUE if X is l e s s t h a n Y, FALSE o t h e r w i s e
4 X > Y // TRUE if X is g r e a t e r t h a n Y, FALSE o t h e r w i s e
5 X <= Y // TRUE if X is l e s s t h a n o r e q u a l t o Y, FALSE o t h e r w i s e
6 X >= Y // TRUE if X is g r e a t e r t h a n o r e q u a l t o Y, FALSE o t h e r w i s e

1.7.3.6 Conditional Operators

Verilog contains a conditional operator that can be used to provide a more intuitive approach to mod-
eling logic statements. The keyword for the conditional operator is ? with the following syntax:
1 < t a r g e t _ n e t > = <Boolean_condition > ? < true_assignment > : < false_assignment >;

This operator specifies a Boolean condition in which if evaluated TRUE, the true_assignment
will be assigned to the target. If the Boolean condition is evaluated FALSE, the false_assignment
portion of the operator will be assigned to the target. The values in this assignment can be signals or
logic values. The Boolean condition can be any combination of the Boolean operators described above.
Nested conditional operators can also be implemented by inserting subsequent conditional operators in
place of the false_value.
Example:
1 F = (A == 1 ’ b0 ) ? 1 ’ b1 : 1 ’ b0 ; / / I f A i s a z e r o , F =1 , o t h e r w i s e F=0
2 // T h i s m o d e l s an i n v e r t e r
3

4 F = ( s e l == 1 ’ b0 ) ? A : B ; / / I f s e l i s a z e r o , F=A, o t h e r w i s e F=B
5 // This models a s e l e c t a b l e s w i t c h

29
6

7 F = ( (A == 1 ’ b0 ) && (B == 1 ’ b0 ) ) ? 1 ’ b0 : / / N e s t e d c o n d i t i o n a l s t a t e m e n t s
8 ( (A == 1 ’ b0 ) && (B == 1 ’ b1 ) ) ? 1 ’ b1 : / / T h i s m o d e l s an XOR g a t e
9 ( (A == 1 ’ b1 ) && (B == 1 ’ b0 ) ) ? 1 ’ b1 :
10 ( (A == 1 ’ b1 ) && (B == 1 ’ b1 ) ) ? 1 ’ b0 : 1 ’ b0 ;
11

12 F = ( ! C && ( ! A | | B ) ) ? 1 ’ b1 : 1 ’ b0 ; / / T h i s m o d e l s t h e l o g i c e x p r e s s i o n
13 / / F = C ’ . ( A’ +B )

1.7.3.7 Concatenation Operator

In Verilog, the curly brackets (i.e., {}) are used to concatenate multiple signals. The target of this
operation must be the same size of the sum of the sizes of the input arguments.
Example:
1 Bus1 [ 7 : 0 ] = { Bus2 [ 7 : 4 ] , Bus3 [ 3 : 0 ] } ; / / Assuming Bus1 , Bus2 , and Bus3 a r e
2 / / a l l 8− b i t v e c t o r s , t h i s o p e r a t i o n t a k e s t h e u p p e r 4− b i t s o f
3 / / Bus2 , c o n c a t e n a t e s them w i t h t h e l o w e r 4− b i t s o f
4 / / Bus3 , and a s s i g n s t h e 8− b i t c o m b i n a t i o n t o Bus1 .
5

6 BusC = {BusA , BusB } ; / / I f BusA and BusB a r e 4− b i t s , t h e n BusC

7 / / must be 8− b i t s .
8

9 BusC [ 7 : 0 ] = {4 ’ b0000 , BusA } ; / / T h i s p a d s t h e 4− b i t v e c t o r BusA w i t h 4 x

10 / / l e a d i n g z e r o s and a s s i g n s t o t h e 8− b i t v e c t o r BusC .

1.7.3.8 Replication Operator

Verilog provides the ability to concatenate a vector with itself through the replication operator. This
operator uses double curly brackets (i.e., {{}}) and an integer indicating the number of replications to
be performed. The replication syntax is as follows:
1 { < n u m b e r _ o f _ r e p l i c a t i o n s > {< v e c t o r _ n a m e _ t o _ b e _ r e p l i c a t e d >} }
Example:
1 BusX = {4{ Bus1 } } ; / / T h i s i s e q u i v a l e n t t o :
2 / / BusX = { Bus1 , Bus1 , Bus1 , Bus1 } ;
3 BusY = {2{A, B } } ; / / T h i s i s e q u i v a l e n t t o : BusY = {A, B , A, B } ;
4 BusZ = { Bus1 , {2{ Bus2 } } } ; / / T h i s i s e q u i v a l e n t t o :
5 / / BusZ = { Bus1 , Bus2 , Bus2 } ;

1.7.3.9 Numerical Operators

Verilog also provides a set of numerical operators as follows (Table 1.11):

30
 Syntax Operation
+ Addition
- Subtraction (when placed between arguments)
- 2’s complement negation (when placed in front of an argument)
* Multiplication
/ Division
% Modulus
** Raise to the power
<<< Shift to the left, fill with zeros
>>> Shift to the right, fill with sign bit
Table 1.11: Verilog numerical operators.

Example:
1 X + Y // Add X t o Y
2 X − Y // S u b t r a c t Y from X
3 −X // Take t h e two ’ s complement n e g a t i o n o f X
4 X * Y // M u l t i p l y X by Y
5 X / Y // D i v i d e X by Y
6 X % Y // Modulus X / Y
7 X ** Y // R a i s e X t o t h e power o f Y
8 X <<< 3 // S h i f t X l e f t 3 times , f i l l with zeros
9 X >>> 2 // S h i f t X r i g h t 2 times , f i l l with sign b i t
Verilog will allow the use of these operators on arguments of different sizes, types, and signs. The
rules of the operations are as follows:

• If two vectors are of different sizes, the smaller vector is expanded to the size of the larger vector.

– If the smaller vector is unsigned, it is padded with zeros.

– If the smaller vector is signed, it is padded with the sign bit.

• If one of the arguments is real, then the arithmetic will take place using real numbers.

• If one of the arguments is unsigned, then all arguments will be treated as unsigned.

1.7.3.10 Operator Precedence

The following is the order of precedence of the Verilog operators (Table 1.12):

31
 Operators Precedence Notes
! ~ + - Highest Bitwise/unary
{} {{}} Highest Concatenation/replication
() ↓ No operation, just parenthesis
** Power
* / % Binary multiply/divide/modulo
+ - ↓ Binary addition/subtraction
<< >> <<< >>> Shift operators
< <= > >= Greater/less than comparisons
== != ↓ Equality/inequality comparisons
& ~& AND/NAND operators
^ ~^ XOR/XNOR operators
| ~| ↓ OR/NOR operators
&& Boolean AND
|| Boolean OR
?: Lowest Conditional operator
Table 1.12: Verilog operator precedence.

In-class Question 3: What revision of Verilog added the ability to list the port names, types, and
directions just once after the module name?

1. Verilog-1995.

2. Verilog-2001.

3. Verilog-2005.

4. SystemVerilog.

In-class Question 4: What is the difference between types wire and reg?

1. They are the same.

2. The type wire is a simple interconnection while reg will hold the value of its last assignment.

3. The type wire is for scalars while the type reg is for vectors.

4. Only wire is synthesizable.

1.8 Modeling Concurrent Functionality in Verilog

It is important to remember that Verilog is a hardware description language, not a programming lan-
guage. In a programming language, the lines of code are executed sequentially as they appear in the
source file. In Verilog, the lines of code represent the behavior of real hardware. Thus, the assignments
are executed concurrently unless specifically noted otherwise.

32
 1.8.1 Continuous Assignment
Verilog uses the keyword assign to denote a continuous signal assignment. After this keyword, an
assignment is made using the = symbol. The left-hand side (LHS) of the assignment is the target signal
and must be a net type. The right-hand side (RHS) contains the input arguments and can contain nets,
regs, constants, and operators. A continuous assignment models combinational logic. Any change to the
RHS of the expression will result in an update to the LHS target net. The net being assigned to must be
declared prior to the first continuous assignment. Multiple continuous assignments can be made to the
same net. When this happens, the assignment containing signals with the highest drive strength will take
priority.
Example:
1 a s s i g n F1 = A ; / / F1 i s u p d a t e d a n y t i m e A c h a n g e s , where A i s a s i g n a l
2 a s s i g n F2 = 1 ’ b0 ; / / F2 i s assigned the value 0
3 a s s i g n F3 = 4 ’hAA ; / / F3 i s an 8− b i t v e c t o r and i s a s s i g n e d
4 // the v a l u e 101010102
Each individual assignment will be executed concurrently and synthesized as separate logic circuits.
Consider the following example.
Example:
1 a s s i g n X = A;
2 assign Y = B;
3 assign Z = C;
When simulated, these three lines of Verilog will make three separate signal assignments at the exact
same time. This is different from a programming language that will first assign A to X, then B to Y, and
finally C to Z. In Verilog this functionality is identical to three separate wires. This description will be
directly synthesized into three separate wires.
Below is another example of how continuous signal assignments in Verilog differ from a sequentially
executed programming language.
Example:
1 assign A = B;
2 assign B = C;
In a Verilog simulation, the signal assignments of C to B and B to A will take place at the same time.
This means during synthesis, the signal B will be eliminated from the design since this functionality
describes two wires in series. Automated synthesis tools will eliminate this unnecessary signal name.
This is not the same functionality that would result if this example was implemented as a sequentially
executed computer program. A computer program would execute the assignment of B to A first and then
assign the value of C to B second. In this way, B represents a storage element that is passed to A before
it is updated with C.

1.8.2 Continuous Assignment with Logical Operators

Each of the logical operators described in Section 1.7.3.2 can be used in conjunction with concurrent
signal assignments to create individual combinational logic circuits. Example in Fig. 1.15 shows how to
design a Verilog model of a combinational logic circuit using this approach.

33
 Figure 1.15: Modeling combinational logic using continuous assignment with logical operators.

1.8.3 Continuous Assignment with Conditional Operators

Logical operators are good for describing the behavior of small circuits; however, in the prior example,
we still needed to create the canonical sum of products logic expression by hand before describing the
functionality in Verilog. The true power of an HDL is when the behavior of the system can be described
fully without requiring any hand design. The conditional operator allows us to describe a continuous
assignment using Boolean conditions that affect the values of the result. In this approach, we use the
conditional operator (?) in conjunction with the continuous assignment keyword assign. Example in Fig.
1.16 shows how to design a Verilog model of a combinational logic circuit using continuous assignment

34
with conditional operators. Note that this example uses the same truth table as in Example shown in Fig.
1.15 to illustrate a comparison between approaches.

Figure 1.16: Modeling combinational logic using continuous assignment with conditional operators (1).

In the prior example, the conditional operator was based on a truth table. Conditional operators can
also be used to model logic expressions. Example in Fig. 1.17 shows how to design a Verilog model of
a combinational logic circuit when the logic expression is already known. Note that this example again
uses the same truth table as in Examples in Fig. 1.15 and Fig. 1.16 to illustrate a comparison between
approaches.

35
 Figure 1.17: Modeling combinational logic using continuous assignment with conditional operators (2).

1.8.4 Continuous Assignment with Delay

Verilog provides the ability to model gate delays when using a continuous assignment. The # is used
to indicate a delayed assignment. For combinational logic circuits, the delay can be specified for all
transitions, for rising and falling transitions separately, and for rising, falling, and transitions to the value
off separately. A transition to off refers to a transition to Z. If only one delay parameter is specified, it
is used to model all delays. If two delay parameters are specified, the first parameter is used for the rise
time delay, while the second is used to model the fall time delay. If three parameters are specified, the
third parameter is used to model the transition to off. Parentheses are optional but recommended when
using multiple delay parameters.
1 a s s i g n #( < d e l _ a l l > ) < t a r g e t _ n e t > = <RHS_nets , o p e r a t o r s , e t c . . . > ;
2 a s s i g n #( < d e l _ r i s e , d e l _ f a l l > ) < t a r g e t _ n e t > = <RHS_nets , o p e r a t o r s , e t c . . . > ;
3 a s s i g n #( < d e l _ r i s e , d e l _ f a l l , d e l _ o f f > ) < t a r g e t _ n e t > = <RHS_nets , o p e r a t o r s ,
4 etc ... >;

Example:
1 a s s i g n #1 F = A ; // D e l a y o f 1 on a l l t r a n s i t i o n s .
2 a s s i g n # ( 2 , 3 ) F = A; / / D e l a y o f 2 f o r r i s i n g t r a n s i t i o n s and 3
3 // for falling .
4 a s s i g n # ( 2 , 3 , 4 ) F = A; / / D e l a y o f 2 f o r r i s i n g , 3 f o r f a l l i n g , and 4
5 // for off transitions .
When using delay, it is typical to include the ‘timescale directive to provide the units of the
delay being specified. Example in Fig. 1.18 shows a graphical depiction of using delay with continuous
assignments when modeling combinational logic circuits.

36
 Figure 1.18: Modeling delay in continuous assignments.

Verilog also provides a mechanism to model a range of delays that are selected by a switch set in
the CAD compiler. There are three delays categories that can be specified: minimum, typical, and
maximum. The delays are separated by a ":". The following is the syntax of how to use the delay range
capability.

37
1 a s s i g n #( < min >: < t y p >: <max > ) < t a r g e t _ n e t > = <RHS_nets , o p e r a t o r s , e t c . . . > ;
Example:
1 a s s i g n # ( 1 : 2 : 3 ) F = A; / / Specifying a range of delays for a l l
2 // transitions .
3 a s s i g n # ( 1 : 1 : 2 , 2 : 2 : 3 ) F = A; / / S p e c i f y i n g a range of d e l a y s f o r
4 // rising / falling .
5 a s s i g n # ( 1 : 1 : 2 , 2 : 2 : 3 , 4 : 4 : 5 ) F = A; / / S p e c i f y i n g a range of d e l a y s f o r
6 // each t r a n s i t i o n .
The delay modeling capability in continuous assignment is designed to model the behavior of real
combinational logic with respect to short duration pulses. When a pulse is shorter than the delay of the
combinational logic gate, the pulse is ignored. Ignoring brief input pulses on the input accurately models
the behavior of on-chip gates. When the input pulse is faster than the delay of the gate, the output of the
gate does not have time to respond. As a result, there will not be a logic change on the output. This is
called inertial delay modeling and is the default behavior when using continuous assignments. Example
in Fig 1.19 shows a graphical depiction of inertial delay behavior in Verilog.

Figure 1.19: Inertial delay modeling when using continuous assignment.

In-class Question 5: Why is concurrency such an important concept in HDLs?

1. Concurrency is a feature of HDLs that can’t be modeled using schematics.

2. Concurrency allows automated synthesis to be performed.

3. Concurrency allows logic simulators to display useful system information.

4. Concurrency is necessary to model real systems that operate in parallel.

38
 In-class Question 6: Why does modeling combinational logic in its canonical form with continuous
assignment with logical operators defeat the purpose of the modern digital design flow?

1. It requires the designer to first create the circuit using the classical digital design approach and then
enter it into the HDL in a form that is essentially a text-based netlist. This doesn’t take advantage
of the abstraction capabilities and automated synthesis in the modern flow.

2. It cannot be synthesized because the order of precedence of the logical operators in Verilog doesn’t
match the precedence defined in Boolean algebra.

3. The circuit is in its simplest form so there is no work for the synthesizer to do.

4. It doesn’t allow an else clause to cover the outputs for any remaining input codes not explicitly
listed.

1.9 Structural Design and Hierarchy

Structural design in Verilog refers to including lower-level sub-systems within a higher-level module in
order to produce the desired functionality. This is called hierarchy and is a good design practice because
it enables design partitioning. A purely structural design will not contain any behavioral constructs in
the module such as signal assignments but instead just contain the instantiation and interconnections of
other sub-systems. A sub-system in Verilog is simply another module that is called by a higher-level
module. Each lower-level module that is called is executed concurrently by the calling module.

1.9.1 Lower-Level Module Instantiation

The term instantiation refers to the use or inclusion of a lower-level module within a system. In Verilog,
the syntax for instantiating a lower-level module is as follows:
1 module_name < i n s t a n c e _ i d e n t i f i e r > ( p o r t mapping . . . ) ;
The first portion of the instantiation is the module name that is being called. This must match the
lower-level module name exactly, including case. The second portion of the instantiation is an optional
instance identifier. An instance identifier is useful when instantiating multiple instances of the same
lower-level module. The final portion of the instantiation is the port mapping. There are two techniques
to connect signals to the ports of the lower-level module, explicit and positional (implicit).

1.9.1.1 Explicit Port Mapping

In explicit port mapping, the names of the ports of the lower-level sub-system are provided along with
the signals they are being connected to. The lower-level port name is preceded with a period (.), while
the signal it is being connected is enclosed within parentheses. The port connections can be listed in any
order since the details of the connection (i.e., port name to signal name) are explicit. Each connection is
separated by a comma. The syntax for explicit port mapping is as follows:
1 module_name < i n s t a n c e i d e n t i f i e r > (
2 . port_name1 ( s i g n a l 1 ) ,
3 . port_name2 ( s i g n a l 2 ) ,
4 . port_name3 ( s i g n a l 3 ) ,
5 etc . ) ;

39
 Example in Fig. 1.20 shows how to design a Verilog model of a hierarchical system that consists of
two lower-level modules.

Figure 1.20: Verilog structural design using explicit port mapping.

1.9.1.2 Positional Port Mapping

In positional port mapping, the names of the ports of the lower-level modules are not explicitly listed.
Instead, the signals to be connected to the lower-level system are listed in the same order in which the
ports were defined in the sub-system. Each signal name is separated by a comma. This approach requires
less text to describe the connection but can also lead to misconnections due to inadvertent mistakes in
the signal order. The syntax for positional port mapping is as follows:
1 module_name : < i n s t a n c e _ i d e n t i f i e r > ( s i g n a l 1 , s i g n a l 2 , e t c . ) ;
Example in Fig. 1.21 shows how to create the same structural Verilog model as in Example in Fig.
1.21, but using positional port mapping instead.

40
 Figure 1.21: Verilog structural design using positional port mapping.

1.9.2 Gate-Level Primitives

Verilog provides the ability to model basic logic functionality through the use of primitives. A prim-
itives a logic operation that is simple enough that it doesn’t require explicit modeling. An example
of this behavior can be a basic logic gate or even a truth table. Verilog provides a set of gate-level
primitives to model simple logic operations. These gate-level primitives are not(), and(), nand(),
or(), nor(), xor(), and xnor(). Each of these primitives is instantiated as lower-level sub-systems
with positional port mapping. The port order for each primitive has the output listed first followed by
the input(s). The output and each of the inputs are scalars. Gate-level primitives do not need to be
explicitly created as they are provided as part of the Verilog standard. One of the benefits of using
gate-level primitives is that the number of inputs is easily scaled as each primitive can accommodate
an increasing number of inputs automatically. Furthermore, modeling using this approach essentially
provides a gate-level netlist, so it represents a very low-level, detailed gate-level implementation that is
ready for technology mapping. Example in fig. 1.22 shows how to use gate-level primitives to model the
behavior of a combinational logic circuit.

41
 Figure 1.22: Modeling combinational logic circuits using gate-level primitives.

1.9.3 User-Defined Primitives

A user-defined primitive (UDP) is a system that describes the behavior of a low-level component using
a logic table. This is very useful for creating combinational logic functionality that will be used numer-
ous times. UDPs are also useful for large truth tables where it is more convenient to list the functionality
in table form. UDPs are lower-level sub-systems that are intended to be instantiated in higher-level
modules just like gate-level primitives, with the exception that the UPD needs to be created in its own
file. The syntax for a UDP is as follows:
1 p r i m i t i v e pr i m i ti v e _ na m e ( o u t p u t output_name ,
2 i n p u t input_name1 , input_name2 , ...) ;
3 table
4 in1_val in2_val . . . : out_val ;
5 in1_val in2_val . . . : out_val ;
6 :

42
7 endtable
8 endprimitive
A UDP must list its output(s) first in the port definition. It also does not require types to be defined
for the ports. For combinational logic UDPs, all ports are assumed to be of type wire. Example in Fig.
1.23 shows how to design a user-defined primitive to implement a combinational logic circuit.

Figure 1.23: Modeling combinational logic circuits with a user-defined primitive.

Note: To use UDPs in Xilinx ISE you should create a file to define the user defined primitive and
then use ‘include directive to use the UDP in your other design files and also in simulation.
Example:
Listing 1.5: SystemX_UDP.v (UDP File)
1 p r i m i t i v e SystemX_UDP (
2 output F ,
3 i n p u t A, B , C
4 );
5

43
6 table
7 // A B C : F
8 0 0 0 : 1;
9 0 0 1 : 0;
10 0 1 0 : 1;
11 0 1 1 : 0;
12 1 0 0 : 0;
13 1 0 1 : 0;
14 1 1 0 : 1;
15 1 1 1 : 0;
16 endtable
17 endprimitive

Listing 1.6: SystemX.v (Design File)

1 ‘ t i m e s c a l e 1 ns / 1 ps
2 ‘ i n c l u d e " SystemX_UDP . v "
3

4 module SystemX ( o u t p u t w i r e F ,
5 i n p u t w i r e A, B , C
6 );
7

8 SystemX_UDP U0 ( F , A, B , C ) ;
9

10 endmodule

Listing 1.7: test_SystemX.v (Simulation File - Test bench)

1 ‘ t i m e s c a l e 1 ns / 1 ps
2 ‘ i n c l u d e " SystemX_UDP . v "
3

4 module t e s t _ S y s t e m X ;
5 / / Inputs
6 r e g A;
7 reg B;
8 reg C;
9

10 / / Outputs
11 wire F ;
12

13 / / I n s t a n t i a t e t h e U n i t Under T e s t (UUT)
14 SystemX u u t (
15 .F(F) ,
16 . A(A) ,
17 . B(B) ,
18 . C(C)
19 );
20

21 integer i ;
22

23 i n i t i a l begin
24 / / I n i t i a l i z e Inputs
25 A = 0;

44
26 B = 0;
27 C = 0;
28

29 / / Wait 100 n s f o r g l o b a l r e s e t t o f i n i s h
30 #100;
31

32 / / Add s t i m u l u s h e r e
33 f or ( i = 0; i < 8; i = i + 1) begin
34 #10 {A, B , C} = i ;
35 end
36

37 endmodule

1.9.4 Adding Delay to Primitives

Delay can be added to primitives using the same approach as described in Section 1.8.4. The delay is
inserted after the primitive name but before the instance name.
Example:
1 n o t #2 U0 ( An , A) ; / / G a t e l e v e l p r i m i t i v e f o r an i n v e r t e r w i t h d e l a y o f 2 .
2 and #3 U3 ( m0 , An , Bn , Cn ) ; / / G a t e l e v e l p r i m i t i v e f o r an AND g a t e w i t h
3 // delay of 3.
4 SystemX_UDP #1 U0 ( F , A, B , C ) ; / / UDP w i t h a d e l a y o f 1 .
In-class Question 7 : Does the use of lower-level sub-modules model concurrent functionality? Why?

1. No. Since the lower-level behavior of the module being instantiated may contain nonconcurrent
behavior, it is not known what functionality will be modeled.

2. Yes. The modules are treated like independent sub-systems whose behavior runs in parallel just as
if separate parts were placed in a design.

1.10 Overview of Simulation Test Benches

One of the essential components of the modern digital design flow is verifying functionality through
simulation. This simulation takes place at many levels of abstraction. For a system to be tested, there
needs to be a mechanism to generate input patterns to drive the system and then observe the outputs to
verify correct operation. The mechanism to do this in Verilog is called a test bench. A test bench is
a file in Verilog that has no inputs or outputs. The test bench instantiates the system to be tested as a
lower-level module. The test bench generates the input conditions and drives them into the input ports
of the system being tested. Verilog contains numerous methods to generate stimulus patterns. Since a
test bench will not be synthesized, very abstract behavioral modeling can be used to generate the inputs.
The output of the system can be viewed as a waveform in a simulation tool. Verilog also has the ability
to check the outputs against expected results and notify the user if differences occur. Fig. 1.24 gives an
overview of how test benches are used in Verilog.

45
 output wire F

Figure 1.24: Overview of Verilog test benches.

In-class Question 8: How can the output of a DUT be verified when it is connected to a signal that
does not go anywhere?

1. It can’t. The output must be routed to an output port on the test bench.

2. The values of any dangling signal are automatically written to a text file.

3. It is viewed in the logic simulator as either a waveform or text listing.

4. It can’t. A signal that does not go anywhere will cause an error when the Verilog file is compiled.

1.11 Assignments
1. What was the original purpose of Verilog?

2. Can all of the functionality that can be described in Verilog be simulated?

3. Can all of the functionality that can be described in Verilog be synthesized?

4. Give the level of design abstraction that the following statement relates to: if there is ever an error
in the system, it should return to the reset state.

46
 5. Give the level of design abstraction that the following statement relates to: once the design is
implemented in a sum of products form, DeMorgan’s Theorem will be used to convert it to a
NAND-gate only implementation.

6. Give the level of design abstraction that the following statement relates to: the design will be
broken down into two sub-systems, one that will handle data collection and the other that will
control data flow.

7. Give the level of design abstraction that the following statement relates to: the MOSFETs need to
be able to drive at least 8 other loads in this design.

8. Give the level of design abstraction that the following statement relates to: this system will contain
1 host computer and support up to 1000 client computers.

9. Give the design domain that the following activity relates to: drawing the physical layout of the
CPU will require 6 months of engineering time.

10. Give the design domain that the following activity relates to: the CPU will be connected to four
banks of memory.

11. Give the design domain that the following activity relates to: the fan-in specifications for this logic
family require excessive logic circuitry to be used.

12. Give the design domain that the following activity relates to: the performance specifications for
this system require 1 TFLOP at <5 W.

13. Which step in the modern digital design flow does the following statement relate to: a CAD tool
will convert the behavioral model into a gate-level description of functionality.

14. Which step in the modern digital design flow does the following statement relate to: after realistic
gate and wiring delays are determined, one last simulation should be performed to make sure the
design meets the original timing requirements.

15. Which step in the modern digital design flow does the following statement relate to: if the memory
is distributed around the perimeter of the CPU, the wiring density will be minimized.

16. Which step in the modern digital design flow does the following statement relate to: the design
meets all requirements so now I’m building the hardware that will be shipped.

17. Which step in the modern digital design flow does the following statement relate to: the system
will be broken down into three sub-systems with the following behaviors.

18. Which step in the modern digital design flow does the following statement relate to: this system
needs to have 10 Gbytes of memory.

19. Which step in the modern digital design flow does the following statement relate to: to meet the
power requirements, the gates will be implemented in the 74HC logic family.

20. What is the name of the main design unit in Verilog?

21. What are all the possible values that a Verilog net type can take on?

22. What is the highest strength that a value can take on in Verilog.

47
23. What is the range of decimal numbers that can be represented using the type integer in Verilog?

24. What is the width of the vector defined using the type [63:0] wire?

25. What is the syntax for indexing the most significant bit in the type [31:0] wire? Assume the vector
is named example.

26. What is the syntax for indexing the least significant bit in the type [31:0] wire? Assume the vector
is named example.

27. What is the difference between a wire and reg type?

28. How many bits is the type integer by default?

29. How many bits is the type real by default?

30. Design a Verilog model to implement the behavior described by the 3-input minterm list shown in
Fig. 1.25. Use continuous assignment with logical operators. Declare your module and ports to
match the block diagram provided. Use the type wire for your ports. Your answer should include
design source code and simulation obtained from Xilinx ISIM simulator.

31. Design a Verilog model to implement the behavior described by the 3-input minterm list shown
in Fig. 1.25. Use continuous assignment with conditional operators. Declare your module and
ports to match the block diagram provided. Use the type wire for your ports. Your answer should
include design source code and simulation obtained from Xilinx ISIM simulator.

Figure 1.25: System E functionality for question no. 30-31.

32. Design a Verilog model to implement the behavior described by the 3-input maxterm list shown
in Fig. 1.26. Use continuous assignment with logical operators. Declare your module and ports to
match the block diagram provided. Use the type wire for your ports. Your answer should include
design source code and simulation obtained from Xilinx ISIM simulator.

33. Design a Verilog model to implement the behavior described by the 3-input maxterm list shown
in Fig. 1.26. Use continuous assignment with conditional operators. Declare your module and
ports to match the block diagram provided. Use the type wire for your ports. Your answer should
include design source code and simulation obtained from Xilinx ISIM simulator.

48
 Figure 1.26: System F functionality for question no. 32-33.

34. Design a Verilog model to implement the behavior described by the 3-input truth table shown in
Fig. 1.27. Use continuous assignment with logical operators. Declare your module and ports to
match the block diagram provided. Use the type wire for your ports. Your answer should include
design source code and simulation obtained from Xilinx ISIM simulator.

35. Design a Verilog model to implement the behavior described by the 3-input truth table shown in
Fig. 1.27. Use continuous assignment with conditional operators. Declare your module and ports
to match the block diagram provided. Use the type wire for your ports. Your answer should include
design source code and simulation obtained from Xilinx ISIM simulator.

Figure 1.27: System G functionality for question no. 34-35.

36. Design a Verilog model to implement the behavior described by the 4-input truth table shown in
Fig. 1.28. Use continuous assignment and logical operators. Declare your module and ports to
match the block diagram provided. Use the type wire for your ports. Your answer should include
design source code and simulation obtained from Xilinx ISIM simulator.

37. Design a Verilog model to implement the behavior described by the 4-input truth table shown in
Fig. 1.28. Use continuous assignment and conditional operators. Declare your module and ports to
match the block diagram provided. Use the type wire for your ports. Your answer should include
design source code and simulation obtained from Xilinx ISIM simulator.

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 Figure 1.28: System K functionality for question no. 36-37.

38. Design a Verilog model to implement the behavior described by the 3-input minterm list shown
in Fig. 1.25. Use a structural design approach based on gate-level primitives. This is considered
structural because you will need to instantiate the gate-level primitives just like a traditional sub-
system; however, you don’t need to create the gate-level modules as they are already built into the
Verilog standard. You will need to determine a logic expression for the system prior to connecting
the gate-level primitives. You can use whatever approach you prefer to create the logic expression
(i.e., canonical SOP/POS, minimized SOP/POS, etc.). Declare your module and ports to match
the block diagram provided. Use the type wire for your ports. Your answer should include design
source code and simulation obtained from Xilinx ISIM simulator.

39. Design a Verilog model to implement the behavior described by the 3-input minterm list shown in
Fig. 1.25. Use a structural design approach based on a user-defined primitive. This is considered
structural because you will need to instantiate the user-defined primitive just like a traditional sub-
system. You will need to create both the upper-level module and the lower-level UDP. Declare your
module and ports to match the block diagram provided. Use the type wire for your ports. Your
answer should include design source code and simulation obtained from Xilinx ISIM simulator.

40. Design a Verilog model to implement the behavior described by the 4-input truth table shown in
Fig. 1.28. Use a structural design approach based on gate-level primitives. This is considered
structural because you will need to instantiate the gate-level primitives just like a traditional sub-
system; however, you don’t need to create the gate-level modules as they are already built into the
Verilog standard. You will need to determine a logic expression for the system prior to connecting
the gate- level primitives. You can use whatever approach you prefer to create the logic expression
(i.e., canonical SOP/POS, minimized SOP/POS, etc.). Declare your module and ports to match

50
 the block diagram provided. Use the type wire for your ports. Your answer should include design
source code and simulation obtained from Xilinx ISIM simulator.

41. Design a Verilog model to implement the behavior described by the 4-input truth table shown in
Fig. 1.28. Use a structural design approach based on a user-defined primitive. This is considered
structural because you will need to instantiate the user-defined primitive just like a traditional sub-
system. You will need to create both the upper-level module and the lower-level UDP. Declare your
module and ports to match the block diagram provided. Use the type wire for your ports. Your
answer should include design source code and simulation obtained from Xilinx ISIM simulator.

42. What is the purpose of a test bench?

43. Does a test bench have input and output ports?

44. Can a test bench be simulated?

45. Can a test bench be synthesized?

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