CSC 222 – COMPUTER ARCHITECTURE AND

ORGANISATION
PART I
1.0 Computer Architecture

Computer architecture is the conceptual design and fundamental operational structure of a

computer system. It defines:

 Instruction set: What commands the CPU understands (e.g., ADD, MOV, JMP).
 Data types: What kind of data the system can process (integers, floats, etc.).
 Registers and addressing modes: How data is stored and accessed.
 I/O mechanisms and memory architecture.

It focuses on the functionality and performance design of a system, such as pipelining,

parallelism, and instruction-level efficiency.

Computer Organisation

Computer organisation refers to the implementation details of a computer's architecture. It

includes:

 How the control unit, ALU, memory, and I/O devices are interconnected.
 Signal transmission, timing, and data flow between components.
 The actual hardware design, such as gate-level logic or board-level circuitry.

Analogy:

 Architecture is the blueprint of a house (logical plan).

 Organisation is the construction and wiring, ensuring everything works as
per the design.

2.0 Basic Hardware Components of a Computer System

2.1 Central Processing Unit (CPU)

The CPU is the "brain" of the computer. It performs computations, decision-making, and
controls the entire system.

Components:

 Arithmetic Logic Unit (ALU):

o Performs arithmetic operations (addition, subtraction).
o Executes logical operations (AND, OR, NOT, comparisons).
 Control Unit (CU):
o Directs all other units by interpreting instructions from memory.
 o Generates control signals for fetching, decoding, and executing instructions.
 Registers:
o High-speed, small-sized storage inside the CPU.
o Temporarily hold data, instructions, addresses, or intermediate results.
o Common types:
 Accumulator (ACC): Holds results of arithmetic/logic operations.
 Program Counter (PC): Holds address of next instruction.
 Instruction Register (IR): Holds current instruction.

2.2 Memory (Main Storage)

Stores instructions and data temporarily or permanently.

 RAM (Random Access Memory):

o Volatile memory — data lost when power is off.
o Read and write capable.
o Used for active processes and temporary storage.
 ROM (Read-Only Memory):
o Non-volatile — retains data without power.
o Contains firmware like the BIOS or bootloader.
 Cache Memory:
o Small-sized, very fast memory located between CPU and RAM.
o Stores frequently accessed instructions/data to reduce latency.
o Levels: L1 (fastest, smallest), L2, and sometimes L3.

2.3 Input/Output (I/O) Devices

Devices that enable communication between the computer and the outside world.

 Input Devices:
o Send data to the computer.
o Examples: Keyboard, Mouse, Scanner, Microphone.
 Output Devices:
o Receive data from the computer.
o Examples: Monitor, Printer, Speakers.
 I/O Controllers:
o Interfaces that manage data flow between I/O devices and CPU.

2.4 Buses

A bus is a communication system that transfers data between components.

 Data Bus:
o Carries actual data between processor, memory, and I/O.
o Typically bi-directional.
 Address Bus:
o Carries memory addresses of where data is stored or retrieved.
o Uni-directional (from CPU to memory).
 Control Bus:
o Carries control signals such as Read, Write, and Interrupt.
 o Coordinates operations between CPU and peripherals.

Example: When reading from memory, the CPU sends an address over the address bus, issues
a read signal over the control bus, and receives the data over the data bus.

2.5 System Clock

The clock synchronizes all components of the computer.

 Generates a steady stream of electrical pulses (clock cycles).

 All operations are synchronized to these pulses.
 Affects speed of execution: faster clock = more instructions per second.
 Measured in Hz (Hertz) — 1 GHz = 1 billion cycles per second.

Note: A higher clock speed can improve performance, but must be supported by efficient
architecture (e.g., pipelining, instruction throughput).

Summary of Key Points:

Component Function
CPU Processes instructions and controls execution.
ALU Executes arithmetic and logical operations.
Control Unit Directs operation of other CPU components.
Registers Store temporary data and control information.
RAM Volatile memory for active processes.
ROM Non-volatile memory for firmware.
Cache Fast memory to speed up CPU access.
I/O Devices Facilitate user-system interaction.
Buses Carry data, addresses, and control signals.
System Clock Synchronizes component operations.

3. Instruction Set Architecture (ISA)

3.1 What is Instruction Set Architecture (ISA)?

Definition

Instruction Set Architecture (ISA) is the abstract model of a computer that defines:

 The machine-level instructions a processor can execute.

 The data formats, registers, addressing modes, and memory models.
  The interface between hardware and low-level software (e.g., operating systems,
compilers, and assembly language programmers).

In simple terms, ISA is what the programmer sees when programming in machine or
assembly language — it defines how software communicates with the processor.

Key Functions of ISA:

 Defines how instructions are formatted and decoded.

 Specifies how instructions manipulate data and control flow.
 Provides hardware abstraction — same program can run on different
implementations of the same ISA.

3.2 Types of Instructions in ISA

Instruction sets are typically divided into functional categories. Below are the most common
types with detailed examples:

A. Data Movement Instructions

Move data between memory, registers, and I/O ports.

Instruction Description Example

MOV Transfer data between MOV R1, R2 (copies contents of R2 to R1)
registers/memory
LOAD Load data from memory into a LOAD R1, 1000 (load value from memory
register address 1000 to R1)
STORE Store data from register to STORE R1, 1000 (store value in R1 into
memory memory address 1000)

B. Arithmetic and Logic Instructions

Perform numeric and logical operations.

Instruction Description Example

ADD Adds two values ADD R1, R2 (R1 = R1 + R2)
SUB Subtracts values SUB R1, R2 (R1 = R1 - R2)
MUL Multiplies values MUL R1, R2
DIV Divides values DIV R1, R2
AND Bitwise AND AND R1, R2
OR Bitwise OR OR R1, R2
NOT Bitwise NOT NOT R1
CMP Compare two values (sets flags) CMP R1, R2

C. Control Flow Instructions

Modify the normal sequence of execution.

 Instruction Description Example
JMP Unconditional jump to a new address JMP 2000
JE, JNE Conditional jumps based on flags JE 2000 (jump if equal)
CALL Call a subroutine (function) CALL sum_function
RET Return from subroutine RET
BRANCH Branch to another part of the program BRANCH label

D. Input/Output Instructions

Enable data transfer between CPU and I/O devices.

Instruction Description Example

IN Input data from an I/O port IN R1, 60
OUT Output data to an I/O port OUT R1, 62

3.3 Components of an Instruction

Each instruction in machine language typically includes the following components:

1. Opcode (Operation Code)

 Indicates the operation the instruction performs.

 Examples: ADD, SUB, JMP, MOV.

2. Operands

 Specify data to be operated on. Can be:

o Register (e.g., R1)
o Memory address (e.g., 1000)
o Immediate values (e.g., #5)

3. Addressing Mode (sometimes implicit)

 Determines how the operand is accessed:

o Immediate: Operand is directly in the instruction.
o Register: Operand is in a register.
o Direct: Operand is in memory at a specified address.
o Indirect: Address of the operand is in a register.

Example:
assembly
ADD R1, R2

 Opcode: ADD
 Operands: R1, R2
 Meaning: Add contents of R2 to R1, store result in R1.
Instruction Format (Binary Layout)
When a program runs on a CPU, its instructions are ultimately represented in binary
(machine code) — sequences of bits (0 and 1). The format of these bit sequences is known
as the instruction format, and it varies depending on the Instruction Set Architecture (ISA).

Basic Structure of an Instruction

An instruction is typically divided into fields, such as:

Field Name Purpose

Opcode Specifies the operation to be performed (e.g., ADD, LOAD)
Operands Identifies the data or registers used in the operation
Addressing Mode Indicates how to interpret the operands (e.g., direct, immediate)
Immediate/Address A constant value or memory address to use

Example: Fixed-Length Format (RISC Style)

Let’s say we have a 16-bit instruction format (simplified example):

[Opcode: 4 bits][Reg1: 4 bits][Reg2: 4 bits][Dest: 4 bits]

Each part is:

 Opcode: The binary code for the operation (e.g., 0001 for ADD)
 Reg1: First operand (e.g., source register)
 Reg2: Second operand
 Dest: Where to store the result

Example Instruction

Let's consider this assembly instruction:

assembly

ADD R1, R2, R3

This means: R3 = R1 + R2

Assume:

 ADD has an opcode of 0001

 R1 is register 0001
 R2 is register 0010
 R3 is register 0011

So the binary instruction is:

0001 0001 0010 0011

→ This is the machine-level representation of the ADD instruction.

Summary

Level Example Description

Assembly ADD R1, R2, R3 Human-readable instruction using
Language mnemonics
Machine Code 0001 0001 0010 0011 Binary encoding used by CPU (e.g., 16
bits)
Instruction [Opcode][Reg1][Reg2] Layout structure of how the instruction is
Format encoded

Instruction Format Example in MIPS (32-bit)

MIPS stands for Microprocessor without Interlocked Pipeline Stages. It is both:

1. An Instruction Set Architecture (ISA) — a set of machine-level instructions (like

ADD, LOAD, JUMP, etc.) that MIPS CPUs understand.
2. A family of microprocessors — designed using the MIPS ISA.

MIPS architecture uses fixed 32-bit instruction formats. There are three main types:

1. R-Type (Register Format)

Used for arithmetic/logical instructions.

Field Size Description

opcode 6 bits Operation code
Rs 5 bits Source register 1
Rt 5 bits Source register 2
Rd 5 bits Destination register
shamt 5 bits Shift amount (used in shifts)
funct 6 bits Function code (specific operation)

Example: add $t0, $t1, $t2

 opcode: 000000 (R-type)

 rs = $t1 → 01001
 rt = $t2 → 01010
 rd = $t0 → 01000
 shamt: 00000
 funct: 100000 (ADD)

Binary format:
000000 01001 01010 01000 00000 100000

2. I-Type (Immediate Format)

Used for operations involving constants or memory access.

Field Size Description

opcode 6 bits Operation code
rs 5 bits Source register
rt 5 bits Destination register
immediate 16 bits Constant value or offset

Example: addi $t0, $t1, 10

 opcode: 001000 (ADDI)

 rs = $t1 → 01001
 rt = $t0 → 01000
 immediate: 0000000000001010 (10 in binary)

Binary format:

001000 01001 01000 0000000000001010

3. J-Type (Jump Format)

Used for jump instructions.

Field Size Description

Opcode 6 bits Operation code
address 26 bits Target address to jump to

Example: j 1024

 opcode: 000010 (Jump)

 address: 00000000000000010000000000 (binary for 1024)

Binary format:

000010 00000000000000010000000000

Key Takeaways

 Instruction formats define how the CPU interprets bits in an instruction.

 Fields like opcode, register, immediate, and address vary depending on the ISA
and instruction type.
  RISC architectures (like MIPS, ARM) use fixed-length instruction formats for easier
decoding and pipelining.
 CISC architectures (like x86) use variable-length instructions, making decoding more
complex but allowing richer instructions.

3.4 Types of Instruction Set Architectures

Instruction Set Architectures are generally classified into two broad categories:

1. CISC (Complex Instruction Set Computing)

Key Characteristics

 Large number of complex instructions.

 One instruction can execute multiple low-level operations (e.g., memory access +
calculation).
 Variable-length instructions.
 Rich set of addressing modes.

Advantages

 Fewer instructions per program → smaller code size.

 High-level operations can be done with fewer lines of assembly.

Disadvantages

 Instructions take multiple clock cycles to execute.

 Complex decoding makes pipelining harder.

Example Architectures

 Intel x86
 VAX

2. RISC (Reduced Instruction Set Computing)

Key Characteristics

 Small, highly optimized set of simple instructions.

 Fixed-length instructions.
 Emphasis on load/store architecture (only LOAD/STORE access memory).
 Designed for fast execution and efficient pipelining.

Advantages
  Simple instructions enable single-cycle execution.
 Easy to implement instruction pipelining.
 Simpler hardware design.

Disadvantages

 More instructions needed for complex tasks → larger code size.

Example Architectures

 ARM
 MIPS
 RISC-V
 SPARC

Comparison Table: CISC vs RISC

Feature CISC RISC

Instruction High Low
Complexity
Instruction Count Large Small
Instruction Size Variable Fixed
Execution Time Multiple clock cycles Single clock cycle
Memory Access Instructions can access Only LOAD/STORE access
memory memory
Hardware Complexity Complex control logic Simple, streamlined
Pipeline Support Difficult Easier

Recap / Key Takeaways

 ISA defines how software communicates with hardware.

 It includes instruction types, formats, and execution behaviors.
 Instruction categories include data movement, arithmetic/logic, control flow, and I/O.
 Instructions consist of opcode + operands, often influenced by addressing mode.
 Two major design philosophies:
o CISC: Many complex instructions; compact but slow.
o RISC: Few simple instructions; fast and efficient.

4. Instruction Execution Cycle (Fetch-Decode-Execute Cycle)

This cycle describes how a computer executes each instruction of a program. It is repeated
continuously and rapidly by the CPU, one instruction at a time.

Step-by-Step Breakdown

1. Fetch
  What happens: The CPU fetches (reads) the next instruction to execute from the main
memory (RAM).
 How:
o The address of the next instruction is stored in the Program Counter (PC).
o The CPU sends this address to memory via the address bus.
o The instruction is read from memory and loaded into the Instruction Register
(IR).
 Result: The instruction is now ready to be decoded.

Registers involved:

 PC (Program Counter): Holds address of the next instruction

 IR (Instruction Register): Holds the current instruction

2. Decode

 What happens: The CPU decodes the binary instruction stored in the IR to understand:
o What operation is being requested (e.g., ADD, LOAD, JUMP)
o Which operands (registers, memory addresses, or constants) are involved
 How:
o The Control Unit (CU) interprets the opcode part of the instruction.
o It identifies the required registers or addresses.

Example:

 Binary instruction: 0001 0001 0010 0011

 Opcode 0001 → ADD
 Operands: Reg1 = R1, Reg2 = R2, Destination = R3

3. Execute

 What happens: The CPU performs the required operation.

o This could be an arithmetic calculation, memory access, or a jump.
 How:
o For arithmetic/logic: The ALU (Arithmetic Logic Unit) does the computation.
o For memory access: Data is read from or written to memory.
o For branches: The PC may be updated based on conditions.

Examples:

 ADD R1, R2 → R3: ALU adds contents of R1 and R2, stores result in R3
 LOAD R1, 1000: Load data from memory address 1000 into R1

4. Store (Write-Back)

 What happens: The result of the execution is written back to the appropriate register
or memory location.
 Examples:
o If the result is a computation: store in a register.
 o If it's data fetched from memory: load into a register.
o If storing to memory: write data from register to memory.

5. Increment PC

 What happens: The Program Counter (PC) is incremented to point to the next
instruction in memory.
 Usually, it increases by the size of one instruction (e.g., +4 bytes in a 32-bit system).
 In case of jumps or branches, the PC may be modified based on the instruction.

Full Cycle Example

Let’s walk through an example instruction:

assembly
ADD R1, R2, R3 ; R3 = R1 + R2
Step Action
Fetch Get ADD R1, R2, R3 from memory using PC
Decode Identify opcode = ADD, operands = R1, R2, destination = R3
Execute ALU adds contents of R1 and R2
Store Save result into R3
Increment PC Move to next instruction (PC = PC + 4)

Summary

Stage Key Action

Fetch Get the next instruction from memory
Decode Interpret opcode and operands
Execute Perform the operation (ALU or memory)
Store Write the result back to register/memory
Increment PC Prepare to fetch the next instruction

5. Demonstration Using Simulators

5.1 Use of Simulators in Computer Architecture

 Simulators provide virtual environments to understand internal operations of CPUs.

 Benefits:
o Safe and controlled learning.
o Visual representation of execution.
o Step-by-step tracking.

5.2 Popular Simulators

 Little Man Computer (LMC):

 o Simplified model with mailbox memory, simple ISA.
o Instructions: ADD, SUB, STA, LDA, BRA, BRZ, BRP, IN, OUT, HLT
o Demonstrates fetch-decode-execute cycle.
 Logisim:
o Digital logic circuit simulator.
o Useful for designing and testing processor logic gates, memory, buses.
 EduMIPS64:
o Simulates a MIPS64 processor.
o Teaches RISC architecture, pipeline, registers, etc.
 CPUlator:
o ARMv7 and Nios II simulator for embedded systems.
o Useful for understanding assembly and C interaction with hardware.

5.3 Sample Simulation with LMC

Instruction sequence to add two numbers:

assembly
IN // Take input to accumulator
STA 99 // Store at location 99
IN // Take another input
ADD 99 // Add value from location 99
OUT // Output result
HLT // Halt program

Execution:

 Shows how inputs are stored, added, and output.

 Visual feedback of register values and memory state.

6. Summary

 Computer architecture and organisation form the foundation of all computing

systems.
 Hardware components include CPU, memory, I/O, and buses.
 ISA bridges the gap between software and hardware, enabling instruction execution.
 Simulators like LMC and Logisim provide hands-on learning to understand instruction
processing and data flow.

7. Suggested Activities

 Lab Exercise: Simulate a basic program in LMC that adds two numbers and stores the
result.
 Discussion: Compare RISC vs. CISC architectures and their modern relevance.
 Assignment: Design a 4-instruction ISA and simulate basic arithmetic operations.

8. Recommended Readings

 Patterson, D. A., & Hennessy, J. L. (2017). Computer Organization and Design: The
Hardware/Software Interface (5th ed.). Morgan Kaufmann.
 Null, L., & Lobur, J. (2014). The Essentials of Computer Organization and Architecture
(4th ed.). Jones & Bartlett Learning.