UNIT 3

Control Unit: Instruction types, formats, instruction cycles and sub cycles (fetch
and execute etc),
micro operations, execution of a complete instruction. Program Control, Reduced
Instruction Set
Computer, Pipelining. Hardwire and micro programmed control: micro
programme sequencing,
concept of horizontal and vertical microprogramming.

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 UNIT-3 Control Unit

Instructions

Instructions are a set of machine language instructions that Input-Output instruction

a particular processor understands and executes. A
computer performs tasks on the basis of the instruction
provided.

An instruction comprises of groups called fields. These

fields include:
Just like the Register-reference instruction, an Input-
Output instruction does not need a reference to memory
o The Operation code (Opcode) field which
and is recognized by the operation code 111 with a 1 in the
specifies the operation to be performed.
leftmost bit of the instruction. The remaining 12 bits are
o The Address field which contains the location of
the operand, i.e., register or memory location. used to specify the type of the input-output operation or
test performed.
o The Mode field which specifies how the operand
will be located.
 Instruction formats

Instruction formats refer to the way instructions are

encoded and represented in machine language. There are
A basic computer has three instruction code formats which several types of instruction formats, including zero, one,
are: two, and three-address instructions.
Each type of instruction format has its own advantages
1. Memory - reference instruction and disadvantages in terms of code size, execution time,
2. Register - reference instruction and flexibility. Modern computer architectures typically
3. Input-Output instruction use a combination of these formats to provide a balance
between simplicity and power.
Memory - reference instruction Instruction Fields
The most common fields are:
 The operation field specifies the operation to be
performed, like addition.
 Address field which contains the location of the
In Memory-reference instruction, 12 bits of memory is operand, i.e., register or memory location.
used to specify an address and one bit to specify the  Mode field which specifies how operand is to be
addressing mode 'I'. founded.
Types of Instructions
Based on the number of addresses, instructions are
Register - reference instruction
classified as:
NOTE: We will use the X = (A+B)*(C+D) expression to
showcase the procedure.
Zero Address Instructions
These instructions do not specify any operands or
addresses. Instead, they operate on data stored in
The Register-reference instructions are represented by the registers or memory locations implicitly defined by the
Opcode 111 with a 0 in the leftmost bit (bit 15) of the instruction. For example, a zero-address instruction
instruction. might simply add the contents of two registers together
without specifying the register names.
Note: The Operation code (Opcode) of an instruction
refers to a group of bits that define arithmetic and logic
operations such as add, subtract, multiply, shift, and
compliment.
A Register-reference instruction specifies an operation on
or a test of the AC (Accumulator) register.

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 Zero Address Instruction
LOAD A AC = M[A]
A stack-based computer does not use the address field in
the instruction. To evaluate an expression, it is first MUL T AC = AC * M[T]
converted to reverse Polish Notation i.e. Postfix
Notation. STORE X M[X] = AC
Expression: X = (A+B)*(C+D)
Two Address Instructions
Postfixed : X = AB+CD+*
These instructions specify two operands or addresses,
TOP means top of stack
which may be memory locations or registers. The
M[X] is any memory location
instruction operates on the contents of both operands, and
PUSH A TOP = A the result may be stored in the same or a different
location. For example, a two-address instruction might
PUSH B TOP = B add the contents of two registers together and store the
result in one of the registers.
This is common in commercial computers. Here two
ADD TOP = A+B
addresses can be specified in the instruction. Unlike
earlier in one address instruction, the result was stored in
PUSH C TOP = C the accumulator, here the result can be stored at different
locations rather than just accumulators, but require more
PUSH D TOP = D number of bit to represent the address.

ADD TOP = C+D

MUL TOP = (C+D)*(A+B)

Two Address Instruction
POP X M[X] = TOP
One Address Instructions Here destination address can also contain an operand.
These instructions specify one operand or address, which Expression: X = (A+B)*(C+D)
typically refers to a memory location or register. The R1, R2 are registers
instruction operates on the contents of that operand, and M[] is any memory location
the result may be stored in the same or a different
location. For example, a one-address instruction might MOV R1, A R1 = M[A]
load the contents of a memory location into a register.
This uses an implied ACCUMULATOR register for data ADD R1, B R1 = R1 + M[B]
manipulation. One operand is in the accumulator and the
other is in the register or memory location. Implied MOV R2, C R2 = M[C]
means that the CPU already knows that one operand is in
the accumulator so there is no need to specify it. ADD R2, D R2 = R2 + M[D]

MUL R1, R2 R1 = R1 * R2

One Address Instruction MOV X, R1 M[X] = R1

Three Address Instructions
Expression: X = (A+B)*(C+D) These instructions specify three operands or addresses,
LOAD A AC = M[A]
AC is accumulator which may be memory locations or registers. The
M[] is any memory location instruction operates on the contents of all three operands,
ADDis temporary
M[T] B AC location
= AC + M[B] and the result may be stored in the same or a different
location. For example, a three-address instruction might
STORE T M[T] = AC multiply the contents of two registers together and add
the contents of a third register, storing the result in a
LOAD C AC = M[C] fourth register.
This has three address fields to specify a register or a
ADD D AC = AC + M[D] memory location. Programs created are much short in
size but number of bits per instruction increases. These
instructions make the creation of the program much
easier but it does not mean that program will run much
faster because now instructions only contain more
information but each micro-operation (changing the
content of the register, loading address in the address bus
etc.) will be performed in one cycle only

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

  Flexible Operand Use: Increases programming
variety by offering more options for operand selection
and addressing modes.
Three Address Instruction  Intermediate Data Storage: May directly store
interim results, increasing some algorithms’ and
calculations’ efficiency.
Expression: X = (A+B)*(C+D)  Enhanced Code Readability: Produces code that is
R1, R2 are registers frequently easier to read and comprehend than one-
M[] is any memory location address instructions, which is beneficial for
ADD R1, A, B R1 = M[A] + M[B] maintenance and troubleshooting.
 Better Performance: Better overall performance can
result from these instructions because they minimize
ADD R2, C, D R2 = M[C] + M[D]
the amount of memory accesses required for certain
processes.
MUL X, R1, R2 M[X] = R1 * R2 Three-address instructions
Advantages of Zero-Address, One-Address, Two-  Direct Representation of Expressions: Reduces the
Address and Three-Address Instructions need for temporary variables and extra instructions by
Zero-address instructions enabling the direct representation of complicated
 Stack-based Operations: In stack-based expressions.
architectures, where operations implicitly employ the  Parallelism: Allows for the simultaneous fetching and
top items of the stack, zero-address instructions are processing of several operands, which facilitates
commonly used. parallelism in CPU architecture.
 Reduced Instruction Set: It reduces the complexity  Compiler Optimization: Makes it possible for more
of the CPU design by streamlining the instruction set, complex compiler optimizations to be implemented,
which may boost reliability. which improve execution efficiency by scheduling and
 Less Decoding Complexity: Especially helpful for reordering instructions.
recursive or nested processes, which are frequently  Reduced Instruction Count: May increase execution
used in function calls and mathematical computations. performance even with bigger instruction sizes by
 Efficient in Nested Operations: Less bits are perhaps lowering the overall number of instructions
required to specify operands, which simplifies the required for complicated processes.
logic involved in decoding instructions.  Improved Pipeline Utilization: More information in
 Compiler Optimization: Because stacks are based on each instruction allows CPU pipelines to be used more
stacks, several algorithms can take use of this to efficiently, increasing throughput overall.
improve the order of operations.  Better Register Allocation: Permits direct
One-address instructions manipulation of several registers inside a single
 Intermediate Complexity: Strikes a balance between instruction, enabling more effective usage of registers.
versatility and simplicity, making it more adaptable Disadvantages of Zero-Address, One-Address, Two-
than zero-address instructions yet simpler to Address and Three-Address Instructions
implement than multi-address instructions. Zero-address instructions
 Reduced Operand Handling: Compared to multi-  Stack Dependency: In contrast to register-based
address instructions, operand fetching is made simpler architectures, zero-address instructions might result in
by just needing to handle a single explicit operand. inefficiencies when it comes to operand access
 Implicit Accumulator: O ften makes use of an because of their heavy reliance on the stack.
implicit accumulator register, which can expedite up  Overhead of Stack Operations: Performance might
some operations’ execution and simplify designs in be negatively impacted by the frequent push and pop
other situations. actions needed to maintain the stack.
 Code Density: S maller code in comparison to two-  Limited Addressing Capability: The processing of
and three-address instructions, which may result in intricate data structures may become more difficult
more efficient use of memory and the instruction since they do not directly support accessing memory
cache. regions or registers.
 Efficient Use of Addressing Modes: Can make use of  Difficult to Optimize: Because operand access is
different addressing modes (such indexed, direct, and implied in stack-based designs, code optimization
indirect) to improve flexibility without adding a lot of might be more difficult.
complexity.  Harder to Debug: When compared to register-based
Two-address instructions operations, stack-based operations might be less
 Improved Efficiency: Allows for the execution of obvious and more difficult to debug.
operations directly on memory or registers, which One-address instructions
reduces the amount of instructions required for certain  Accumulator Bottleneck: Often uses an accumulator,
activities. which can act as a bottleneck and reduce efficiency
and parallelism.
 Increased Instruction Count: Multiple instructions
may be needed for complex processes, which would

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 increase the overall number of instructions and code size. 1. Fetch instruction from memory.
 Less Efficient Operand Access: There is just one 2. Decode the instruction.
operand that is specifically addressed, which might 3. Read the effective address from memory.
result in inefficient access patterns and extra data 4. Execute the instruction.
management instructions.
 Complex Addressing Modes: The instruction set and
decoding procedure get more complicated when
several addressing modes are supported.
 Data Movement Overhead: Moving data between
memory and the accumulator could need more
instructions, which would increase overhead.
Two-address instructions
 Operand Overwriting: Usually, the result overwrites
one of the source operands, which might lead to an
increase in the number of instructions needed to
maintain data.
 Larger Instruction Size: Because two-address
instructions are bigger than zero- and one-address
instructions, the memory footprint may be increased.
 Intermediate Results Handling: It is frequently
necessary to handle intermediate outcomes carefully,
which can make programming more difficult and
result in inefficiencies.
 Decoding Complexity: The design and performance 1. Fetch:
of the CPU may be impacted by the greater The processor copies the instruction data captured from the
complexity involved in decoding two addresses. RAM.
 Inefficient for Some Operations: The two-address
style could still be inefficient for some tasks, needing
2. Decode:
more instructions to get the desired outcome.
Decoded captured data is transferred to the unit for execution.
Three-address instructions
 Largest Instruction Size: Has the highest memory
requirements per instruction, which can put strain on 3. Execute:
the instruction cache and increase code size. Instruction is finally executed. The result is then registered in
 Complex Instruction Decoding: Three addresses to the processor or RAM (memory address).
decode adds complexity to the CPU architecture,
which might affect power consumption and  Interrupt SUB-Cycle:
performance. In interrupt cycle, an interrupt can occur any time during
 Increased Operand Fetch Time: Each instruction the program execution. Whenever it is caused, a series of
may execute more slowly if obtaining three operands events of events take place so that the instruction fetch
takes a long period. execute cycle can again resume after the OS calls the
 Higher Hardware Requirements: Has the potential routine to handle the interrupt. This cycle of fetching a
to raise cost and power consumption since it requires new instruction, decoding it and finally executing it
more advanced hardware to handle the higher operand continues until the computer is turned off.
handling and addressing capabilities.
 Power Consumption: Higher power consumption is a
crucial factor for devices that run on batteries since it
can be caused by more complicated instructions and
increased memory utilization.

 Instruction Cycle

A program residing in the memory unit of a computer consists

of a sequence of instructions. These instructions are
executed by the processor by going through a cycle for
each instruction.

In a basic computer, each instruction cycle consists of the

following phases:

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 To accommodate interrupts, an interrupt cycle is added to 1. Load: Moves data from memory into a register.
the instruction cycle as shown in figure. In the interrupt 2. Store: Saves data from a register back into memory.
cycle, the processor checks to see if any interrupts have 3. Add: Adds two values and stores the result in a
occurred, indicated by the presence of an interrupt signal. register.
If no interrupts are pending, the processor proceeds to the 4. Subtract: Subtracts one value from another and stores
fetch cycle and fetches the next instruction of the current the result in a register.
program. If an interrupt is pending, the processor does the 5. AND: Performs a logical AND operation on two
following: values and stores the result in a register.
6. OR: Performs a logical OR operation on two values
and stores the result in a register.
7. NOT: Reverses the bits of a value and stores the result
(i) It suspends execution of the current in a register.
program being executed and saves 8. Shift: Moves the bits of a value to the left or right
its context. This means saving the within a register.
address of the next instruction to be 9. Rotate: Rotates the bits of a value left or right in a
executed and any other data relevant register.
to the processor's current activity. How Micro-Operations Work?
(ii) (ii) It sets the program counter to Micro-operations are combined to perform more complex
the starting address of an interrupt instructions. For example, an addition instruction might
handler routine. The processor now involve several micro-operations:
proceeds to the fetch cycle and  First, a load operation to move values into registers.
fetches the first instruction in the  Then, an add operation to perform the calculation.
interrupt handler program, which  Finally, a store operation to save the result in memory
will service the interrupt. The
interrupt handler program is
generally part of the operating
system. Typically, this program  Execution of a Complete Instructions:
determines the nature of the
interrupt and performs whatever The execution of instructions refers to the process that
actions are needed. the CPU (Central Processing Unit) follows to execute
machine-level instructions, typically in the form of
assembly language or binary code. This process
 Micro Operation involves several stages that ensure that the instruction
is properly fetched, decoded, and executed.
Micro-operation refers to the smallest tasks performed
by the CPU’s control unit. These micro-operations helps Here's a breakdown of the typical steps involved in
to execute complex instructions. They involve simple the execution of a complete instruction in computer
tasks like moving data between registers, performing organization, focusing on the "fetch-decode-execute"
arithmetic calculations, or executing logic operations. cycle:
Each micro-operation is completed in a single clock
cycle. 1. Fetch Stage:

Below Figure shows the concept being discussed here. 1. Instruction Fetch: The instruction to be executed
is fetched from memory.
2. The CPU contains a Program Counter (PC),
which holds the address of the next instruction
to be executed.
3. The PC points to the memory location of the
instruction.
4. The CPU then loads the instruction from the
memory into the Instruction Register (IR).
5. After fetching the instruction, the Program
Counter is incremented (or updated) to point to
the next instruction.

Micro-operations are small tasks performed inside the 2. Decode Stage:

CPU. These tasks use data stored in the CPU’s registers
to do basic operations like math or logic tasks. They also 1. Instruction Decode: The CPU decodes the
help move data between registers or between memory fetched instruction to understand what operation
and registers. needs to be performed.
Examples of Micro-Operations

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 2. The control unit (CU) interprets the instruction Example of a Complete Instruction Execution:
in the Instruction Register (IR).
3. The instruction is usually in machine code, and
Let's look at a simple example using a basic arithmetic operation,
the control unit identifies the opcode (operation
such as adding two numbers in registers.
code) to determine the type of instruction (e.g.,
add, subtract, move data, jump).
4. It also identifies the operands (data or addresses)  Fetch: The CPU fetches the instruction ADD R1,
that will be used by the instruction. The R2, R3 (add the contents of registers R2 and R3,
operands might be in registers, memory and store the result in R1).
locations, or immediate values.
5. If the instruction involves a memory address, the 1. The Program Counter (PC) points to the memory
effective address may need to be calculated location of the ADD instruction.
(e.g., using index registers, or base and offset 2. The instruction is fetched and stored in the
addressing). Instruction Register (IR).

3. Execute Stage:  Decode: The control unit decodes the

instruction.
1. Execute: The CPU performs the operation
specified by the decoded instruction. 1. The opcode ADD is recognized.
2. If the instruction is an arithmetic or logic 2. The operands are identified: register R2 and R3.
operation, the Arithmetic Logic Unit (ALU) 3. The control unit prepares the ALU for an
performs the operation on the operands. addition operation and sets up the necessary
3. If it's a memory operation (e.g., load or store), control signals.
the CPU accesses the memory to read or write
data.  Execute: The ALU performs the addition.
4. If the instruction involves a jump or branch, the
CPU may modify the Program Counter based on 1. The contents of registers R2 and R3 are added
the instruction (e.g., jump to a new address). together.
5. For I/O operations, the CPU interacts with 2. The result is stored in a temporary register or
peripheral devices as per the instruction. directly placed into R1.

4. Memory Access (if needed):  Write-back: The result from the ALU (R2 + R3)
is written back to register R1.
1. For load or store operations, there may be a  Repeat: The program continues to the next
separate stage to interact with memory: instruction, and the cycle repeats.
2. If the instruction is a load, data is fetched from
memory and stored in a register.
3. If the instruction is a store, data from a register
is written to memory.
 Program Control Instructions

5. Write-back (if needed): Program Control Instructions are the machine code instructions
which are used to control the flow of execution of
1. Write-back: After the execution stage, the results instructions in the processor domain. These are important
of the computation (if any) are written back to in instilling on the processor how to execute a certain task,
the destination register or memory. access different programs and control the decision making
2. For most arithmetic operations, the result is on the basis of some conditions. They are commonly used
stored in a register. in assembly language and generated by high level language
3. For memory instructions, data may be written which is compiled into machine code form to enable the
back to memory. processor act in the desired manner.

6. Repeat Cycle: Types of Program Control Instructions

1. Compare Instruction
Compare instruction is specifically provided, which is similar to
The CPU then returns to the fetch stage and continues this
a subtract instruction except the result is not stored
cycle, fetching and executing the next instruction from
anywhere, but flags are set according to the result. Example:
memory until the program ends. CMP R1, R2 ;
2. Unconditional Branch Instruction
It causes an unconditional change of execution sequence

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 Example:  Simpler instructions: RISC processors use a smaller
JUMP L2 set of simple instructions, which makes them easier to
Mov R3, R1 goto L2 decode and execute quickly. This results in faster
3. Conditional Branch Instruction processing times.
A conditional branch instruction is used to examine the  Faster execution: Because RISC processors have a
values stored in the condition code register to determine simpler instruction set, they can execute instructions
whether the specific condition exists and to branch if it faster than CISC processors.
does.  Lower power consumption: RISC processors
Example: consume less power than CISC processors, making
Assembly Code : BE R1, R2, L1 them ideal for portable devices.
Compiler allocates R1 for x and R2 for y Disadvantages of RISC
High Level Code: if (x==y) goto L1;  More instructions required: RISC processors require
more instructions to perform complex tasks than CISC
4. Subroutines processors.
A subroutine is a program fragment that lives in user  Increased memory usage: RISC processors require
space, performs a well-defined task. It is invoked by more memory to store the additional instructions
another user program and returns control to the calling needed to perform complex tasks.
program when finished.  Higher cost: Developing and manufacturing RISC
Example: processors can be more expensive than CISC
CALL and RET processors.
Complex Instruction Set Architecture (CISC)
5. Halting Instructions The main idea is that a single instruction will do all
 NOP Instruction – NOP is no operation. It cause no loading, evaluating, and storing operations just like a
change in the processor state other than an multiplication command will do stuff like loading data,
advancement of the program counter. It can be used to evaluating, and storing it, hence it’s complex.
synchronize timing. Characteristics of CISC
 Complex instruction, hence complex instruction
 HALT – It brings the processor to an orderly halt, decoding.
remaining in an idle state until restarted by interrupt,  Instructions are larger than one-word size.
trace, reset or external action.  Instruction may take more than a single clock cycle to
6. Interrupt Instructions get executed.
Interrupt is a mechanism by which an I/O or an  Less number of general-purpose registers as
instruction can suspend the normal execution of operations get performed in memory itself.
processor and get itself serviced.  Complex Addressing Modes.
 RESET – It reset the processor. This may include any  More Data types.
or all setting registers to an initial value or setting Advantages of CISC
program counter to standard starting location.  Reduced code size: CISC processors use complex
 TRAP – It is non-maskable edge and level triggered instructions that can perform multiple operations,
interrupt. TRAP has the highest priority and vectored reducing the amount of code needed to perform a task.
interrupt.  More memory efficient: Because CISC instructions
 INTR – It is level triggered and maskable interrupt. It are more complex, they require fewer instructions to
has the lowest priority. It can be disabled by resetting perform complex tasks, which can result in more
the processor. memory-efficient code.
 Widely used: CISC processors have been in use for a
longer time than RISC processors, so they have a
 Reduced Instruction Set Architecture (RISC) larger user base and more available software.
Disadvantages of CISC
The main idea behind this is to simplify hardware by  Slower execution: CISC processors take longer to
using an instruction set composed of a few basic steps for execute instructions because they have more complex
loading, evaluating, and storing operations just like a instructions and need more time to decode them.
load command will load data, a store command will store  More complex design: CISC processors have more
the data. complex instruction sets, which makes them more
Characteristics of RISC difficult to design and manufacture.
 Simpler instruction, hence simple instruction  Higher power consumption: CISC processors
decoding. consume more power than RISC processors because of
 Instruction comes undersize of one word. their more complex instruction sets.
 Instruction takes a single clock cycle to get executed.
 More general-purpose registers.
 Simple Addressing Modes.  Pipelining
 Fewer Data types.
 A pipeline can be achieved. Pipelining is the process of accumulating instruction from
Advantages of RISC the processor through a pipeline. It allows storing and

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 executing instructions in an orderly process. It is also 3. Add or subtract mantissas
known as pipeline processing. Pipelining is a technique 4. Produce the result.
where multiple instructions are overlapped during Registers are used for storing the intermediate results
execution. Pipeline is divided into stages and these stages between the above operations.
are connected with one another to form a pipe like  Instruction Pipeline
structure. Instructions enter from one end and exit from In this a stream of instructions can be executed by
another end. Pipelining increases the overall instruction overlapping fetch, decode and execute phases of an
throughput. In pipeline system, each segment consists of instruction cycle. This type of technique is used to increase
an input register followed by a combinational circuit. The the throughput of the computer system. An instruction
register is used to hold data and combinational circuit pipeline reads instruction from the memory while previous
performs operations on it. The output of combinational instructions are being executed in other segments of the
circuit is applied to the input register of the next segment. pipeline. Thus we can execute multiple instructions
simultaneously. The pipeline will be more efficient if the
instruction cycle is divided into segments of equal
duration.
 hardwired and micro-programmed
Introduction :
The control unit is responsible for directing the flow of
data and instructions within the CPU. There are two main
approaches to implementing a control unit: hardwired
and micro-programmed.
Pipeline system is like the modern day assembly line setup A hardwired control unit is a control unit that uses a fixed
in factories. For example in a car manufacturing industry, set of logic gates and circuits to execute instructions. The
control signals for each instruction are hardwired into the
huge assembly lines are setup and at each point, there are control unit, so the control unit has a dedicated circuit for
robotic arms to perform a certain task, and then the car each possible instruction. Hardwired control units are
simple and fast, but they can be inflexible and difficult to
moves on ahead to the next arm. modify.
Types of Pipeline It is divided into 2 categories: On the other hand, a micro-programmed control unit is a
control unit that uses a microcode to execute instructions.
1. Arithmetic Pipeline The microcode is a set of instructions that can be
2. Instruction Pipeline modified or updated, allowing for greater flexibility and
ease of modification. The control signals for each
 Arithmetic Pipeline instruction are generated by a microprogram that is stored
Arithmetic pipelines are usually found in most of the in memory, rather than being hardwired into the control
unit.
computers. They are used for floating point operations,
1. Hardwired Control Unit: The control
multiplication of fixed point numbers etc hardware can be viewed as a state
machine that changes from one state to
. For example: The input to the Floating Point Adder
another in every clock cycle, depending
pipeline is: on the contents of the instruction
register, the condition codes, and the
X = A*2^a
external inputs. The outputs of the state
Y = B*2^b machine are the control signals. The
sequence of the operation carried out by
Here A and B are mantissas (significant digit of floating
this machine is determined by the
point numbers), while a and b are exponents. wiring of the logic elements and hence
named “hardwired”.
The floating point addition and subtraction is done in 4
 Fixed logic circuits that correspond directly to the
parts: Boolean expressions are used to generate the control
signals.
1. Compare the exponents.
 Hardwired control is faster than micro-programmed
2. Align the mantissas. control.

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 A controller that uses this approach can operate at
high speed. Micro-
 RISC architecture is based on the hardwired control Hardwired programmed
unit Control Unit Control Unit

Fixed set of Microcode stored

Implementation logic gates and in memory
circuits

Less flexible, More flexible,

Flexibility difficult to easier to modify
modify

Supports
Supports complex
limited
Instruction Set instruction sets
instruction
2. Micro-programmed Control Unit – sets
 The control signals associated with operations are
stored in special memory units inaccessible by the
programmer as Control Words. Complex design,
Simple design,
 Control signals are generated by a program that is Complexity of more difficult to
easy to
similar to machine language programs. Design implement
implement
 The micro-programmed control unit is slower in speed
because of the time it takes to fetch microinstructions
from the control memory. Slower operation
Some Important Terms due to microcode
Speed Fast operation
1. Control Word: A control word is a word whose decoding
individual bits represent various control signals.
2. Micro-routine: A sequence of control words
corresponding to the control sequence of a machine Easier to debug
Debugging and Difficult to
instruction constitutes the micro-routine for that and test
Testing debug and test
instruction.
3. Micro-instruction: Individual control words in this
micro-routine are referred to as microinstructions. Larger size,
4. Micro-program: A sequence of micro-instructions is Smaller size,
Size and Cost higher cost
called a micro-program, which is stored in a ROM or lower cost
RAM called a Control Memory (CM).
5. Control Store: the micro-routines for all instructions
Difficult to Easier to upgrade
in the instruction set of a computer are stored in a Maintenance and
upgrade and and maintain
special memory called the Control Store. Upgradability
maintain

Types of Micro-programmed Control Unit – Based on

the type of Control Word stored in the Control Memory
(CM), it is classified into two types :
1. Horizontal Micro-programmed Control Unit :
The control signals are represented in the decoded binary
format that is 1 bit/CS. Example: If 53 Control signals
are present in the processor then 53 bits are required.
More than 1 control signal can be enabled at a time.
 It supports longer control words.
 It is used in parallel processing applications.
 It allows a higher degree of parallelism. If degree is n,
n CS is enabled at a time.
The differences between hardwired and micro-  It requires no additional hardware(decoders). It means
programmed control units: it is faster than Vertical Microprogrammed.
 It is more flexible than vertical microprogrammed
2. Vertical Micro-programmed Control Unit :
The control signals are represented in the encoded binary

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

 format. For N control signals- Log2(N) bits are  Control Memory : Control memory is a type of
required. memory which contains addressable storage registers.
 It supports shorter control words. Data is temporarily stored in control memory. Control
 It supports easy implementation of new control signals memory can be accessed quicker than main memory.
therefore it is more flexible.
 It allows a low degree of parallelism i.e., the degree of
parallelism is either 0 or 1.
 Requires additional hardware (decoders) to generate  Horizontal Micro-programmed Control unit
control signals, it implies it is slower than horizontal
microprogrammed. With the help of decoded binary format, we can represent
 It is less flexible than horizontal but more flexible the control signals in the horizontal micro-programmed
than that of a hardwired control unit. control unit, i.e., 1bit/CS. Here, n bit encoding is needed
for 'n' control signals. With the help of a single control
point, each bit is identified in the horizontal micro-
 Micro Instructions Sequencer programmed CU. This Control point is used to show that
Micro Instructions Sequencer is a combination of all the corresponding micro-operation is going to be executed.
hardware for selecting the next micro-instruction address. In this control unit, every micro-program needs less
The micro-instruction in control memory contains a set of number of micro-instructions. The several resources can be
bits to initiate micro-operations in computer registers and controlled simultaneously with the help of each and every
other bits to specify the method by which the address is micro-instruction. It also has a bigger advantage, i.e., it has
obtained. the ability to utilize more efficient hardware.
Implementation of Micro Instructions Sequencer
A higher degree of parallelism is provided by the
horizontal CU. This parallelism contains a separate control
field and a minimum number of encoding. In the
horizontal CU, the task to develop the micro-programs
with the help of using resources efficiently and optimally
is very complex. Each control bit in the horizontal micro-
programmed control unit is independent to each other.
That's why this CU provides great flexibility. The
horizontal microinstruction contains more information as
compared to the vertical microinstruction because
horizontal microinstruction contains a greater length.

 Control Address Register(CAR) : Control address

register receives the address from four different paths.
For receiving the addresses from four different paths,
Multiplexer is used.
Fig: Horizontal Microcode
 Multiplexer : Multiplexer is a combinational circuit
which contains many data inputs and single data
output depending on control or select inputs. Vertical Micro-programmed CU
 Branching : Branching is achieved by specifying the
branch address in one of the fields of the micro In contrast to the Horizontal micro-programmed CU, a
instruction. Conditional branching is obtained by higher degree of encoding and variable format can be
using part of the micro-instruction to select a specific applied in the vertical micro-programmed control unit.
status bit in order to determine its condition. With the help of encoded binary format, we can represent
 Mapping Logic : An external address is transferred the control signals in the vertical micro-programmed CU.
into control memory via a mapping logic circuit. Here, log2n bit encoding is needed for 'n' control signals.
 Incrementer : Incrementer increments the content of A single micro-operation is represented by every vertical
the control address register by one, to select the next micro-instruction. With the help of vertical CU, we can
micro-instruction in sequence. shorten the length of microinstruction as well as prevent
 Subroutine Register (SBR) : The return address for a the length of microinstruction from being directly affected
subroutine is stored in a special register called by the increasing memory capacity.
Subroutine Register whose value is then used when
the micro-program wishes to return from the The microinstruction is performed with the help of a code,
subroutine. and this code will be translated into the individual control
signals with the help of a decoder. Because here we only
specified the micro-operation that will be performed and

NOTES BY KAVYA SINGH DEPARTMENT OF CSE

the fields of microinstruction are fully utilized. There are encoding. encoding so that it can
basically 4 to 6 fields, and these fields approximately require reduce the control world's
16 to 32 bits per instruction. As compared to the horizontal length.
micro-programmed, we can easily write the vertical micro-
programmed. Same as the conventional machine language
format, the vertical microinstruction also contains a few A higher degree of
The low degree of
operands and one operation. So we can easily use the parallelism is allowed by
parallelism is allowed by the
vertical microinstruction for micro- programming. the horizontal micro-
vertical micro-programmed
programmed CU. If there
CU. That means there can
are is 'n' number of degrees,
either be 0 or 1 degree of
n control signals will be
parallelism.
enabled at a time.

The vertical
microinstruction is used by
The horizontal the vertical micro-
microinstruction is used by programmed CU. Here each
the horizontal micro- action will be performed
programmed CU. Here with the help of a code, and
control line is attacked with this code will be translated
Fig: Vertical Microcode every bit of the control field. into the individual control
signals with the help of a
Differences between Horizontal and Vertical Micro- decoder.
programmed CU

There are various differences between the vertical

programmed CU and horizontal programmed CU, which
are described as follows:

Horizontal Micro- Vertical Micro-

programmed CU programmed CU

This control unit is able to This control unit is able to

support longer control support shorter control
words. words.

In this CU, we need

additional hardware to
In this CU, we don't need
generate the control signals.
any type of additional
These types of hardware
hardware.
must be in the form of
decoders.

Compared to the vertical Compared to the horizontal

micro-programmed control micro-programmed control
unit, this control unit is less unit, this control unit
flexible. is more flexible.

Compared to the vertical Compared to the horizontal

micro-programmed control micro-programmed control
unit, this control unit unit, this control unit
is faster. is slower.

Compared to the vertical Compared to the horizontal

micro-programmed control micro-programmed control
unit, this control unit unit, this control unit
makes less use of ROM makes more use of ROM

NOTES BY KAVYA SINGH DEPARTMENT OF CSE