96
L T P J C
U18ECI6203 VLSI AND HDL PROGRAMMING
3 0 2 0 4
Course Outcomes (COs):
After successful completion of this course, the students should be able to
CO1: Implement and verify combinational and sequential circuits using Verilog HDL(K3,S4)
CO2: Explain working and electrical properties of MOSFET (K2)
CO3: Discuss the CMOS fabrication Technologies (K2)
CO4: Apply CMOS logics in complex digital circuits(K3)
CO5: Discuss various implementation strategies (K2)
Pre-requisites:
1. U18ECI3203-Digital System Design
CO/PO Mapping:
(S/M/W indicates strength of correlation) S-Strong, M-Medium, W-Weak
PROGRAMME OUTCOMES
Cos
PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12 PSO1 PSO2
CO1 M M S
CO2 S M W W S
CO3 S M S W S
CO4 M M S S S
CO5 M M M S S
Course Assessment Methods
DIRECT
Continuous Assessment Test I, II
Assignment
End Semester Examination
INDIRECT
Course-end survey
VERILOG HDL 09 Hours
VLSI Circuit Design Flow-Hierarchical modeling concepts – Basic concepts: Lexical conventions – Datatypes
– Modules and ports. Gate level modeling – Dataflow modeling – Behavioral modeling – Design examples of
Combinational and Sequential circuits – Switch level modeling – Tasks and Functions – UDP concepts.
MOS CIRCUIT DESIGN PROCESS 09 Hours
Introduction of MOSFET: Symbols, Enhancement mode-Depletion mode transistor operation – Threshold
voltage derivation – Drain current Vs voltage derivation – Second order Effects. NMOS and CMOS
inverter – Determination of pull up to pull down ratio.
Signature of BOS Chairperson, ECE
97
MOS TECHNOLOGY 09 Hours
Chip Design Hierarchy – IC Layers – Photolithography and Pattern Transfers – Basic MOS Transistors –
CMOS Fabrication: n-well – p-well – twin tub – Latch up and prevention (SOI) –BiCMOS technology-
Submicron CMOS Process –– CMOS Design Rules: Lambda based design rules-Stick diagrams-Masks and
Layout
CMOS LOGIC GATES & OTHER COMPLEX CIRCUITS 10 Hours
CMOS Static Logic – Transmission Gate Logic – Tri-State Logic – Pass Transistor Logic – Dynamic CMOS
Logic – Domino CMOS Logic, NORA CMOS Logic, Differential Cascade Voltage Switch (DCVS) Logic,
True Single Phase Clock (TSPC) Dynamic Logic. Arithmetic Circuits – Design of Adders: -carry select-carry
save. Design of multipliers: Array multipliers.
VLSI IMPLEMENTATION STRATEGIES 08 Hours
Introduction to FPGA-FPGA Design Flow- FPGA architecture- FPGA Devices- Xilinx 4000 series.
Introduction to SoC: Driving Forces for SoC – Components of SoC – Design flow of SoC –
Hardware/Software nature of SoC – Design Trade-offs – SoC Applications.
REFERENCES:
1. Douglas A. Pucknell, “Basic VLSI Systems and Circuits”, Prentice Hall of India, 3rd Edition, reprint
2008.
2. Michael J Flynn and Wayne Luk, “Computer system Design: System-on-Chip”, Wiley-India,
3. Samir Palnitkar, “Verilog HDL – Guide to Digital Design and Synthesis”, Pearson Education, 3rd
Edition, 2003.
4. John P. Uyemura, “Introduction to VLSI Circuits and Systems”, John Wiley & Sons, Reprint 2009
5. Weste&Eshraghian, “Principles of CMOS VLSI Design”, Addison Wesley, 2nd Edition, 2008.
6. John P Uyemura, “Chip Design for Submicron VLSI: CMOS layout and simulation”, Thomson
India Edition, 2010.
7. Wayne Wolf, “FPGA-Based System Design”, First Edition, Prentice Hall India Private Limited, 2004.
LAB COMPONENT:
LIST OF EXPERIMENTS:
I Design and Simulation using HDL
1. Combinational logic circuits.
2. Sequential logic circuits.
3. VLSI multipliers.
4. Memory
5. FSM
II Implementation using Xilinx FPGA
1. FPGA Implementation of any two combinational and sequential circuits
III System design using IP core generator
IV Layout generation for VLSI circuits using backend tools.
Theory: 45 Tutorial: 0 Practical: 30 Project: 0 Total: 75 Hour
Signature of BOS Chairperson, ECE
