PRELIMINARY TECHNICAL DATA

= Low Power, +2.3 V to +5.5 V, 50 MHz

Complete DDS
Preliminary Technical Data AD9834
FEATURES Capability for phase modulation and frequency modula-
+2.3 V to +5.5 V Power Supply tion is provided. Frequency accuracy can be controlled to
50 MHz Speed one part in 0.25 billion. Modulation is effected by loading
Low Jitter Clock Output registers through the serial interface.
Sine Output/Triangular Output The AD9834 offers the user a variety of output
Serial Loading waveforms. The SIN ROM can be bypassed so that a
Power-Down Option linear up/down ramp is output from the DAC. If the SIN
Narrowband SFDR > 72 dB ROM is not by-passed, a sinusoidal output is available.
20 mW Power Consumption at 3 V Also, if a clock output is required, the MSB of the DAC
20-Pin TSSOP data can be output, or the on-chip comparator can be
APPLICATIONS used.
Test Equipment The digital section is driven by an on-board regulator
Slow Sweep Generator which steps down the applied DVDD to +2.5 V when
DDS Tuning DVDD exceeds +2.5 V. The analog and digital sections
Digital Modulation are independent and can be run from different power
supplies e.g. AVDD can equals 5 V with DVDD equal to
GENERAL DESCRIPTION
3 V, etc.
The AD9834 is a numerically controlled oscillator The AD9834 has a power-down pin (SLEEP) which
employing a phase accumulator, a SIN ROM and a allows external control of a power-down mode. Sections of
10-bit D/A converter integrated on a single CMOS the device which are not being used can be powered down to
chip. Clock rates up to 50 MHz are supported with a minimise the current consumption e.g. the DAC can be
power supply from 2.3 V to 5.5 V. powered down when a clock output is being generated.
The part is available in a 20-pin TSSOP package.
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND DGND DVDD CAP/2.5V REFOUT FS ADJUST

On-Board
MCLK Reference
Regulator
FullScale
Control COMP
VCC
FSELECT 2.5V

28 Bit
FREQ0 REG Phase 12 IOUT
10-Bit
Accumulator SIN MUX
MUX DAC
(28 Bit) ROM IOUTB
28 Bit
FREQ1 REG
MSB
MUX DIV BY
12 Bit PHASE0 REG 2
MUX
12 Bit PHASE1 REG
MUX
SIGN BIT OUT
16 Bit Control
Register

Serial Interface COMPARATOR VIN

&
Control Logic
AD9834
FSYNC SCLK SDATA PSELECT SLEEP RESET
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 PRELIMINARY TECHNICAL DATA
AD9834
Ω;
SPECIFICATIONS1 (VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V; TA = TMIN to TMAX; RSET = 6.8 kΩ;
RLOAD = 200 Ω for IOUT and IOUTB unless otherwise noted)
Parameter Min Typ Max Units Test Conditions/Comments
SIGNAL DAC SPECIFICATIONS
Resolution 10 Bits
Update Rate (fMAX) 50 MSPS
IOUT Full Scale 2.8 mA
Output Compliance2 0.8 V
DC Accuracy:
Integral Nonlinearity ±1 LSB
Differential Nonlinearity ±0.5 LSB

DDS SPECIFICATIONS
Dynamic Specifications:
Signal to Noise Ratio 50 dB fMCLK = 50 MHz, fOUT = fMCLK/4096
Total Harmonic Distortion -53 dBc fMCLK = 50 MHz, fOUT = fMCLK/4096
Spurious Free Dynamic Range (SFDR):
Wideband (0 to Nyquist) 50 dBc fMCLK = 50 MHz, fOUT = fMCLK/7
NarrowBand (± 200 kHz) 72 dBc fMCLK = 50 MHz, fOUT = fMCLK/7
Clock Feedthrough –55 dBc
Wake Up Time 1 ms

COMPARATOR
Input Voltage Range 1 V p-p ac-coupled internally
Input Capacitance 10 pF
Input HighPass Cutoff Frequency 4 MHz
Input DC Resistance 1 MΩ
Input DC Current 10 µA

OUTPUT BUFFER
Output Rise/Fall Time 20 ns Using a 15 pF Load
Output Jitter 100 ps rms When DAC data MSB is output

VOLTAGE REFERENCE
Internal Reference 1.116 1.2 1.284 V 1.2 V ± 7%
REFOUT Input Impedance3 1 KΩ
Reference TC 100 ppm/°C

LOGIC INPUTS
VINH, Input High Voltage DVDD –0.9 V +3.6 V to +5.5 V Power Supply
DVDD - 0.5 V +2.7 V to +3.6 V Power Supply
2 V +2.3 V to + 2.7 V Power Supply
VINL, Input Low Voltage 0.9 V +3.6 V to +5.5 V Power Supply
0.5 V +2.3 V to + 3.6 V Power Supply
IINH, Input Current 1 µA
CIN, Input Capacitance 10 pF

POWER SUPPLIES fMCLK = 50 MHz, fOUT = fMCLK/7

AVDD 2.3 5.5 V
DVDD 2.3 5.5 V
I AA 4 5 mA
I DD 4 0.5 + 0.04/MHz mA
IAA + IDD4 7 10 mA 3 V Power Supply
10 15 mA 5 V Power Supply
Low Power Sleep Mode4 0.25 mA DAC and Internal Clock Powered Down
NOTES
1
Operating temperature range is as follows: B Version: –40°C to +85°C; typical specifications are at 25ⴗC
2
Guaranteed by Design.
3
Applies when REFOUT is sourcing current. The impedance is higher when REFOUT is sinking current.
4
Measured with the digital inputs static and equal to 0 V or DVDD.
Specifications subject to change without notice. There is 95% test coverage of the digital circuitry.

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 PRELIMINARY TECHNICAL DATA
AD9834
RSET
6.8 K
100nF 10nF

CAP/2.5V REFOUT FS
ADJUST AVDD

10nF
ON-BOARD FULL-SCALE COMP
REGULATOR
REFERENCE CONTROL

12
SIN IOUT
10-BIT DAC
ROM
200R 20pF
AD9834

Figure 1. Test Circuit With which Specifications are tested.

TIMING CHARACTERISTICS1 (VDD = +2.3 V to +5.5 V; AGND = DGND = 0 V, unless otherwise noted)

Parameter Limit at TMIN to TMAX Units Test Conditions/Comments

t1 20 ns min MCLK Period
t2 8 ns min MCLK High Duration
t3 8 ns min MCLK Low Duration
t4 25 ns min SCLK Period
t5 10 ns min SCLK High Duration
t6 10 ns min SCLK Low Duration
t7 5 ns min FSYNC to SCLK Falling Edge Setup Time
t8 10 ns min FSYNC to SCLK Hold Time
t4 - 5 ns max
t9 5 ns min Data Setup Time
t10 3 ns min Data Hold Time
t11 8 ns min FSELECT, PSELECT Setup Time Before MCLK Rising Edge
t11A* 8 ns min FSELECT, PSELECT Setup Time After MCLK Rising Edge
1
Guaranteed by design, not production tested.
*See Pin Description Section.

t1
MCLK MCLK

t2 t 11 t 11A
t3
FSELECT, VALID DATA VALID DATA VALID DATA
PSELECT

Figure 2. Master Clock

Figure 3. Control Timing

t5 t4
SCLK

t7 t6 t8
FSYNC

t10
t9

SDATA D15 D14 D2 D1 D0 D15 D14

Figure 4. Serial Timing

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 PRELIMINARY TECHNICAL DATA
AD9834
ABSOLUTE MAXIMUM RATINGS* Storage Temperature Range . . . . . . . . . –65°C to +150°C
(TA = +25°C unless otherwise noted) Maximum Junction Temperature . . . . . . . . . . . . . +150°C
AVDD to AGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V TSSOP Package
DVDD to DGND . . . . . . . . . . . . . . . . . . . . –0.3 V to +6 V θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . 143°C/W
AVDD to DVDD . . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V θJC Thermal Impedance . . . . . . . . . . . . . . . . . . . 45°C/W
AGND to DGND. . . . . . . . . . . . . . . . . . –0.3 V to +0.3 V Lead Temperature, Soldering (10 sec) . . . . . . . . . 300°C
CAP/2.5V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.75 V IR Reflow, Peak Temperature . . . . . . . . . . . . . . . 220°C
Digital I/O Voltage to DGND –0.3 V to DVDD + 0.3 V *Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
Analog I/O Voltage to AGND –0.3 V to AVDD + 0.3 V damage to the device. This is a stress rating only and functional operation of the device
at these or any other conditions above those listed in the operational sections of this
Operating Temperature Range specification is not implied. Exposure to absolute maximum rating conditions for
Industrial (B Version) . . . . . . . . . . . . . . –40°C to +85°C extended periods may affect device reliability.

ORDERING GUIDE

Model Temperature Range Package Description Package Option

AD9834BRU – 40°C to +85°C 20-Pin TSSOP (Thin Shrink Small Outline Package ) RU-20
EVAL-AD9834EB Evaluation Board

PIN CONFIGURATION

FS ADJUST 1 20 IOUTB
REFOUT 2 AD9834 19 IOUT
COMP 3 18 AGND
AVDD 4 O 17 VIN
TOP VIEW
DVDD 5 (Not to Scale) 16 SIGNBITOUT
CAP/+2.5V 6 15 FSYNC
DGND 7 14 SCLK
MCLK 8 13 SDATA
FSELECT 9 12 SLEEP
PSELECT 10 11 RESET

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD9834 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.

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 PRELIMINARY TECHNICAL DATA
AD9834
PIN FUNCTIONS DESCRIPTIONS

Pin # Mnemonic Function

ANALOG SIGNAL AND REFERENCE

1 FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This
determines the magnitude of the full-scale DAC current. The relationship between RSET and
the full-scale current is as follows:
IOUTFULL-SCALE = 18 x VREFOUT/RSET
VREFOUT = 1.20 V nominal, RSET = 6.8 kΩ typical
2 REFOUT Voltage Reference Output. The AD9834 has an internal 1.20 V reference, which is made
available at this pin.
3 COMP A DAC Bias Pin. This pin is used for de-coupling the DAC bias voltage.
17 VIN Input to comparator. The comparator can be used to generate a square wave from the
sinusoidal DAC output. The DAC output should be filtered appropriately before being applied
to the comparator to improve jitter. When bits OPBITEN and SIGNPIB in the control
register are set to 1, the comparator input is connected to VIN.
19,20 IOUT, IOUTB Current Output. This is a high impedance current source. A load resistor of nominally 200 Ω
should be connected between IOUT and AGND. IOUTB should preferably be tied through an
external load resistor of 200 Ω to AGND but can be tied directly to AGND. A 20pF capacitor
to AGND is also recommended to prevent clock feedthrough.
POWER SUPPLY
4 AVDD Positive power supply for the analog section. AVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between AVDD and AGND.
5 DVDD Positive power supply for the digital section. DVDD can have a value from +2.3 V to +5.5 V.
A 0.1 µF decoupling capacitor should be connected between DVDD and DGND.
6 CAP/2.5V The digital circuitry operates from a +2.5 V power supply. This +2.5 V is generated from
DVDD using an on board regulator (when DVDD exceeds +2.7 V). The regulator requires a
decoupling capacitor of typically 100 nF which is connected from CAP/2.5V to DGND. If
DVDD is equal to or less than +2.7 V, CAP/2.5 V should be shorted to DVDD.
7 DGND Digital Ground.
18 AGND Analog Ground.
DIGITAL INTERFACE AND CONTROL
8 MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the
frequency of MCLK. The output frequency accuracy and phase noise are determined by this
clock.
9 FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is
used in the phase accumulator. The frequency register to be used can be selected using the pin
FSELECT or the bit FSEL. When the bit FSEL is being used to select the frequency register,
this pin, FSELECT, should be tied to CMOS high or low.
10 PSELECT Phase Select Input. PSELECT controls which phase register, PHASE0 or PHASE1, is added
to the phase accumulator output. The phase register to be used can be selected using the pin
PSELECT or the bit PSEL. When the phase registers are being controlled by the bit PSEL,
this pin, PSELECT, should be tied to CMOS high or low.
11 RESET Active high digital input. RESET resets appropriate internal registers to zero which
corresponds to an analog output of midscale. RESET does not affect any of the addressable
registers.
12 SLEEP Active high digital input. When this pin is high, the DAC is powered down. This pin has the
same function as control bit SLEEP12.
13 SDATA Serial Data Input. The 16-bit serial data word is applied to this input.
14 SCLK Serial Clock Input. Data is clocked into the AD9834 on each falling SCLK edge.
15 FSYNC Active Low Control Input. This is the frame synchronisation signal for the input data. When
FSYNC is taken low, the internal logic is informed that a new word is being loaded into
the device.
16 SIGN BIT OUT Logic Output. The comparator output is available on this pin or, alternatively, the MSB from
the NCO can be output on this pin. Setting bit OPBITEN in the control register to 1 enables
this output pin. Bit SIGNPIB determines whether the comparator output or the MSB from
the NCO is output on the pin.

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 PRELIMINARY TECHNICAL DATA
AD9834
Typical Performance Characteristics

TPC 1. Typical Current Consumption TPC 2. Narrow Band SFDR vs. MCLK TPC 3. Wide Band SFDR vs. MCLK
vs. MCLK Frequency Frequency Frequency

TPC 4. Wide Band SFDR vs. fOUT/fMCLK TPC 5. SNR vs. MCLK Frequency TPC 6. SNR vs. fOUT/fMCLK for
for Various MCLK Frequencies Various MCLK Frequencies

TPC 7. Wake-Up Time vs. TPC 8. VREFOUT vs. Temperature

Temperature

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 PRELIMINARY TECHNICAL DATA
AD9834
Typical Performance Characteristics

TPC 9. fMCLK = 10 MHz; fOUT = 2.4 kHz; TPC 10. fMCLK = 10 MHz; fOUT = 1.43 kHz TPC 11. fMCLK = 10 MHz; fOUT = 3.33 kHz
Frequency Word = 000FBA9 = fMCLK/7 ; = fMCLK/3 ;
Frequency Word = 2492492 Frequency Word = 5555555

TPC 12. fMCLK = 50 MHz; fOUT = 12 kHz; TPC 13. fMCLK = 50 MHz; fOUT = 120 kHz; TPC 14. fMCLK = 50 MHz; fOUT = 1.2
Frequency Word = 000FBA9 Frequency Word = 009D496 MHz; Frequency Word = 0624DD3

TPC 15. fMCLK = 50 MHz; fOUT = 4.8 TPC 16. fMCLK = 50 MHz; TPC 17. fMCLK = 50 MHz;
MHz; Frequency Word = 189374C fOUT = 7.143 MHz = fMCLK/7 ; fOUT = 16.667 MHz = fMCLK/3 ;
Frequency Word = 2492492 Frequency Word = 5555555

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 PRELIMINARY TECHNICAL DATA
AD9834
TERMINOLOGY THEORY OF OPERATION
Integral Nonlinearity Sine waves are typically thought of in terms of their
This is the maximum deviation of any code from a magnitude form a(t) = sin (ωt). However, these are
straight line passing through the endpoints of the transfer nonlinear and not easy to generate except through piece
function. The endpoints of the transfer function are zero wise construction. On the other hand, the angular
scale, a point 0.5 LSB below the first code transition information is linear in nature. That is, the phase angle
(000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB rotates through a fixed angle for each unit of time. The
above the last code transition (111 . . . 10 to 111 . . . 11). angular rate depends on the frequency of the signal by the
The error is expressed in LSBs. traditional rate of ω = 2πf.
Differential Nonlinearity
MAGNITUDE
This is the difference between the measured and ideal 1 +1
LSB change between two adjacent codes in the DAC. A
specified differential nonlinearity of ±1 LSB maximium ensures
0
monotonicity.
Output Compliance
-1
The output compliance refers to the maximum voltage
that can be generated at the output of the DAC to meet PHASE
2π
the specifications. When voltages greater than that speci-
fied for the output compliance are generated, the AD9834
may not meet the specifications listed in the data sheet. 0

Spurious Free Dynamic Range

Along with the frequency of interest, harmonics of the Figure 5. Sine Wave
fundamental frequency and images of the these frequencies
are present at the output of a DDS device. The spurious Knowing that the phase of a sine wave is linear and given
free dynamic range (SFDR) refers to the largest spur or a reference interval (clock period), the phase rotation for
harmonic which is present in the band of interest. The that period can be determined.
wide band SFDR gives the magnitude of the largest har- ∆Phase = ωδt
monic or spur relative to the magnitude of the fundamental Solving for ω
frequency in the 0 to Nyquist bandwidth. The narrow band
SFDR gives the attenuation of the largest spur or harmonic ω = ∆Phase/δt = 2πf
in a bandwidth of ±200 kHz about the fundamental fre- Solving for f and substituting the reference clock
quency. frequency for the reference period (1/fMCLK = δt)
Total Harmonic Distortion f = ∆Phase x fMCLK/2π
Total Harmonic Distortion (THD) is the ratio of the rms The AD9834 builds the output based on this simple
sum of harmonics to the rms value of the fundameltal. For equation. A simple DDS chip can implement this
the AD9834, THD is defined as: equation with three major subcircuits:
THD = 20 log√(V22 + V32 + V42 + V52 + V62)/V1 Numerical Controlled Oscillator + Phase Modulator
where V1 is the rms amplitude of the fundamental and V2, SIN ROM
V3, V4, V5 and V6 are the rms amplitudes of the second Digital- to- Analog Convertor.
through thre sixth harmonic. Each of these sub-circuits are discussed in the following
Signal-to-Noise Ratio (SNR) section.
S/N is the ratio of the rms value of the measured output
signal to the rms sum of all other spectral components
below the Nyquist frequency, excluding the first six har-
monics and dc. The value for SNR is expressed in
decibels.
Clock Feedthrough
There will be feedthrough from the MCLK input to the
analog output. Clock feedthrough refers to the magnitude
of the MCLK signal relative to the fundamental frequency
in the AD9834’s output spectrum.

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 PRELIMINARY TECHNICAL DATA
AD9834
CIRCUIT DESCRIPTION
The AD9834 is a fully integrated Direct Digital Synthesis DAC. This requires the SIN ROM to have two bits of
(DDS) chip. The chip requires one reference clock, one phase resolution more than the 10-bit DAC.
low precision resistor and eight decoupling capacitors to The SIN ROM is enabled using bits MODE and
provide digitally created sine waves up to 25 MHz. In OPBITEN in the control register. This is explained fur-
addition to the generation of this RF signal, the chip is ther in Table 14.
fully capable of a broad range of simple and complex Digital-to-Analog Converter
modulation schemes. These modulation schemes are fully The AD9834 includes a high impedance current source
implemented in the digital domain allowing accurate and 10-bit DAC, capable of driving a wide range of loads.
simple realization of complex modulation algorithms us- Full-scale output current can be adjusted, for optimum
ing DSP techniques. power and external load requirements, through the use of
The internal circuitry of the AD9834 consists of the fol- a single external resistor (RSET).
lowing main sections: a Numerical Controlled Oscillator The DAC can be configured for either single-ended or
(NCO), Frequency and Phase Modulators, SIN ROM, a differential operation. IOUT and IOUTB can be con-
Digital-to-Analog Converter, a Comparator and a nected through equal external resistors to AGND to
Regulator. develop complementary output voltages. The load resis-
Numerical Controlled Oscillator + Phase Modulator tors can be any value required, as long as the full-scale
This consists of two frequency select registers, a phase voltage developed across it does not exceed the voltage
accumulator, two phase offset registers and a phase offset compliance range. Since full-scale current is controlled by
adder. The main component of the NCO is a 28-bit phase RSET, adjustments to RSET can balance changes made to the
accumulator which assembles the phase component of the load resistors.
output signal. Continuous time signals have a phase range Comparator
of 0 to 2␲. Outside this range of numbers, the sinusoid The AD9834 can be used to generate synthesised digital
functions repeat themselves in a periodic manner. The clock signals. This can be done by using the on-board
digital implementation is no different. The accumulator self-biasing comparator, which converts the DAC's sinu-
simply scales the range of phase numbers into a multibit soidal signal to a square wave. The output from the DAC
digital word. The phase accumulator in the AD9834 is may be filtered externally before being applied to the
implemented with 28 bits. Therefore, in the AD9834, 2␲ comparator input. The comparator reference voltage is the
= 228. Likewise, the ∆Phase term is scaled into this range time-average of the signal applied to VIN. The comparator
of numbers 0 < ∆Phase < 228 – 1. Making these substitu- can accept a signal of 1 Vpp. As the comparator's input is
tions into the equation above ac-coupled, to operate correctly as a zero crossing
f = ∆Phase x fMCLK/228 dectector, it requires a minimum input frequency of 3
MHz. The comparator's output will be a square wave with
where 0 < ∆Phase < 228 - 1. an amplitude from 0 V to DVDD.
The input to the phase accumulator (i.e., the phase step) To enable the comparator, bits SIGNPIB and OPBITEN
can be selected either from the FREQ0 Register or in the control resister are set to '1'. This is explained fur-
FREQ1 Register and this is controlled by the FSELECT ther in Table 13.
pin or the FSEL bit. NCOs inherently generate Regulator
continuous phase signals, thus avoiding any output The AD9834 has separate power supplies for the analog
discontinuity when switching between frequencies. and digital section. AVDD provides the power supply
Following the NCO, a phase offset can be added to required for the analog section, while DVDD provides the
perform phase modulation using the 12-bit Phase power supply for the digital section. Both of these supplies
Registers. The contents of one of these phase registers is can have a value of +2.3V to +5.5V, and are independant
added to the most significant bits of the NCO. The of each other e.g. the analog section can be operated at 5V
AD9834 has two Phase registers, the resolution of these and the digital section can be operated at 3V or vice versa.
registers being 2π/4096.
SIN ROM The internal digital section of the AD9834 is operated at
To make the output from the NCO useful, it must be 2.5 V. An on-board regulator steps down the voltage ap-
converted from phase information into a sinusoidal value. plied at DVDD to 2.5 V. The digital inteface (serial port)
Since phase information maps directly into amplitude, the of the AD9834 is also operated from DVDD. These digi-
SIN ROM uses the digital phase information as an ad- tal signals are level shifted within the AD9834 to make
dress to a look-up table, and converts the phase them 2.5V compatible.
information into amplitude. Although the NCO contains a When the applied voltage at the DVDD pin of the
28-bit phase accumulator, the output of the NCO is trun- AD9834 is equal to or less than 2.5V, the pins CAP/2.5V
cated to 12 bits. Using the full resolution of the phase and DVDD should be tied together, thus by-passing the
accumulator is impractical and unnecessary as this would on-board regulator.
require a look-up table of 228 entries. It is necessary only
to have sufficient phase resolution such that the errors due
to truncation are smaller than the resolution of the 10-bit

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 PRELIMINARY TECHNICAL DATA
AD9834
FUNCTIONAL DESCRIPTION
signal will appear at the DAC output 7 MCLK cycles after
Serial Interface RESET is set to 0.
The AD9834 has a standard 3-wire serial interface, which
is compatible with SPI, QSPI, MICROWIRE and DSP Latency
interface standards. Associated with each operation is a latency. When the pins
Data is loaded into the device as a 16-bit word under the FSELECT and PSELECT change value there is a pipe-
control of a serial clock input, SCLK. The timing dia- line delay before control is transfered to the selected
gram for this operation is given in Figure 4. register. When the timing specifications t11 and t11A are
The FSYNC input is a level triggered input that acts as a met (see figure 3) FSELECT and PSELECT have laten-
frame synchronisation and chip enable. Data can only be cies of 7 MCLK cycles. When the timing specifications
transferred into the device when FSYNC is low. To start t11 and t11A are not met, the latency is increased by one
the serial data transfer, FSYNC should be taken low, ob- MCLK cycle.
serving the minimum FSYNC to SCLK falling edge setup Similarly there is a latency associated with each asynchro-
time, t7. After FSYNC goes low, serial data will be shifted nous write operation. If a selected frequency/phase register
into the device's input shift register on the falling edges of is loaded with a new word there is a delay of 7 to 8 MCLK
SCLK for 16 clock pulses. FSYNC may be taken high cycles before the analog output will change. (There is an
after the sixteenth falling edge of SCLK, observing the uncertainty of one MCLK cycle as it depends on the posi-
minimum SCLK falling edge to FSYNC rising edge time, tion of the MCLK rising edge when the data is loaded into
t8. Alternatively, FSYNC can be kept low for a multiple of the destination register.)
16 SCLK pulses, and then brought high at the end of the The negative transition of the RESET and SLEEP func-
data transfer. In this way, a continuous stream of 16 bit tions are sampled on the internal falling edge of MCLK,
words can be loaded while FSYNC is held low, FSYNC therefore also have a latency associated with them.
only going high after the 16th SCLK falling edge of the
last word loaded. The Control Register
The SCLK can be continuous or, alternatively, the SCLK The AD9834 contains a 16-bit control register which sets
can idle high or low between write operations. up the AD9834 as the user wishes to operate it. All control
Powering up the AD9834 bits, except MODE, are sampled on the internal negative
The flow chart in Figure 7 shows the operating routine for edge of MCLK.
the AD9834. When the AD9834 is powered up, the part Table 2, on the following page, describes the individual
should be reset. This will reset appropriate internal regis- bits of the control register. The different functions and the
ters to zero to provide an analog output of midscale. To various output options from the AD9834 are described in
avoid spurious DAC outputs while the AD9834 is being more detail in the section following Table 2.
initialized, the RESET bit/pin should be set to 1 until the To inform the AD9834 that you wish to alter the contents
part is ready to begin generating an output. RESET does of the Control register, D15 and D14 must be set to '0' as
not reset the phase, frequency or control registers. These shown below.
registers will contain invalid data and, therefore, should be
set to a known value by the user. The RESET bit/pin Table 1. Control Register
should then be set to 0 to begin generating an output. A
D15 D14 D13 D0
0 0 CONTROL BITS

SLEEP12
AD9834
SLEEP1
SIN (Low Power) IOUT
0
Phase ROM MUX
Accumulator 1 10 - Bit DAC IOUTB
(28 Bit)

COMPARATOR VIN
MODE + OPBITEN

1
Div 1 MUX DIGITAL
by 2 MUX 0 OUTPUT SIGN BIT OUT
0 (enable)
DIV2

SIGNPIB
OPBITEN

Figure 6. Function of Control Bits

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 PRELIMINARY TECHNICAL DATA
AD9834
Table 2. Description of bits in the Control Register

Bit Name Function

D13 B28 Two write operations are required to load a complete word into either of the Frequency registers.
B28 = '1' allows a complete word to be loaded into a frequency register in two consecutive
writes. The first write contains the 14 LSBs of the frequency word and the next write will
contain the 14 MSBs. The first two bits of each sixteen-bit word define the frequency register to
which the word is loaded, and should therefore be the same for both of the consecutive writes.
Refer to table 6 for the appropriate addresses. The write to the frequency register occurs after both
words have been loaded, so the register never holds an intermediate value. An example of a com-
plete 28-bit write is shown in table 7.
When B28 = '0' the 28-bit frequency register operates as 2 14-bit registers, one containing the 14
MSBs and the other containing the 14 LSBs. This means that the 14 MSBs of the frequency
word can be altered independent of the 14 LSBs and vice versa. To alter the 14 MSBs or the 14
LSBs, a single write is made to the appropriate Frequency address. The control bit D12 (HLB)
informs the AD9834 whether the bits to be altered are the 14 MSBs or 14 LSBs.
D12 HLB This control bit allows the user to continuously load the MSBs or LSBs of a frequency regiser
while ignoring the remaining 14 bits. This is useful if the complete 28 bit resolution is not re-
quired. HLB is used in conjunction with D13 (B28). This control bit indicates whether the 14 bits
being loaded are being transferred to the 14 MSBs or 14 LSBs of the addressed frequency regis-
ter. D13 (B28) must be set to '0' to be able to change the MSBs and LSBs of a frequency word
seperately. When D13 (B28) = '1', this control bit is ignored.
HLB = '1' allows a write to the 14 MSBs of the addressed frequency register.
HLB = '0' allows a write to the 14 LSBs of the addressed frequency register.
D11 FSEL The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase
accumulator. See table 4 on selecting a frequency register.
D10 PSEL The PSEL bit defines whether the PHASE0 register or the PHASE1 register data is added to the
output of the phase accumulator. See Table 5 on selecting a phase register.
D9 PIN/SW Functions that select frequency and phase registers, reset internal registers, and power down the
DAC can be implemented using either software or hardware. PIN/SW selects the source of
control for these functions.
PIN/SW = '1' implies that the functions are being controlled using the appropriate control pins.
PIN/SW = '0' implies that the functions are being controlled using the appropriate control bits.
D8 RESET RESET = '1' resets internal registers to zero, which corresponds to an analog output of midscale.
RESET = '0' disables Reset. This function is explained further in Table 11.
D7 SLEEP1 When SLEEP1 = '1', the internal MCLK clock is disabled. The DAC output will remain at its
present value as the NCO is no longer accumulating.
When SLEEP1 = '0' MCLK is enabled. This function is explained further in Table 12.
D6 SLEEP12 SLEEP12 = '1' powers down the on-chip DAC. This is useful when the AD9834 is used to output
the MSB of the DAC data.
SLEEP12 = '0' implies that the DAC is active. This function is explained further in Table 12.
D5 OPBITEN The function of this bit is to control whether there is an output at the pin SIGN BIT OUT. This
bit should remain at '0' if the user is not using the pin SIGN BIT OUT.
OPBITEN = '1' enables the pin SIGN BIT OUT.
When OPBITEN equals 0, the SIGN BIT OUT output buffer is put into a high impedance state
and, therefore, no output is available at the SIGN BIT OUT pin.
D4 SIGNPIB The function of this bit is to control what is output at the pin SIGN BIT OUT.
When SIGNPIB = '1', the on board comparator is connected to SIGN BIT OUT. After filtering
the sinusoidal output from the DAC, the waveform can be applied to the comparator to generate a
square waveform. This is explained futher in Table 13.
When SIGNPIB = '0', the MSB (or MSB/2) of the DAC data is connected to the pin SIGN BIT
OUT. The bit DIV2 controls whether it is the MSB or MSB/2 that is ouput.
D3 DIV2 DIV2 is used in association with SIGNPIB and OPBITEN. This is fully explained in Table 13.
When DIV2 = '1', the digital output is passed directly to the SIGN BIT OUT pin.
When DIV2 = '0', the digital output/2 is passed directly to the SIGN BIT OUT pin.
D2 Reserved This bit must always be set to 0.
D1 MODE The function of this bit is to control what is output at the IOUT/IOUT pins. This bit should be
set to '0' if the control bit OPBITEN = '1'.
When MODE = '1', the SIN ROM is bypassed, resulting in a ramp output from the DAC.
When MODE = '0' the SIN ROM is used to convert the phase information into amplitude infor-
mation which results in a sinusoidal signal at the output (See table 14).
D0 Reserved This bit must always be set to 0.

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 PRELIMINARY TECHNICAL DATA
AD9834
The Frequency and Phase Resisters
The AD9834 contains 2 frequency registers and 2 phase The FSELECT and PSELECT pins are sampled on the
registers. These are described in Table 3 below. internal falling edge of MCLK. It is recommended that
the data on these pins does not change within a time win-
Table 3. Frequency/Phase Registers dow of the falling edge of MCLK (see Figure 3 for
timing). If FSELECT/PSELECT changes value when a
Register Size Description falling edge occurs, there is an uncertainty of one MCLK
cycle as to when control is transferred to the other fre-
FREQ0 28 Bits Frequency Register 0. When FSEL quency/phase register.
bit or FSELECT pin = 0, this regis-
ter defines the output frequency as a The flow charts in Figures 8 and 9 show the routine for
fraction of the MCLK frequency. selecting and writing to the frequency and phase registers
FREQ1 28 Bits Frequency Register 1. When FSEL of the AD9834.
bit or FSELECT pin = 1, this regis- Writing to a Frequency Register:
ter defines the output frequency as a When writing to a frequency register, bits D15 and D14
fraction of the MCLK frequency. give the address of the frequency register.
PHASE0 12 Bits Phase Offset Register 0. When PSEL
bit or PSELECT pin = 0, the con- Table 6. Frequency Register Bits
tents of this register are added to the
output of the phase accumulator. D15 D14 D13 D0
PHASE1 12 Bits Phase Offset Register 1. When PSEL 0 1 MSB 14 FREQ0 REG BITS LSB
bit or PSELECT pin = 1, the con- 1 0 MSB 14 FREQ1 REG BITS LSB
tents of this register are added to the
output of the phase accumulator. If the user wishes to alter the entire contents of a fre-
quency register, two consecutive writes to the same
address must be performed, as the frequency registers are
The analog output from the AD9834 is 28 bits wide. The first write will contain the 14 LSBs
fMCLK/228 x FREQREG while the second write will contain the 14 MSBs. For this
where FREQREG is the value loaded into the selected mode of operation, the control bit B28 (D13) should be
frequency register. This signal will be phase shifted by set to 1. An example of a 28-bit write is shown in Table 7
2π/4096 x PHASEREG below.
where PHASEREG is the value contained in the selected
phase register. Table 7: Writing 3FFF0000 to FREQ0 REG
Access to the frequency and phase registers is controlled
by both the FSELECT/PSELECT pins and the FSEL/ SDATA input Result of input word
PSEL control bits. If the control bit PIN/SW = 1, the
0010 0000 0000 0000 Control word write (D15, D14 = 00);
pins controls the function, whereas if PIN/SW = 0, the
B28 (D13) = 1; HLB (D12) = X
bits control the function. This is outlined in tables 4 and 5
0100 0000 0000 0000 FREQ0 REG write (D15, D14 = 01);
below. If the FSEL/PSEL bits are being used, the pins
14 LSBs = 0000
should preferably be held at CMOS logic high or low.
0111 1111 1111 1111 FREQ0 REG write (D15, D14 = 01);
Control of the frequency/phase registers can be inter-
14 MSBs = 3FFF
changed from the pins to the bits.
In some applications, the user does not need to alter all 28
Table 4: Selecting a Frequency Register
bits of the frequency register. With coarse tuning, only
FSELECT FSEL PIN/SW Selected Register the 14 MSBs are altered while with fine tuning, only the
14 LSBs are altered. By setting the control bit B28 (D13)
0 X 1 FREQ0 REG to 0, the 28-bit frequency register operates as 2 14-bit
1 X 1 FREQ1 REG registers, one containing the 14 MSBs and the other con-
X 0 0 FREQ0 REG taining the 14 LSBs. This means that the 14 MSBs of the
X 1 0 FREQ1 REG frequency word can be altered independent of the 14 LSBs
and vice versa. Bit HLB (D12) in the control register
identifies which 14 bits are being altered. Examples of this
Table 5: Selecting a Phase Register are shown over.
PSELECT PSEL PIN/SW Selected Register

0 X 1 PHASE0 REG
1 X 1 PHASE1 REG
X 0 0 PHASE0 REG
X 1 0 PHASE1 REG

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 PRELIMINARY TECHNICAL DATA
AD9834
Table 8: Writing 3FFF to the 14 LSBs of FREQ1 REG The Sleep Function

SDATA input Result of input word Sections of the AD9834 which are not in use can be pow-
ered down minimise power consumption. This is done
0000 0000 0000 0000 Control word write (D15, D14 = 00); using the Sleep Function. The parts of the chip that can
B28 (D13) = 0; HLB (D12) = 0, i.e. LSBs be powered down are the Internal clock and the DAC.
1011 1111 1111 1111 FREQ1 REG write (D15, D14 = 10); The DAC can be powered down through hardware or
14 LSBs = 3FFF software. The pin/bits required for the Sleep Function are
outlined in Table 12.
Table 9: Writing 3FFF to the 14 MSBs of FREQ0 REG Table 12: Applying the SLEEP Function
SDATA input Result of Input word SLEEP SLEEP1 SLEEP12 PIN/SW Result
0001 0000 0000 0000 Control word write (D15, D14 = 00); pin bit bit bit
B28 (D13) = 0; HLB (D12) = 1, i.e. MSBs 0 X X 1 No powerdown
0111 1111 1111 1111 FREQ0 REG write (D15, D14 = 01); 1 X X 1 DAC Powered Down
14 MSBs = 3FFF X 0 0 0 No powerdown
X 0 1 0 DAC Powered Down
Writing to a Phase Register: X 1 0 0 Internal Clock disabled
When writing to a phase register, bits D15 and D14 are X 1 1 0 Both the DAC powered
set to 11. Bit D13 identifies which phase register is being down and the Internal
loaded. Clock disabled

Table 10. Phase Register Bits DAC Powered Down: This is useful when the AD9834 is
used to output the MSB of the DAC data only. In this
D15 D14 D13 D12 D11 D0
case, the DAC is not required so it can be powered down
1 1 0 X MSB 12 PHASE0 BITS LSB to reduce power consumption.
1 1 1 X MSB 12 PHASE1 BITS LSB Internal Clock disabled: When the internal clock of the
AD9834 is disabled the DAC output will remain at its
present value as the NCO is no longer accumulating. New
The RESET Function frequency, phase and control words can be written to the
The RESET function resets appropriate internal registers part when the SLEEP1 control bit is active. The
to zero to provide an analog output of midscale. RESET synchronising clock is still active which means that the
does not reset the phase, frequency or control registers. selected frequency and phase registers can also be changed
When the AD9834 is powered up, the part should be re- either at the pins or by using the control bits. Setting the
set. To reset the AD9834, set the RESET pin/bit to 1. To SLEEP1 bit equal to 0 enables the MCLK. Any changes
take the part out of reset, set the pin/bit to 0. A signal will made to the registers while SLEEP1 was active will be
appear at the DAC output 7 MCLK cycles after RESET is seen at the output after a certain latency.
set to 0. The effect of asserting the SLEEP pin is seen immediately
The RESET function is controlled by both the RESET at the output, i.e. the zero to one transition of this pin is
pin and the RESET control bit. If the control bit PIN/SW not sampled. However, the negative transition of SLEEP
= 0, the RESET bit controls the function, whereas if PIN/ is sampled on the internal falling edge of MCLK.
SW = 1, the pin control the function.
The SIGN BIT OUT Pin
Table 11: Applying RESET
The AD9834 offers a variety of outputs from the chip.
RESET pin RESET bit PIN/SW Result The digital outputs are available from the SIGN BIT
OUT pin. The available outputs are the comparator out-
0 X 1 No Reset Applied put or the MSB of the DAC data.
1 X 1 Internal Registers Reset This pin must be enabled before use. The enabling/dis-
X 0 0 No Reset Applied abling of this pin is controlled by the bit OPBITEN (D5)
X 1 0 Internal Registers Reset in the control register. When OPBITEN = 1, this pin is
enabled. Note that the MODE bit (D1) in the control
The effect of asserting the RESET pin is seen immedi- register should be set to '0' if OPBITEN = '1'.
ately at the output, i.e. the zero to one transition of this
pin is not sampled. However, the negative transition of
RESET is sampled on the internal falling edge of MCLK.

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 PRELIMINARY TECHNICAL DATA
AD9834
Comparator Output: The AD9834 has an on-board APPLICATIONS
comparator. To connect this comparator to the SIGN Because of the various output options available from the
BIT OUT pin, the SIGNPIB (D4) control bit must be set part, the AD9834 can be configured to suit a wide variety
to 1. After filtering the sinusoidal output from the DAC, of applications.
the waveform can be applied to the comparator to generate One of the areas where the AD9834 is suitable is in modu-
a square waveform. lation applications. The part can be used to perform
MSB from the NCO: The MSB from the NCO can be simple modulation such as FSK. More complex modula-
output from the AD9834. By setting the SIGNPIB (D4) tion schemes such as GMSK and QPSK can also be
control bit to 0, the MSB of the DAC data is available at implemented using the AD9834.
the SIGN BIT OUT pin. This is useful as a coarse clock In an FSK application, the two frequency registers of the
source. This square wave can also be divided by 2 before AD9834 are loaded with different values; one frequency
being output. The bit DIV2 (D3) in the control register will represent the space frequency while the other will
controls the frequency of this output from the SIGN BIT represent the mark frequency. The digital data stream is
OUT pin. fed to the FSELECT pin which will cause the AD9834 to
modulate the carrier frequency between the two values.
Table 13: Various Outputs from SIGN BIT OUT The AD9834 has two phase registers; this enables the part
to perform PSK. With phase shift keying, the carrier fre-
OPBITEN MODE SIGNPIB DIV2 SIGN BIT OUT quency is phase shifted, the phase being altered by an
Bit Bit Bit Bit Pin amount which is related to the bit stream being input to
the modulator.
0 X X X High Impedance
1 0 0 0 DAC data MSB / 2 The AD9834 is also suitable for signal generator applica-
1 0 0 1 DAC data MSB tions. With the on-board comparator, the device can be
1 0 1 0 Reserved used to generate a square wave.
1 0 1 1 Comparator Output With its low current consumption, the part is suitable for
1 1 X X Reserved applications in which it can be used as a local oscillator.

The IOUT/IOUTB Pins

The analog outputs from the AD9834 are available from
the IOUT/IOUTB pins. The available outputs are a
sinuoidal output or a ramp output.
Sinusoidal Output: The SIN ROM is used to convert the
phase information from the frequency and phase registers
into amplitude information which results in a sinusoidal
signal at the output. To have a sinusoidal output from the
IOUT/IOUTB pins set the bt MODE (D1) = 1.
Up/Down Ramp Output: The SIN ROM can be bypassed
so that the truncated digital output from the NCO is sent
to the DAC. In this case, the output is no longer sinusoi-
dal. The DAC will produce a ramp up/down function. To
have a ramp output from the IOUT/IOUTB pins set the
bt MODE (D1) = 0.
Note that the SLEEP pin/SLEEP12 bit must be 0 (i.e. the
DAC is enabled) when using these pins.

Table 14: Various Outputs from IOUT/IOUTB

OPBITEN Bit MODE Bit IOUT / IOUTB Pins

0 0 Sinusoid
0 1 Up/Down Ramp
1 0 Sinusoid
1 1 Reserved

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 PRELIMINARY TECHNICAL DATA
AD9834
DATA WRITE
See Figure 9

SELECT DATA
SOURCES
See Figure 10
INITIALISATION
See Figure 8 below
WAIT 7/8 MCLK
CYCLES
See Timing Diagram Fig. 2

DAC OUTPUT
VOUT = VREFOUT * 18 * RLOAD/RSET * (1+ (SIN(2p(FREQREG * FMCLK * t/228 + PHASEREG/212)))

YES
CHANGE PHASE? CHANGE PSEL/ YES
PSELECT?
NO NO
YES CHANGE FSEL/ YES CHANGE PHASE
CHANGE FREQUENCY?
FSELECT? REGISTER?

NO NO YES

CHANGE FREQ
REGISTER? CHANGE DAC OUTPUT
YES FROM SIN TO RAMP?
YES
NO
CONTROL CHANGE OUTPUT AT
REGISTER SIGN BIT OUT PIN?
WRTE? YES
NO

Figure 7. Flow Chart for AD9834 Initialisation and Operation

INITIALISATION

APPLY RESET
USING CONTROL USING PIN
BIT

(CONTROL REGISTER WRITE) (CONTROL REGISTER WRITE)

RESET = 1 SET RESET PIN = 1
PIN/SW = 1
PIN/SW = 0

WRITE TO FREQUENCY AND PHASE REGISTERS

FREQ0 REG = FOUT0 / fMCLK * 228
FREQ1 REG = FOUT1 / fMCLK * 228
PHASE 0 & PHASE1 REG = (PhaseShift * 212) / 2p

(See Figure 9 Below)

SET RESET = 0
SELECT FREQUENCY REGISTERS
SELECT PHASE REGISTERS

USING CONTROL
USING PIN
BIT

(CONTROL REGISTER WRITE) (APPLY SIGNALS AT PINS)

RESET bit = 0 RESET pin = 0

FSEL = Selected Freq Register FSELECT = Selected Freq Register
PSEL = Selected Phase Register PSELECT = Selected Phase Register
PIN/SW = 0

Figure 8. Initialisation

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 PRELIMINARY TECHNICAL DATA
AD9834

DATA WRITE

NO
NO WRITE TO PHASE
WRITE A FULL 28-BIT WORD WRITE 14 MSBs OR LSBs
TO A FREQUENCY REGISTER? TO A FREQUENCY REGISTER? REGISTER?

YES YES
YES
(CONTROL REGISTER WRITE)
(CONTROL REGISTER WRITE)
B28 (D13) = 0
B28 (D13) = 1
HLB (D12) = 0 / 1 (16 - Bit Write)

D15, D14 = 11
D13 = 0/1 (chooses the
phase register)
WRITE 2 CONSECUTIVE WRITE A 16-BIT WORD D12 = X
16-BIT WORDS D11 ... D0 = Phase Data
(See Tables 8 & 9 for
(See Table 7 for Example) examples)

WRITE TO ANOTHER
WRITE ANOTHER FULL WRITE 14 MSBs OR LSBs PHASE REGISTER?
YES YES
28 BITS TO A TO A
FREQUENCY REGISTER? FREQUENCY REGISTER? YES

NO
NO NO

Figure 9. Data Writes

SELECT DATA SOURCES

YES
FSELECT AND PSELECT SET FSELECT
PINS BEING USED? AND PSELECT

NO

(CONTROL REGISTER WRITE) (CONTROL REGISTER WRITE)

PIN/SW = 0 PIN/SW = 1
SET FSEL Bit
SET PSEL Bit

Figure 10. Selecting Data Sources

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 PRELIMINARY TECHNICAL DATA
AD9834
GROUNDING AND LAYOUT INTERFACING TO MICROPROCESSORS
The printed circuit board that houses the AD9834 should The AD9834 has a standard serial interface which allows
be designed so that the analog and digital sections are the part to interface directly with several microprocessors.
separated and confined to certain areas of the board. This The device uses an external serial clock to write the data/
facilitates the use of ground planes which can be separated control information into the device. The serial clock can
easily. A minimum etch technique is generally best for have a frequency of 40 MHz maximum. The serial clock
ground planes as it gives the best shielding. Digital and can be continuous or, it can idle high or low between
analog ground planes should only be joined in one place. write operations. When data/control information is being
If the AD9834 is the only device requiring an AGND to written to the AD9834, FSYNC is taken low and is held
DGND connection, then the ground planes should be low while the 16 bits of data are being written into the
connected at the AGND and DGND pins of the AD9834. AD9834. The FSYNC signal frames the 16 bits of infor-
If the AD9834 is in a system where multiple devices re- mation being loaded into the AD9834.
quire AGND to DGND connections, the connection AD9834 to ADSP-21xx Interface
should be made at one point only, a star ground point that
should be established as close as possible to the AD9834. Figure 12 shows the serial interface between the AD9834
and the ADSP-21xx. The ADSP-21xx should be set up to
Avoid running digital lines under the device as these will operate in the SPORT Transmit Alternate Framing Mode
couple noise onto the die. The analog ground plane should (TFSW = 1). The ADSP-21xx is programmed through
be allowed to run under the AD9834 to avoid noise cou- the SPORT control register and should be configured as
pling. The power supply lines to the AD9834 should use follows:
as large a track as is possible to provide low impedance Internal clock operation (ISCLK = 1)
paths and reduce the effects of glitches on the power sup- Active low framing (INVTFS = 1)
ply line. Fast switching signals such as clocks should be 16-bit word length (SLEN = 15)
shielded with digital ground to avoid radiating noise to Internal frame sync signal (ITFS = 1)
other sections of the board. Avoid crossover of digital and Generate a frame sync for each write (TFSR = 1).
analog signals. Traces on opposite sides of the board Transmission is initiated by writing a word to the Tx reg-
should run at right angles to each other. This will reduce ister after the SPORT has been enabled. The data is
the effects of feedthrough through the board. A microstrip clocked out on each rising edge of the serial clock and
technique is by far the best but is not always possible with clocked into the AD9834 on the SCLK falling edge.
a double-sided board. In this technique, the component
side of the board is dedicated to ground planes while sig-
nals are placed on the other side.
Good decoupling is important. The analog and digital
supplies to the AD9834 are independent and separately
pinned out to minimize coupling between analog and digi-
tal sections of the device. All analog and digital supplies
should be decoupled to AGND and DGND respectively
with 0.1 µF ceramic capacitors in parallel with 10 µF
tantalum capacitors. To achieve the best from the
decoupling capacitors, they should be placed as close as
possible to the device, ideally right up against the device.
Figure 11. ADSP2101/ADSP2103 to AD9834 Interface
In systems where a common supply is used to drive both
the AVDD and DVDD of the AD9834, it is recommended AD9834 to 68HC11/68L11 Interface
that the system’s AVDD supply be used. This supply Figure 13 shows the serial interface between the AD9834
should have the recommended analog supply decoupling and the 68HC11/68L11 microcontroller. The
between the AVDD pins of the AD9834 and AGND and microcontroller is configured as the master by setting bit
the recommended digital supply decoupling capacitors MSTR in the SPCR to 1 and, this provides a serial clock
between the DVDD pins and DGND. on SCK while the MOSI output drives the serial data line
SDATA. Since the microcontroller does not have a dedi-
cated frame sync pin, the FSYNC signal is derived from a
port line (PC7). The set up conditions for correct opera-
tion of the interface are as follows:
SCK idles high between write operations (CPOL = 0)
data is valid on the SCK falling edge (CPHA = 1).
When data is being transmitted to the AD9834, the
FSYNC line is taken low (PC7). Serial data from the
68HC11/68L11 is transmitted in 8-bit bytes with only 8
falling clock edges occuring in the transmit cycle. Data is
transmitted MSB first. In order to load data into the
AD9834, PC7 is held low after the first 8 bits are trans-
ferred and a second serial write operation is performed to
the AD9834. Only after the second 8 bits have been trans-

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 PRELIMINARY TECHNICAL DATA
AD9834
ferred should FSYNC be taken high again.
being applied to the AD9834. The interface to the
DSP56000/DSP56001 is similar to that of the DSP56002.

Figure 12. 68HC11/68L11 to AD9834 Interface

AD9834 to 80C51/80L51 Interface Figure 14. AD9834 to DSP56002 Interface
Figure 14 shows the serial interface between the AD9834
and the 80C51/80L51 microcontroller. The
microcontroller is operated in mode 0 so that TXD of the
80C51/80L51 drives SCLK of the AD9834 while RXD
drives the serial data line SDATA. The FSYNC signal is AD9834 EVALUATION BOARD
again derived from a bit programmable pin on the port
(P3.3 being used in the diagram). When data is to be The AD9834 Evaluation Board allows designers to evalu-
transmitted to the AD9834, P3.3 is taken low. The ate the high performance AD9834 DDS modulator with
80C51/80L51 transmits data in 8 bit bytes thus, only 8 minimum of effort.
falling SCLK edges occur in each cycle. To load the re- To prove that this device will meet the user's waveform
maining 8 bits to the AD9834, P3.3 is held low after the synthesis requirements, the user only require's a power-
first 8 bits have been transmitted and a second write op- supply, an IBM-compatible PC and a spectrum analyser
eration is initiated to transmit the second byte of data. along with the evaluation board.
P3.3 is taken high following the completion of the second The DDS evaluation kit includes a populated, tested
write operation. SCLK should idle high between the two AD9834 printed circuit board. The evaluation board in-
write operations. The 80C51/80L51 outputs the serial terfaces to the parallel port of an IBM compatible PC.
data in a format which has the LSB first. The AD9834 Software is available with the evaluation board which al-
accepts the MSB first (the 4 MSBs being the control in- lows the user to easily program the AD9834. A schematic
formation, the next 4 bits being the address while the 8 of the Evaluation board is shown in Figure 24. The soft-
LSBs contain the data when writing to a destination regis- ware will run on any IBM compatible PC which has
ter). Therefore, the transmit routine of the 80C51/80L51 Microsoft Windows95, Windows98 or Windows ME 2000
must take this into account and re-arrange the bits so that NT™ installed.
the MSB is output first.
Using the AD9834 Evaluation Board
The AD9834 Evaluation kit is a test system designed to
simplify the evaluation of the AD9834. An application
note is also available with the evaluation board and gives
full information on operating the evaluation board.
Prototyping Area
An area is available on the evaluation board for the user to
add additional circuits to the evaluation test set. Users
may want to build custom analog filters for the output or
add buffers and operational amplifiers to be used in the
final application.
Figure 13. 80C51/80L51 to AD9834 Interface
XO vs. External Clock
AD9834 to DSP56002 Interface The AD9834 can operate with master clocks up to
Figure 15 shows the interface between the AD9834 and 50MHz. A 50MHz oscillator is included on the evaluation
the DSP56002. The DSP56002 is configured for normal board. However, this oscillator can be removed and, if
mode asynchronous operation with a Gated internal clock required, an external CMOS clock connected to the part.
(SYN = 0, GCK = 1, SCKD = 1). The frame sync pin is Power Supply
generated internally (SC2 = 1), the transfers are 16 bits
wide (WL1 = 1, WL0 = 0) and the frame sync signal will Power to the AD9834 Evaluation Board must be provided
frame the 16 bits (FSL = 0). The frame sync signal is externally through pin connections. The power leads
available on pin SC2 but, it needs to be inverted before should be twisted to reduce ground loops.

REV PrM
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 PRELIMINARY TECHNICAL DATA
AD9834
DVDD AVDD
C1 C2
0.1µ F 0.1µ F
C13
1 0.01µ F LK4
2
SCLK AVDD
3
SDATA
4 6 5 4 C3
FSYNC DVDD C14
5 0.01µ F CAP DVDD AVDD 10nF
C6 3
J1 COMP
6 0.1µ F DVDD
1 2 C4
7 REFOUT
2 18 14 SCLK 0.1µ F
8 SCLK
9 4 16 13 SDATA 12 LK5
SDATA SLEEP
10
6 14 15 FSYNC 1 R4
11 FSYNC FSADJUST
12 8 12 11 6.8k
RESET RESET
13
14 C11 IOUTB
RESET 20
15
U2 U1 IOUTB
16 R1 R2 R6 C12
10K 10K AD9834 IOUT 200R
17 19
18 IOUT
PSELECT LK1 R5
19 10
PSELECT 200R C11
20
FSELECT 9 VIN 17 R7
21 FSELECT
LK2 300R
22
C11
23
8 16
24 MCLK SBOUT
SIGNBITOUT
25
26 SW DVDD DGND AGND
27 7 18 DVDD
J2 J3 AVDD
28
C8 C7 C9 C10
29
10µF 0.1µ F 0.1µ F 10µF
30 MCLK
LK3
31
DVDD
32 R3 50R 14
33 C5 DVDD
34 0.1µ F
35 U3
36 8
OUT

DGND
7

Figure 15. AD9834 Evaluation Board Layout

Integrated Circuits Links

U3 OSC XTAL 50 MHz Lk1 Lk2 Lk5 3 pin sil header
U1 AD9834BRU Lk3 Lk4 2 pin sil header
U2 74HCT244

Switch
Capacitors SW End Stackable Switch (SDC
C1 C2 C5 C6 C7 C9 C14 100nF Ceramic Capacitor Double Throw)
C3 C4 C13 10nF ceramic Capacitor
C8 C10 10uF Tantalum Capacitor
C11 C12 C15 C16 Option for extra Sockets
decoupling capacitors PSEL1; FSEL1; CLK1; Sub Minature BNC
IOUT; IOUTB; SBOUT; Connector

Connectors
Resistors J1 36-Pin Edge Connector
R1 R2 10 KΩ Resistor J2, J3 PCB Mounting Terminal
R3 51 Ω Resistor Block
R4 6.8 kΩ Resistor
R5 R6 200 Ω Resistor
R7 300 Ω Resistor

REV PrM
–19–
 PRELIMINARY TECHNICAL DATA
AD9834
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).

20-Lead Small Outline Package (TSSOP)

(RU-20)

0.260 (6.60)
0.252 (6.40)

20 11

0.177 (4.50)
0.169 (4.30)

0.256 (6.50)
0.246 (6.25)
1
10

0.006 (0.15) PIN 1

0.002 (0.05) 0.0433
(1.10)
MAX 8o 0.028 (0.70)
0.0256 (0.65) 0.0118 (0.30) 0o
SEATING 0.0079 (0.20) 0.020 (0.50)
BSC 0.0075 (0.19)
PLANE
0.0035 (0.090)

REV PrM
–20–