Dual Interface for

Flat Panel Displays

AD9882
FEATURES FUNCTIONAL BLOCK DIAGRAM
Analog Interface
140 MSPS Maximum Conversion Rate AD9882
Programmable Analog Bandwidth
ANALOG INTERFACE
0.5 V to 1.0 V Analog Input Range REF REFBYPASS
500 ps p-p PLL Clock Jitter at 140 MSPS 8 ROUT
RAIN CLAMP A/D
3.3 V Power Supply
Full Sync Processing
8 GOUT
Midscale Clamping GAIN CLAMP A/D

4:2:2 Output Format Mode

8 BOUT
Digital Interface BAIN CLAMP A/D

DVI 1.0 Compatible Interface DATACK

8
ROUT
SOGIN
112 MHz Operation HSYNC
SYNC HSOUT
PROCESSING AND 8
High Skew Tolerance of 1 Full Input Clock FILT CLOCK VSOUT GOUT
GENERATION
Sync Detect for “Hot Plugging” VSYNC SOGOUT
8
Supports High Bandwidth Digital Content Protection BOUT

APPLICATIONS SCL
DATACK
SERIAL REGISTER AND
RGB Graphics Processing SDA POWER MANAGEMENT MUXES
LCD Monitors and Projectors A0 HSOUT

Plasma Display Panels

VSOUT
Scan Converter DIGITAL INTERFACE
Microdisplays RX0+
SOGOUT
8 ROUT
Digital TV RX0–
RX1+ DVI GOUT
8
RX1– RECEIVER DE
RX2+ 8 BOUT
RX2–
RXC+ DATACK
GENERAL DESCRIPTION RXC–
DE
RTERM
The AD9882 offers designers the flexibility of an analog interface HSYNC
DDCSCL
and Digital Visual Interface (DVI) receiver integrated on a single DDCSDA
HDCP VSYNC
chip. Also included is support for High bandwidth Digital MCL
MDA
Content Protection (HDCP).
Analog Interface
The AD9882 is a complete 8-bit 140 MSPS monolithic analog
interface optimized for capturing RGB graphics signals from
personal computers and workstations. Its 140 MSPS encode Digital Interface
rate capability and full power analog bandwidth of 300 MHz The AD9882 contains a DVI 1.0 compatible receiver and supports
supports resolutions up to SXGA (1280 ¥ 1024 at 75 Hz). display resolutions up to SXGA (1280 ¥ 1024 at 60 Hz). The
The analog interface includes a 140 MHz triple ADC with receiver features an intra-pair skew tolerance of up to one full
internal 1.25 V reference, a Phase Locked Loop (PLL), and clock cycle.
programmable gain, offset, and clamp control. The user provides With the inclusion of HDCP, displays may now receive encrypted
only a 3.3 V power supply, analog input, and Hsync. Three- video content. The AD9882 allows for authentication of a video
state CMOS outputs may be powered from 2.2 V to 3.3 V. receiver, decryption of encoded data at the receiver, and renew-
The AD9882’s on-chip PLL generates a pixel clock from Hsync. ability of that authentication during transmission as specified by
Pixel clock output frequencies range from 12 MHz to 140 MHz. the HDCP v1.0 protocol.
PLL clock jitter is typically 500 ps p-p at 140 MSPS. The AD9882 Fabricated in an advanced CMOS process, the AD9882 is
also offers full sync processing for composite sync and Sync-on- provided in a space-saving 100-lead LQFP surface-mount plastic
Green (SOG) applications. package and is specified over the 0∞C to 70∞C temperature range.
REV. A

Information furnished by Analog Devices is believed to be accurate and

reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
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registered trademarks are the property of their respective companies. Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
AD9882–SPECIFICATIONS
ANALOG INTERFACE
(VD = 3.3 V, VDD = 3.3 V, ADC Clock = Maximum Conversion Rate, unless
ELECTRICAL CHARACTERISTICS otherwise noted.)

Test AD9882KST-100 AD9882KST-140

Parameter Temp Level Min Typ Max Min Typ Max Unit
RESOLUTION 8 8 Bits
DC ACCURACY
Differential Nonlinearity 25∞C I ± 0.5 +1.25/–1.0 ± 0.5 +1.35/–1.0 LSB
Full VI +1.35/–1.0 +1.45/–1.0 LSB
Integral Nonlinearity 25∞C I ± 0.5 ± 1.85 ± 0.5 ± 2.0 LSB
Full VI ± 2.0 ± 2.3 LSB
No Missing Codes Full VI Guaranteed Guaranteed
ANALOG INPUT
Input Voltage Range
Minimum Full VI 0.5 0.5 V p-p
Maximum Full VI 1.0 1.0 V p-p
Gain Tempco 25∞C V 100 100 ppm/∞C
Input Bias Current Full IV 1 1 mA
Input Full-Scale Matching Full VI 1.5 8.0 1.5 8.0 % FS
Offset Adjustment Range Full VI 46 49 56 46 49 56 % FS
REFERENCE OUTPUT
Output Voltage Full VI 1.20 1.25 1.32 1.20 1.25 1.32 V
Temperature Coefficient Full V ± 50 ± 50 ppm/∞C
SWITCHING PERFORMANCE1
Maximum Conversion Rate Full VI 100 140 MSPS
Minimum Conversion Rate Full IV 10 10 MSPS
Data to Clock Skew Full IV –0.5 +2.0 –0.5 +2.0 ns
Serial Port Timing
tBUFF Full VI 4.7 4.7 ms
tSTAH Full VI 4.0 4.0 ms
tDHO Full VI 0 0 ms
tDAL Full VI 4.7 4.7 ms
tDAH Full VI 4.0 4.0 ms
tDSU Full VI 250 250 ns
tSTASU Full VI 4.7 4.7 ms
tSTOSU Full VI 4.0 4.0 ms
Hsync Input Frequency Full IV 15 110 15 110 kHz
Maximum PLL Clock Rate Full VI 100 140 MHz
Minimum PLL Clock Rate Full IV 12 12 MHz
PLL Jitter 25∞C IV 500 7002 500 7002 ps p-p
Full IV 10002 10002 ps p-p
Sampling Phase Tempco Full IV 15 15 ps/∞C
DIGITAL INPUTS
Input Voltage, High (VIH) Full VI 2.6 2.6 V
Input Voltage, Low (VIL) Full VI 0.8 0.8 V
Input Current, High (IIH) Full IV –1.0 –1.0 mA
Input Current, Low (IIL) Full IV +1.0 +1.0 mA
Input Capacitance 25∞C V 3 3 pF
1
DIGITAL OUTPUTS
Output Voltage, High (VOH) Full IV VDD – 0.1 VDD – 0.1 V
Output Voltage, Low (VOL) Full IV 0.4 0.4 V
Duty Cycle, DATACK Full IV 45 50 55 45 50 55 %
Output Coding Binary Binary

–2– REV. A
 AD9882
Test AD9882KST-100 AD9882KST-140
Parameter Temp Level Min Typ Max Min Typ Max Unit
1
POWER SUPPLY
VD Supply Voltage Full IV 3.15 3.3 3.45 3.15 3.3 3.45 V
VDD Supply Voltage Full IV 2.2 3.3 3.6 2.20 3.3 3.6 V
PVD Supply Voltage Full IV 3.15 3.3 3.45 3.15 3.3 3.45 V
ID Supply Current (VD) 25∞C V 162 181 mA
IDD Supply Current (VDD)3 25∞C V 47 63 mA
IPVD Supply Current (PVD) 25∞C V 19 21 mA
Total Supply Current Full VI 228 237 265 274 mA
Power-Down Supply Current Full VI 30 35 30 35 mA
DYNAMIC PERFORMANCE
Analog Bandwidth, Full Power 25∞C V 300 300 MHz
Signal-to-Noise Ratio (SNR) 25∞C V 44 43 dB
fIN = 2.3 MHz
Crosstalk Full V 55 55 dBc
THERMAL CHARACTERISTICS
␪JA Junction-to-Ambient4 V 43 43 ∞C/W
NOTES
1
Drive Strength = 11.
2
VCO Range = 10, Charge Pump Current = 110, PLL Divider = 1693.
3
DATACK Load = 15 pF, Data Load = 5 pF.
4
Simulated typical performance with package mounted to a four-layer board.
Specifications subject to change without notice.

REV. A –3–
AD9882
DIGITAL INTERFACE
ELECTRICAL CHARACTERISTICS (VD = 3.3 V, VDD = 3.3 V, Clock = Maximum, unless otherwise noted.)

Test AD9882KST
Parameter Conditions Temp Level Min Typ Max Unit
RESOLUTION 8 Bits
DC DIGITAL I/O Specifications
High Level Input Voltage (VIH) Full VI 2.6 V
Low Level Input Voltage (VIL) Full VI 0.8 V
High Level Output Voltage (VOH) Full IV 2.4 V
Low Level Output Voltage (VOL) Full IV 0.4 V
Output Leakage Current (IOL) High Impedance Full IV –10 +10 mA
DC SPECIFICATIONS
Output High Drive Output Drive = High Full V 11 mA
(IOHD)(VOUT = VOH) Output Drive = Med Full V 8 mA
Output Drive = Low Full V 5 mA
Output Low Drive Output Drive = High Full V –7 mA
(IOLD)(VOUT = VOL) Output Drive = Med Full V –6 mA
Output Drive = Low Full V –5 mA
DATACK High Drive Output Drive = High Full V 28 mA
(VOHC)(VOUT = VOH) Output Drive = Med Full V 14 mA
Output Drive = Low Full V 7 mA
DATACK Low Drive Output Drive = High Full V –15 mA
(VOLC)(VOUT = VOL) Output Drive = Med Full V –9 mA
Output Drive = Low Full V –7 mA
Differential Input Voltage
Single-Ended Amplitude Full IV 75 800 mV
POWER SUPPLY
VD Supply Voltage Full IV 3.15 3.3 3.45 V
VDD Supply Voltage Full IV 2.2 3.3 3.6 V
PVD Supply Voltage Full IV 3.15 3.3 3.45 V
ID Supply Current (Typical Pattern)1 25∞C V 269 mA
IDD Supply Current (Typical Pattern)1, 2 25∞C V 32 mA
IPVD Supply Current (Typical Pattern)1 25∞C V 54 mA
Total Supply Current with HDCP
(Typical Pattern)1, 2 Full IV 355 367 mA
ID Supply Current (Worst-Case Pattern)3 25∞C V 276 mA
IDD Supply Current (Worst-Case Pattern)2, 3 25∞C V 127 mA
IPVD Supply Current (Worst-Case Pattern)3 25∞C V 54 mA
Total Supply Current with HDCP
(Worst-Case Pattern)2, 3 Full IV 457 468 mA
Power-Down Supply Current (IPD) Full VI 30 35 mA

–4– REV. A
 AD9882
Test AD9882KST
Parameter Conditions Temp Level Min Typ Max Unit
AC SPECIFICATIONS
Intra-Pair (+ to –) Differential
Input Skew (TDPS) Full IV 360 ps
Channel-to-Channel Differential Full IV 1 Clock
Input Skew (TCCS) Period
Low-to-High Transition Time
for Data (DLHT) Output Drive = High,
CL = 10 pF Full IV 2.2 ns
Output Drive = Med,
CL = 7 pF Full IV 2.5 ns
Output Drive = Low,
CL = 5 pF Full IV 3.2 ns

Low-to-High Transition Time for

DATACK (DLHT) Output Drive = High,
CL = 10 pF Full IV 1.0 ns
Output Drive = Med,
CL = 7 pF Full IV 1.6 ns
Output Drive = Low,
CL = 5 pF Full IV 2.1 ns

High-to-Low Transition Time for

Data (DHLT) Output Drive = High,
CL = 10 pF Full IV 2.2 ns
Output Drive = Med,
CL = 7 pF Full IV 1.9 ns
Output Drive = Low,
CL = 5 pF Full IV 1.7 ns

High-to-Low Transition Time for

DATACK (DHLT) Output Drive = High,
CL = 10 pF Full IV 1.0 ns
Output Drive = Med,
CL = 7 pF Full IV 1.0 ns
Output Drive = Low,
CL = 5 pF Full IV 1.4 ns
Data-to-Clock Skew4 Full IV –0.5 +2.0 ns
Duty Cycle, DATACK4 Full IV 40 46 50 %
DATACK Frequency (FCIP) Full VI 25 112 MHz
NOTES
1
The typical pattern contains a grayscale area, Output Drive = High.
2
DATACK Load = 10 pF, Data Load = 10 pF.
3
The worst-case pattern contains a black and white checkerboard pattern, Output Drive = High.
4
DRIVE STRENGTH = 11
Specifications subject to change without notice.

REV. A –5–
AD9882
ABSOLUTE MAXIMUM RATINGS* EXPLANATION OF TEST LEVELS
VD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V Test Level
VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.6 V I. 100% production tested.
Analog Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V
VREF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VD to 0.0 V II. 100% production tested at 25∞C and sample tested at
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V to 0.0 V specified temperatures.
Digital Output Current . . . . . . . . . . . . . . . . . . . . . . . . 20 mA III. Sample tested only.
Operating Temperature . . . . . . . . . . . . . . . . –25∞C to +85∞C
IV. Parameter is guaranteed by design and characterization
Storage Temperature . . . . . . . . . . . . . . . . . –65∞C to +150∞C
testing.
Maximum Junction Temperature . . . . . . . . . . . . . . . . 175∞C
Maximum Case Temperature . . . . . . . . . . . . . . . . . . . 150∞C V. Parameter is a typical value only.
*Stresses above those listed under Absolute Maximum Ratings may cause perma- VI. 100% production tested at 25∞C; guaranteed by design
nent damage to the device. This is a stress rating; functional operation of the device and characterization testing.
at these or any other conditions outside of those indicated in the operation sections
of this specification is not implied. Exposure to absolute maximum ratings for
extended periods may affect device reliability.

ORDERING GUIDE

Temperature Package
Model Range Option
AD9882KST-100 0∞C to 70∞C ST-100
AD9882KST-140 0∞C to 70∞C ST-100
AD9882/PCB 25∞C Evaluation Board

CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD9882 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.

–6– REV. A
 AD9882
PIN CONFIGURATION

89 SOGOUT

85 DATACK
99 RED<0>
98 RED<1>
97 RED<2>
96 RED<3>
95 RED<4>
94 RED<5>
93 RED<6>
92 RED<7>

88 HSOUT

79 HSYNC
87 VSOUT

80 VSYNC
91 GND

84 GND

82 MDA
81 MCL

78 SDA
77 SCL
VDD

83 VDD
100 VDD

86 DE

76 A0
90
GND 1 75 GND
GREEN<7> 2 74 MIDBYPASS
GREEN<6> 3 73 REFBYPASS
GREEN<5> 4 72 VD
GREEN<4> 5 71 GND
GREEN<3> 6 70 RAIN
GREEN<2> 7 69 VD
GREEN<1> 8 68 GND
GREEN<0> 9 67 VD
VDD 10 66 GND
GND 11 65 GAIN
BLUE<7> 12 AD9882 64 SOGIN
BLUE<6> 13 TOP VIEW 63 VD
(Not to Scale)
BLUE<5> 14 62 GND
BLUE<4> 15 61 VD
BLUE<3> 16 60 GND
BLUE<2> 17 59 BAIN
BLUE<1> 18 58 VD
BLUE<0> 19 57 GND
VDD 20 56 VD
GND 21 55 GND
CTL 0 22 54 DDCSDA
CTL 1 23 53 DDCSCL
CTL 2 24 52 PVD
CTL 3 25 51 GND
GND 26
VD 27
RTERM 28
VD 29
VD 30
GND 31
RX0– 32
RX0+ 33
GND 34
RX1– 35
RX1+ 36
GND 37
RX2– 38
RX2+ 39
GND 40
RXC+ 41
RXC– 42
VD 43
PVD 44
GND 45
PVD 46
GND 47
FILT 48
PVD 49
GND 50

REV. A –7–
AD9882
Table I. Complete Pinout List

Pin Pin
Type Mnemonic Function Value Number Interface
Analog RAIN Analog Input for Converter R 0.0 V to 1.0 V 70 Analog
Video Inputs GAIN Analog Input for Converter G 0.0 V to 1.0 V 65 Analog
BAIN Analog Input for Converter B 0.0 V to 1.0 V 59 Analog
External HSYNC Horizontal Sync Input 3.3 V CMOS 79 Analog
Sync/Clock VSYNC Vertical Sync Input 3.3 V CMOS 80 Analog
SOGIN Input for Sync-on-Green 0.0 V to 1.0 V 64 Analog
Sync HSOUT HSYNC Output Clock (Phase-Aligned with DATACK) 3.3 V CMOS 88 Both
Outputs VSOUT VSYNC Output Clock 3.3 V CMOS 87 Both
SOGOUT Sync-on-Green Slicer Output 3.3 V CMOS 89 Analog
References REFBYPASS Internal Reference Bypass 1.25 V 73 Analog
MIDBYPASS Internal Midscale Voltage Bypass 74 Analog
PLL Filter FILT Connection for External Filter Components for 48 Analog
Internal PLL
Power VD Analog Power Supply 3.15 V to 3.45 V Both
Supply VDD Output Power Supply 2.2 V to 3.6 V Both
PVD PLL Power Supply 3.15 V to 3.45 V Both
GND Ground 0V Both
Serial Port SDA Serial Port Data I/O 3.3 V CMOS 78 Both
Control SCL Serial Port Data Clock (100 kHz Max) 3.3 V CMOS 77 Both
A0 Serial Port Address Input 3.3 V CMOS 76 Both
Data Red [7:0] Outputs of Converter “Red”, Bit 7 is the MSB 3.3 V CMOS 92–99 Both
Outputs Green [7:0] Outputs of Converter “Green”, Bit 7 is the MSB 3.3 V CMOS 2–9 Both
Blue [7:0] Outputs of Converter “Blue”, Bit 7 is the MSB 3.3 V CMOS 12–19 Both
Data Clock
Output DATACK Data Output Clock for the Analog and Digital Interface 3.3 V CMOS 85 Both
Digital Video RX0+ Digital Input Channel 0 True 33 Digital
Data Inputs RX0– Digital Input Channel 0 Complement 32 Digital
RX1+ Digital Input Channel 1 True 36 Digital
RX1– Digital Input Channel 1 Complement 35 Digital
RX2+ Digital Input Channel 2 True 39 Digital
RX2– Digital Input Channel 2 Complement 38 Digital
Digital Video RXC+ Digital Data Clock True 41 Digital
Clock Inputs RXC– Digital Data Clock Complement 42 Digital
Data Enable DE Data Enable 3.3 V CMOS 86 Digital
Control Bits CTL [0:3] Decoded Control Bits 3.3 V CMOS 22–25 Digital
RTERM RTERM Sets Internal Termination Resistance 28 Digital
HDCP DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 53 Digital
DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 54 Digital
MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 81 Digital
MDA HDCP Master Serial Port Data I/O 3.3 V CMOS 82 Digital

–8– REV. A
 AD9882
PIN DESCRIPTIONS OF SHARED PINS BETWEEN DATA OUTPUTS
ANALOG AND DIGITAL INTERFACES RED Data Output, RED Channel
HSOUT Horizontal Sync Output GREEN Data Output, GREEN Channel
A reconstructed and phase-aligned version of the BLUE Data Output, BLUE Channel
video Hsync. The polarity of this output can be The main data outputs. Bit 7 is the MSB. These
controlled via a serial bus bit. In analog interface outputs are shared between the two interfaces
mode, the placement and duration are variable. and behave according to which interface is active.
In digital interface mode, the placement and Refer to the sections on the two interfaces for
duration are set by the graphics transmitter. more information on how these outputs behave.
VSOUT Vertical Sync Output DATACK Data Output Clock
The separated Vsync from a composite signal or Just like the data outputs, the data clock output
a direct pass-through of the Vsync input. The is shared between the two interfaces. It behaves
polarity of this output can be controlled via a differently depending on which interface is active.
serial bus bit. The placement and duration in all Refer to the sections on the two interfaces to
modes is set by the graphics transmitter. determine how this pin behaves.

SERIAL PORT (2-WIRE)

SDA Serial Port Data I/O
SCL Serial Port Data Clock
A0 Serial Port Address Input
For a full description of the 2-wire serial register,
refer to the Control Port section on 2-Wire
Serial Control.

Table II. Analog Interface Pin List

Pin
Pin Type Mnemonic Function Value Number
Analog Video RAIN Analog Input for Converter R 0.0 V to 1.0 V 70
Inputs GAIN Analog Input for Converter G 0.0 V to 1.0 V 65
BAIN Analog Input for Converter B 0.0 V to 1.0 V 59
External HSYNC Horizontal SYNC Input 3.3 V CMOS 79
Sync/Clock VSYNC Vertical SYNC Input 3.3 V CMOS 80
SOGIN Sync-on-Green Input 0.0 V to 1.0 V 64
Sync Outputs HSOUT Hsync Output (Phase-Aligned with DATACK) 3.3 V CMOS 88
VSOUT Vsync Output 3.3 V CMOS 87
SOGOUT Composite SYNC 3.3 V CMOS 89
Voltage REFBYPASS Internal Reference Bypass 1.25 V 73
Reference MIDBYPASS Internal Midscale Voltage Bypass 74
Clamp Voltages
PLL Filter FILT Connection for External Filter Components for Internal PLL 48
Power Supply VD Main Power Supply 3.15 V to 3.45 V
PVD PLL Power Supply (Nominally 3.3 V) 3.15 V to 3.45 V
VDD Output Power Supply 2.2 V to 3.6 V
GND Ground 0V

REV. A –9–
AD9882
PIN FUNCTION DETAIL (ANALOG INTERFACE) SOGOUT Sync-on-Green Slicer Output
INPUTS This pin can be programmed to produce either
RAIN Analog Input for RED Channel the output from the Sync-on-Green slicer com-
GAIN Analog Input for GREEN Channel parator or an unprocessed but delayed version of
BAIN Analog Input for BLUE Channel the Hsync input. See the Sync Processing Block
High impedance inputs that accept the RED, Diagram, Figure 18, to view how this pin is
GREEN, and BLUE channel graphics signals, connected.
respectively. For RGB, the three channels are Note: The output from this pin is the composite
identical and can be used for any colors, but SYNC without additional processing from the
colors are assigned for convenient reference. AD9882.
For proper 4:2:2 formatting in a YPbPr application, FILT External Filter Connection
the Y must be connected to the GAIN input, the For proper operation, the pixel clock generator
Pb must be connected to the BAIN input, and the PLL requires an external filter. Connect the
Pr must be connected to the RAIN input. filter shown in Figure 6 to this pin. For optimal
They accommodate input signals ranging from performance, minimize noise and parasitics on
0.5 V to 1.0 V full scale. Signals should be this node.
ac-coupled to these pins to support clamp REFBYPASS Internal Reference BYPASS
operation. Bypass for the internal 1.25 V band gap refer-
HSYNC Horizontal Sync Input ence. It should be connected to ground through
This input receives a logic signal that establishes a 0.1 mF capacitor.
the horizontal timing reference and provides the The absolute accuracy of this reference is ± 4%,
frequency reference for pixel clock generation. and the temperature coefficient is ± 50 ppm,
The logic sense of this pin is controlled by Serial which is adequate for most AD9882 applica-
Register Bit 10H, Bit 6 (Hsync Polarity). Only tions. If higher accuracy is required, an external
the leading edge of Hsync is active; the trailing reference may be employed instead.
edge is ignored. When Hsync Polarity = 0, the MIDBYPASS Midscale Voltage Reference BYPASS
falling edge of Hsync is used. When Hsync Bypass for the internal midscale voltage refer-
Polarity = 1, the rising edge is active. ence. It should be connected to ground through
The input includes a Schmitt trigger for noise a 0.1 mF capacitor. The exact voltage varies with
immunity, with a nominal input threshold of the gain setting of the RED channel.
1.5 V. HSOUT Horizontal Sync Output
Electrostatic Discharge (ESD) protection diodes A reconstructed and phase-aligned version of
will conduct heavily if this pin is driven more the Hsync input. The duration of Hsync can
than 0.5 V above the maximum tolerance voltage only be programmed on the analog interface,
(3.3 V), or more than 0.5 V below ground. not the digital.
VSYNC Vertical Sync Input DATACK Data Output Clock
This is the input for vertical sync. The data clock output signal is used to clock the
SOGIN Sync-on-Green Input output data and HSOUT into external logic.
This input is provided to assist with processing It is produced by the internal clock generator
signals with embedded sync, typically on the and is synchronous with the internal pixel
GREEN channel. The pin is connected to a sampling clock.
high speed comparator with an internally gener- When the sampling time is changed by adjusting
ated threshold, which is set by the value of the PHASE register, the output timing is shifted
register 0FH, Bits 7–3. as well. The Data, DATACK, and HSOUT
When connected to an ac-coupled graphics outputs are all moved so the timing relationship
signal with embedded sync, it will produce a among the signals is maintained.
noninverting digital output on SOGOUT. VSOUT Vertical Sync Output
When not used, this input should be left uncon- The separated Vsync from a composite signal or
nected. For more details on this function and a direct pass-through of the Vsync input. The
how it should be configured, refer to the Sync- polarity of this output can be controlled via
on-Green section. Register 10H, Bit 2. The placement and duration
in all modes is set by the graphics transmitter.

–10– REV. A
 AD9882
RED Data Output, RED Channel VDD Digital Output Power Supply
GREEN Data Output, GREEN Channel A large number of output pins (up to 25) switch-
BLUE Data Output, BLUE Channel ing at high speed (up to 140 MHz) generates a
These are the main data outputs. Bit 7 is the MSB. lot of power supply transients. These supply
The delay from pixel sampling time to output is pins are identified separately from the VD pins
fixed. When the sampling time is changed by so special care can be taken to minimize out-
adjusting the PHASE register, the output timing put noise transferred into the sensitive analog
is shifted as well. The DATACK and HSOUT circuitry.
outputs are also moved, so the timing relation- If the AD9882 is interfacing with lower voltage
ship among the signals is maintained. logic, VDD may be connected to a lower supply
Please refer to the timing diagrams for more voltage (as low as 2.2 V) for compatibility.
information. PVD Clock Generator Power Supply
The most sensitive portion of the AD9882 is the
POWER SUPPLY clock generation circuitry. These pins provide
VD Main Power Supply power to the clock PLL and help the user design
These pins supply power to the main elements of for optimal performance. The designer should
the circuit. They should be as quiet as possible. provide noise-free power to these pins.
GND Ground
The ground return for all circuitry on chip. It is
recommended that the AD9882 be assembled on
a single solid ground plane, with careful attention
to ground current paths.

Table III. Interface Selection Controls

Analog Digital
AIO Interface Interface AIS Active
(0FH Bit 2) Detect Detect (0FH Bit 1) Interface Description
1 X X 0 Analog Force the analog interface active.
1 Digital Force the digital interface active.
0 0 X None Neither interface was detected. Both interfaces are
0 powered down.
0 1 X Digital The digital interface was detected. Power down the
analog interface.
1 0 X Analog The analog interface was detected. Power down the
digital interface.
1 1 0 Analog Both interfaces were detected. The analog interface
gets priority.
1 Digital Both interfaces were detected. The digital interface
gets priority.

REV. A –11–
AD9882
Table IV. Power-Down Modes, 4:2:2 and 4:4:4 Format Descriptions

Analog Digital Active Active

Power- Interface Interface Interface Interface 4:2:2
Mode Down1 Detect2 Detect3 Override Select Formatting Data Sheet Signals Powered On
Soft Power- 1 0 0 0 X X Serial bus, digital interface clock detect,
Down (Seek analog interface clock detect, SOG
Mode)
Digital 1 0 1 0 X X Serial bus; digital interface and analog
Interface On interface activity detect; SOG, band gap
reference; red, green, and blue outputs
Analog 1 1 0 0 X 0 Serial bus; analog interface and digital
Interface On interface clock detect; SOG, band gap
4:4:4 Format reference; red, green, and blue outputs
Analog 1 1 0 0 X 1 Serial bus; analog interface and digital
Interface On interface clock detect; SOG, band gap
4:2:2 Format reference; red and green outputs only
Serial Bus 1 1 1 1 0 0 Same as Analog Interface
Arbitrated on 4:4:4 Mode
Interface
Serial Bus 1 1 1 1 0 1 Same as Analog Interface
Arbitrated on 4:2:2 Mode
Interface
Serial Bus 1 1 1 1 1 X Same as Digital Interface Mode
Arbitrated
Interface
Override to 1 1 X 1 0 0 Same as Analog Interface
Analog 4:4:4 Mode
Interface
Override to 1 1 X 1 0 1 Same as Analog Interface
Analog 4:2:2 Mode
Interface
Override to 1 X 1 1 1 X Same as Digital Interface Mode
Digital
Interface
Absolute 0 X X X X X Serial Bus
Power-
Down
NOTES
1
Power-down is controlled via Bit 1 in Serial Bus Register 14H.
2
Analog Interface Detect is determined by OR-ing Bits 7, 6, and 5 in Serial Bus Register 15H.
3
Digital Interface Detect is determined by Bit 4 in Serial Bus Register 15H.

–12– REV. A
 AD9882
THEORY OF OPERATION (INTERFACE DETECTION) THEORY OF OPERATION AND DESIGN GUIDE
Active Interface Detection and Selection (ANALOG INTERFACE)
The AD9882 includes circuitry to detect whether an interface is General Description
active or not. See Table III. The AD9882 is a fully integrated solution for capturing analog
For detecting the analog interface, the circuitry monitors the RGB signals and digitizing them for display on flat panel
presence of Hsync, Vsync, and Sync-on-Green. The result of monitors or projectors. The device is ideal for implementing a
the detection circuitry can be read from the 2-wire serial inter- computer interface for HDTV monitors or as the front end to
face bus at Address 15H, Bits 7, 5, and 6, respectively. If one of high performance video scan converters.
these sync signals disappears, the maximum time it takes for the Implemented in a high performance CMOS process, the inter-
circuitry to detect it is 100 ms. face can capture signals with pixel rates of up to 140 MHz.
For detecting the digital interface, there are two stages of detection. The AD9882 includes all necessary input buffering, signal dc
The first stage searches for the presence of the digital interface restoration (clamping), offset and gain (brightness and contrast)
clock. The circuitry for detecting the digital interface clock is adjustment, pixel clock generation, sampling phase control, and
active even when the digital interface is powered down. The output data formatting. All controls are programmable via a
result of this detection stage can be read from the 2-wire serial 2-wire serial interface. Full integration of these sensitive analog
interface bus at Address 15H, Bit 4. If the clock disappears, the functions makes the system design straightforward and less
maximum time it takes for the circuitry to detect it is 100 ms. sensitive to the physical and electrical environment.
Once a digital interface clock is detected, the digital interface is With a typical power dissipation of only 875 mW and an operat-
powered up and the second stage of detection begins. During ing temperature range of 0∞C to 70∞C, the device requires no
the second stage, the circuitry searches for 32 consecutive DEs. special environmental considerations.
Once 32 DEs are found, the detection process is complete.
Input Signal Handling
There is an override for the automatic interface selection. It is The AD9882 has three high impedance analog input pins for
the AIO (Active Interface Override) bit, Register 0FH, Bit 2. the RED, GREEN, and BLUE channels. They will accommodate
When the AIO bit is set to logic “0,” the automatic circuitry will signals ranging from 0.5 V to 1.0 V p-p.
be used. When the AIO bit is set to logic “1,” the AIS (Active
Interface Select) bit (Register 0FH, Bit 1) will be used to Signals are typically brought onto the interface board via a
determine the active interface rather than the automatic circuitry. DVI-I connector, a 15-pin D connector, or BNC connectors.
The AD9882 should be located as close as practical to the input
Power Management connector. Signals should be routed via matched-impedance
The AD9882 is a dual interface device with shared outputs. Only traces (normally 75 W) to the IC input pins.
one interface can be used at a time. For this reason, the chip auto-
matically powers down the unused interface. When the analog At that point, the signal should be resistively terminated (75 W
interface is being used, most of the digital interface circuitry is to the signal ground return) and capacitively coupled to the
powered down, and vice versa. This helps to minimize the AD9882 AD9882 inputs through 47 nF capacitors. These capacitors
total power dissipation. In addition, if neither interface has activity form part of the dc restoration circuit. See Figure 1.
on it, then the chip powers down both interfaces. The AD9882 In an ideal world of perfectly matched impedances, the best
uses the activity detect circuits, the active interface bits in Serial performance can be obtained with the widest possible signal band-
Register 15H, the active interface override bits in Register 0FH, width. The wide bandwidth inputs of the AD9882 (300 MHz) can
Bits 2 and 1, and the power-down bit in Register 14H, Bit 1, to track the input signal continuously as it moves from one pixel
determine the correct power state. In a given power mode, not all level to the next and digitize the pixel during a long, flat pixel
circuitry in the inactive interface is powered down completely. time. In many systems, however, there are mismatches, reflections,
When the digital interface is active, the band gap reference and noise, which can result in excessive ringing and distortion of
Hsync, Vsync, and SOG detect circuitry remain powered up. the input waveform. This makes it more difficult to establish a
When the analog interface is active, the digital interface clock sampling phase that provides good image quality. It has been
detect circuit is not powered down. Table IV summarizes how shown that a small inductor in series with the input is effective
the AD9882 determines what power mode to be in and what in rolling off the input bandwidth slightly and providing a high
circuitry is powered on/off in each of these modes. The power- quality signal over a wider range of conditions. Using a Fair-Rite
down command has priority, then the active interface override, #2508051217Z0 High Speed Signal Chip Bead inductor in the
and then the automatic circuitry. circuit of Figure 1 gives good results in most applications.
47nF RAIN
RGB
INPUT GAIN
BAIN
75⍀

Figure 1. Analog Input Interface Circuit

REV. A –13–
AD9882
Hsync, Vsync Inputs These are both 8-bit values, providing considerable flexibility in
The AD9882 receives a horizontal sync signal and uses it to clamp generation. The clamp timing is referenced to the trailing
generate the pixel clock and clamp timing. This can be either a edge of Hsync since the back porch (black reference) always
sync signal directly from the graphics source or a preprocessed follows Hsync. A good starting point for establishing clamping is
TTL or CMOS level signal. to set the clamp placement to 08H (providing eight pixel periods
The Hsync input includes a Schmitt trigger buffer and is capable for the graphics signal to stabilize after sync) and set the clamp
of handling signals with long rise times, with superior noise duration to 14H (giving the clamp 20 pixel periods to re-establish
immunity. In typical PC based graphic systems, the sync signals the black reference).
are simply TTL level drivers feeding unshielded wires in the The value of the external input coupling capacitor affects the
monitor cable. As such, no termination is required. performance of the clamp. If the value is too small, there can be
Serial Control Port an amplitude change during a horizontal line time (between
The serial control port is designed for 3.3 V logic. If there are clamping intervals). If the capacitor is too large, then it will take
5 V drivers on the bus, these pins should be protected with excessively long for the clamp to recover from a large change in
150 W series resistors placed between the pull-up resistors and incoming signal offset. The recommended value (47 nF) results
the input pins. in recovery from a step error of 100 mV to within one-half LSB
in 10 lines using a clamp duration of 20 pixel periods on a 75 Hz
Output Signal Handling SXGA signal.
The digital outputs are designed and specified to operate from
a 3.3 V power supply (VDD). They can also work with a VDD as YUV Clamping
low as 2.5 V for compatibility with other 2.5 V logic. YUV signals are slightly different from RGB signals in that the
dc reference level (black level in RGB signals) will be at the
Clamping midpoint of the U and V video. For these signals, it can be
RGB Clamping necessary to clamp to the midscale range of the A/D converter
To properly digitize the incoming signal, the dc offset of the range (80H) rather than the bottom of the A/D converter range (00H).
input must be adjusted to fit the range of the on-board A/D
converters. Clamping to midscale rather than ground can be accomplished
by setting the clamp select bits in the serial bus register. Each of
Most graphics systems produce RGB signals with black at ground the three converters has its own selection bit so that they can be
and white at approximately 0.75 V. However, if sync signals are clamped to either midscale or ground independently. These bits
embedded in the graphics, the sync tip is often at ground and are located in Register 11H and are Bits 4–6. The midscale
black is at 300 mV; white will be approximately 1.0 V. Some reference voltage that each A/D converter clamps to is provided
common RGB line amplifier boxes use emitter-follower buffers on the MIDBYPASS pin (Pin 74). This pin should be bypassed
to split signals and increase drive capability. This introduces a to ground with a 0.1 mF capacitor (even if midscale clamping is
700 mV dc offset to the signal, which is removed by clamping not required).
for proper capture by the AD9882.
Gain and Offset Control
The key to clamping is to identify a portion (time) of the signal The AD9882 can accommodate input signals with inputs ranging
when the graphic system is known to be producing black. Origi- from 0.5 V to 1.0 V full scale. The full-scale range is set in three
nating from CRT displays, the electron beam is “blanked” by 8-bit registers (RED Gain, GREEN Gain, and BLUE Gain).
sending a black level during horizontal retrace to prevent
disturbing the image. Most graphics systems maintain this A code of 0 establishes a minimum input range of 0.5 V;
format of sending a black level between active video lines. 255 corresponds with the maximum range of 1.0 V. Note
that INCREASING the gain setting results in an image with
An offset is then introduced, which results in the A/D converters LESS contrast.
producing a black output (code 00H) when the known black
input is present. The offset then remains in place when other The offset control shifts the entire input range, resulting in a
signal levels are processed, and the entire signal is shifted to change in image brightness. Three 7-bit registers (RED Offset,
eliminate offset errors. GREEN Offset, BLUE Offset) provide independent settings
for each channel.
In systems with embedded sync, a blacker-than-black signal
(Hsync) is produced briefly to signal the CRT that it is time to The offset controls provide a ± 63 LSB adjustment range. This
begin a retrace. For obvious reasons, it is important to avoid range is connected with the full-scale range, so if the input range
clamping on the tip of Hsync. Fortunately, there is virtually always is doubled (from 0.5 V to 1.0 V), the offset step size is also
a period following Hsync called the back porch, in which a good doubled (from 2 mV per step to 4 mV per step).
black reference is provided. This is the time when clamping should Figure 2 illustrates the interaction of gain and offset controls.
be done. The magnitude of an LSB in offset adjustment is proportional to
The clamp timing is established by the AD9882 internal clamp the full-scale range, so changing the full-scale range also changes
timing generator. The Clamp Placement Register (05H) is the offset. The change is minimal if the offset setting is near
programmed with the number of pixel times that should pass midscale. When changing the offset, the full-scale range is not
after the trailing edge of Hsync before clamping starts. A second affected, but the full-scale level is shifted by the same amount as
register (Clamp Duration, 06H) sets the duration of the clamp. the zero-scale level.

–14– REV. A
 AD9882
The stability of this clock is a very important element in provid-
ing the clearest and most stable image. During each pixel time,

H
7F
=
there is a period during which the signal is slewing from the old

T
SE
FF
pixel amplitude and settling at its new value. Then there is a

O
1.0 V
H time when the input voltage is stable, before the signal must
3F
T
= slew to a new value (Figure 4). The ratio of the slewing time to
SE
O
FF the stable time is a function of the bandwidth of the graphics
INPUT RANGE

DAC and the bandwidth of the transmission system (cable and

00
H termination). It is also a function of the overall pixel rate. Clearly,
=
ET if the dynamic characteristics of the system remain fixed, then
FS
OF
0.5 V the slewing and settling time is likewise fixed. This time must be
subtracted from the total pixel period, leaving the stable period.
At higher pixel frequencies, the total cycle time is shorter, and
H
T = 7F the stable pixel time becomes shorter as well.
OFFSE

PIXEL CLOCK INVALID SAMPLE TIMES

0.0 V OFFSET = 3FH

00H FFH
OFFS
ET =
00H

GAIN

Figure 2. Gain and Offset Control

Sync-on-Green (SOG)
The Sync-on-Green input operates in two steps. First, it sets
a baseline clamp level off of the incoming video signal with a
negative peak detector. Second, it sets the Sync trigger level
Figure 4. Pixel Sampling Times
(nominally 150 mV above the negative peak). The exact trigger
level is variable and can be programmed via Register 0FH, Any jitter in the clock reduces the precision with which the
Bits 7–3. The Sync-on-Green input must be ac-coupled to the sampling time can be determined and must also be subtracted
green analog input through its own capacitor as shown in Figure 3. from the stable pixel time.
The value of the capacitor must be 1 nF ± 20%. If Sync-on-Green
Considerable care has been taken in the design of the AD9882’s
is not used, this connection is not required and SOGIN should
clock generation circuit to minimize jitter. As indicated in Fig-
be left unconnected. (Note: The Sync-on-Green signal is always
ure 5, the clock jitter of the AD9882 is less than 6% of the total
negative polarity.) Please refer to the Sync Processing section
pixel time in all operating modes, making the reduction in the
for further information.
valid sampling time due to jitter negligible.

RAIN 10
47nF
BAIN
47nF 8
PIXEL CLOCK JITTER (p-p) – %

GAIN
47nF
SOGIN 6
1nF

Figure 3. Typical Clamp Configuration

4
Clock Generation
A Phase Locked Loop (PLL) is employed to generate the pixel
2
clock. The Hsync input provides a reference frequency for the
PLL. A Voltage Controlled Oscillator (VCO) generates a much
higher pixel clock frequency. This pixel clock is divided by the 0
PLL divide value (Registers 01H and 02H) and phase compared 25.1 31.5 36.0 40.0 50.0 56.2 65.0 75.0 78.7 85.5 94.5 108.0 135.0
with the Hsync input. Any error is used to shift the VCO frequency PIXEL CLOCK FREQUENCY – MHz

and maintain lock between the two signals.

Figure 5. Pixel Clock Jitter vs. Frequency

REV. A –15–
AD9882
The PLL characteristics are determined by the loop filter design, Table V. VCO Frequency Ranges
the PLL charge pump current, and the VCO range setting.
The loop filter design is illustrated in Figure 6. Recommended PV1 PV0 Pixel Clock Range (MHz)
settings of VCO range and charge pump current for VESA 0 0 12–41
standard display modes are listed in Table VII. 0 1 41–82
1 0 82–140
PVD
CP CZ
0.0082␮F 0.082␮F 3. The 3-bit Charge Pump Current Register (Register 03H,
RZ Bits 3–5). This register allows the current that drives the
2.74k⍀
low-pass loop filter to be varied. The possible current values
FILT are listed in Table VI.

Figure 6. PLL Loop Filter Detail Table VI. Charge Pump Current/Control Bits

Four programmable registers are provided to optimize the Ip2 Ip1 Ip0 Current (mA)
performance of the PLL. These registers are:
0 0 0 50
1. The 12-bit Divisor Register (Registers 01H and 02H). The 0 0 1 100
input Hsync frequencies range from 15 kHz to 110 kHz. The 0 1 0 150
PLL multiplies the frequency of the Hsync signal, producing 0 1 1 250
pixel clock frequencies in the range of 12 MHz to 140 MHz. 1 0 0 350
The Divisor Register controls the exact multiplication factor. 1 0 1 500
This register may be set to any value between 221 and 4095. 1 1 0 750
(The divide ratio that is actually used is the programmed 1 1 1 1500
divide ratio plus one.)
2. The 2-bit VCO Range Register (Register 03H, Bits 6 and 7). 4. The 5-bit Phase Adjust Register (Register 04H, Bits 3–7).
To improve the noise performance of the AD9882, the VCO The phase of the generated sampling clock may be shifted to
operating frequency range is divided into three overlapping locate an optimum sampling point within a clock cycle. The
regions. The VCO Range register sets this operating range. Phase Adjust Register provides 32 phase-shift steps of 11.25∞
The frequency ranges for the lowest and highest regions are each. The Hsync signal with an identical phase shift is available
shown in Table V. through the HSOUT pin.

Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats

Refresh Horizontal
Standard Resolution Rate (Hz) Frequency (kHz) Pixel Rate (MHz) VCORNGE CURRENT
VGA 640 ¥ 480 60 31.5 25.175 00 101
72 37.7 31.500 00 101
75 37.5 31.500 00 101
85 43.3 36.000 00 110
SVGA 800 ¥ 600 56 35.1 36.000 00 101
60 37.9 40.000 00 110
72 48.1 50.000 01 101
75 46.9 49.500 01 101
85 53.7 56.250 01 101
XGA 1024 ¥ 768 60 48.4 65.000 01 101
70 56.5 75.000 01 110
75 60.0 78.750 01 110
80 64.0 85.500 10 101
85 68.3 94.500 10 101
SXGA 1280 ¥ 1024 60 64.0 108.000 10 101
75 80.0 135.000 11 110

–16– REV. A
 AD9882
The COAST function allows the PLL to continue to run at the Register (Register 04H) to optimize the pixel sampling time.
same frequency, in the absence of the incoming Hsync signal or Display systems use Hsync to align memory and display write
during disturbances in Hsync (such as equalization pulses). This cycles, so it is important to have a stable timing relationship
may be used during the vertical sync period, or any other time between Hsync output (HSOUT) and data clock (DATACK).
that the Hsync signal is unavailable. Also, the polarity of the Three things happen to Horizontal Sync in the AD9882. First,
Hsync signal may be set through the Hsync Polarity Bit (Register the polarity of Hsync input is determined and will thus have a
10H, Bit 6). If not using automatic polarity detection, the Hsync known output polarity. The known output polarity can be pro-
polarity bit should be set to match the polarity of the Hsync grammed either active high or active low (Register 10H, Bit 5).
input signal. Second, HSOUT is aligned with DATACK and data outputs.
Third, the duration of HSOUT (in pixel clocks) is set via
TIMING (ANALOG INTERFACE) Register 07H. HSOUT is the sync signal that should be used to
The following timing diagrams show the operation of the AD9882. drive the rest of the display system.
The Output Data Clock signal is created so that its rising edge Coast Timing
always occurs between data transitions and can be used to latch In most computer systems, the Hsync signal is provided continu-
the output data externally. ously on a dedicated wire. In these systems, the COAST function
tPER
is unnecessary and should be disabled using Register 11H, Bits 1–3.
In some systems, however, Hsync is disturbed during the Vertical
tDCYCLE
Sync period (Vsync). In other cases, Hsync pulses disappear.
DATACK In other systems, such as those that employ Composite Sync
(Csync) signals or embedded Sync-on-Green (SOG), Hsync
tSKEW includes equalization pulses or other distortions during Vsync. To
avoid upsetting the clock generator during Vsync, it is important
DATA
HSOUT
to ignore these distortions. If the pixel clock PLL sees extraneous
pulses, it will attempt to lock to this new frequency and will
have changed frequency by the end of the Vsync period. It will
Figure 7. Output Timing then take a few lines of correct Hsync timing to recover at the
beginning of a new frame, resulting in a “tearing” of the image
Hsync Timing at the top of the display.
Horizontal Sync (Hsync) is processed in the AD9882 to elimi-
nate ambiguity in the timing of the leading edge with respect to The COAST function is provided to eliminate this problem. It
the phase-delayed pixel clock and data. is an internally generated signal, created by the sync processing
engine that disables the PLL input and allows the clock to free-run
The Hsync input is used as a reference to generate the pixel at its then-current frequency. The PLL can free-run for several
sampling clock. The sampling phase can be adjusted, with respect lines without significant frequency drift.
to Hsync, through a full 360∞ in 32 steps via the Phase Adjust

REV. A –17–
AD9882
TIMING DIAGRAMS

RGBIN P0 P1 P2 P3 P4 P5 P6 P7

HSYNC

PXCK

HS

5 PIPE DELAY

ADCCK

DATACK

DATAOUT D0 D1 D2 D3 D4 D5 D6 D7

HSOUT VARIABLE DURATION

Figure 8. 4:4:4 Mode (for RGB and YPbPr)

RGBIN P0 P1 P2 P3 P4 P5 P6 P7

HSYNC

PXCK

HS
5 PIPE DELAY

ADCCK

DATACK

GOUTA Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7

ROUTA Pb0 Pr0 Pb2 Pr2 Pb4 Pr4 Pb6 Pr6

HSOUT VARIABLE DURATION

Figure 9. 4:2:2 Mode (for YPbPr Only)

–18– REV. A
 AD9882
Table VIII. Digital Interface Pin List

Pin Type Mnemonic Function Value Pin Number

Digital Video RX0+ Digital Input Channel 0 True 33
Data Inputs RX0– Digital Input Channel 0 Complement 32
RX1+ Digital Input Channel 1 True 36
RX1– Digital Input Channel 1 Complement 35
RX2+ Digital Input Channel 2 True 39
RX2– Digital Input Channel 2 Complement 38
Digital Video RXC+ Digital Data Clock True 41
Clock Inputs RXC– Digital Data Clock Complement 42
Termination RTERM Control Pin for Setting the Internal Termination 28
Control Resistance
Outputs DE Data Enable 3.3 V CMOS 86
HSOUT Hsync Output 3.3 V CMOS 88
VSOUT Vsync Output 3.3 V CMOS 87
CTL0, CTL1, Decoded Control Bit Outputs 3.3 V CMOS 22–25
CTL2, CTL3
HDCP DDCSCL HDCP Slave Serial Port Data Clock 3.3 V CMOS 53
DDCSDA HDCP Slave Serial Port Data I/O 3.3 V CMOS 54
MCL HDCP Master Serial Port Data Clock 3.3 V CMOS 81
MDA HDCP Master Serial Port Data I/O 3.3 V CMOS 82
Power Supply VD Main Power Supply 3.15 V to 3.45 V
PVD PLL Power Supply 3.15 V to 3.45 V
VDD Output Power Supply 2.2 V to 3.6 V
GND Ground Supply 0V

DIGITAL INTERFACE PIN DESCRIPTIONS OUTPUTS

DIGITAL DATA INPUTS DE Data Enable Output
RX0+ Positive Differential Input Data (Channel 0) This pin outputs the state of data enable (DE).
RX0– Negative Differential Input Data (Channel 0) The AD9882 decodes DE from the incoming
RX1+ Positive Differential Input Data (Channel 1) stream of data. The DE signal will be HIGH
RX1– Negative Differential Input Data (Channel 1) during active video and will be LOW while there
RX2+ Positive Differential Input Data (Channel 2) is no active video.
RX2– Negative Differential Input Data (Channel 2) DDCSCL HDCP Slave Serial Port Data Clock
These six pins receive three pairs of differential, low voltage swing input pixel
data from a DVI transmitter. For use in communicating with the HDCP
enabled DVI transmitter.
DIGITAL CLOCK INPUTS DDCSDA HDCP Slave Serial Port I/O
RXC+ Positive Differential Input Clock For use in communicating with the HDCP
RXC– Negative Differential Input Clock enabled DVI transmitter.
These two pins receive the differential, low voltage swing input pixel clock from
a DVI transmitter. MCL HDCP Master Serial Port Data Clock
Connects to the EEPROM for reading the
TERMINATION CONTROL encrypted HDCP keys.
RTERM Internal Termination Set Pin MDA HDCP Master Serial Port Data I/O
This pin is used to set the termination resistance Connects to the EEPROM for reading the
for all of the digital interface high speed inputs. encrypted HDCP keys.
To set, place a resistor of value equal to 10¥ the
CTL Digital Control Outputs
desired input termination resistance between this
These pins output the control signals for the
pin (Pin 28) and ground supply. Typically, the
Red and Green channels. CTL0 and CTL1
value of this resistor should be 500 W.
correspond to the Red channel’s input, while
CTL2 and CTL3 correspond to the Green
channel’s input.

REV. A –19–
AD9882
POWER SUPPLY Data Decoder
VD Main Power Supply The data decoder receives frames of data and sync signals from
It should be as quiet as possible. the data capture block (in 10-bit parallel words) and decodes
PVD PLL Power Supply them into groups of eight RGB bits, two control bits, and a data
It should be as quiet as possible. enable bit (DE).

VDD Outputs Power Supply HDCP

The power for the data and clock outputs. It can The AD9882 contains all the circuitry necessary for decryption
run at 3.3 V or 2.5 V. of a high bandwidth digital content protection encoded DVI
video stream. A typical HDCP implementation is shown in
GND Ground Figure 10. Several features of the AD9882 make this possible
The ground return for all circuitry on the device. and add functionality to ease the implementation of HDCP.
It is recommended that the application circuit
board have a single, solid ground plane. The basic components of HDCP are included in the AD9882.
A slave serial bus connects to the DDC clock and DDC data
pins on the DVI connector to allow the HDCP enabled DVI
THEORY OF OPERATION (DIGITAL INTERFACE) transmitter to coordinate the HDCP algorithm with the AD9882.
Capturing of the Encoded Data A second serial port (MDA/MCL) allows the AD9882 to read
The first step in recovering the encoded data is to capture the raw the HDCP keys and key selection vector (KSV) stored in an
data. To accomplish this, the AD9882 employs a high speed phase external serial EEPROM. When transmitting encrypted video,
locked loop (PLL) to generate clocks capable of oversampling the DVI transmitter enables HDCP through the DDC port.
the data at the correct frequency. The data capture circuitry The AD9882 then decodes the DVI stream using information
continuously monitors the incoming data during horizontal and provided by the transmitter, HDCP keys, and KSV.
vertical blanking times (when DE is low) and selects the best
sampling phase for each data channel independently. The phase The AD9882 allows the MDA and MCL pins to be three-stated
information is stored and used until the next blanking period using the MDA/MCL three-state bit (Register 1B, Bit 7) in the
(one video line). configuration registers. The three-state feature allows the EEPROM
to be programmed in-circuit. The MDA/MCL port must be
Data Frames three-stated before attempting to program the EEPROM using
The digital interface data is captured in groups of 10 bits each, an external master. The keys will be stored in an I2C compatible
which are called data frames. During the active data period, 3.3 V serial EEPROM of at least 512 bytes in size. The EEPROM
each frame is made up of the nine encoded video data bits and should have a device address of A0H.
one dc balancing bit. The data capture block receives this
data serially but outputs each frame in parallel 10-bit words. Proprietary software licensed from Analog Devices encrypts
the keys and creates properly formatted EEPROM images for
Special Characters use in a production environment. Encrypting the keys helps
During periods of horizontal or vertical blanking time (when DE is maintain the confidentiality of the HDCP keys as required by
low), the digital transmitter will transmit special characters. The the HDCP v1.0 specification. The AD9882 includes hard-
AD9882 will receive these characters and use them to set the video ware for decrypting the keys in the external EEPROM.
frame boundaries and the phase recovery loop for each chan-
nel. There are four special characters that can be received. ADI will provide a royalty free license for the proprietary
They are used to identify the top, bottom, left side, and right software needed by customers to encrypt the keys between
side of each video frame. The data receiver can differentiate the AD9882 and the EEPROM only after customers provide
these special characters from active data because the special evidence of a completed HDCP Adopter’s license agreement
characters have a different number of transitions per data frame. and sign ADI’s software license agreement. The Adopter’s
license agreement is maintained by Digital Content Protection,
Channel Resynchronization LLC, and can be downloaded from www.digital-cp.com.
The purpose of the channel resynchronization block is to To obtain ADI’s software license agreement, contact the Display
resynchronize the three data channels to a single internal data Electronics Product Line directly by sending an email to
clock. Coming into this block, all three data channels can be on flatpanel_apps@analog.com.
different phases of the 3¥ oversampling PLL clock (0∞, 120∞,
and 240∞). This block can resynchronize the channels from a
worst-case skew of one full input period (8.93 ns at 112 MHz).

3.3V 3.3V

DVI
5k⍀ PULL-UP 5k⍀ PULL-UP
CONNECTOR
RESISTORS RESISTORS
DDC CLOCK DDC SCL MCL SCL
AD9882 EEPROM
DDC DATA D S DDC SDA MDA SDA
150⍀ SERIES
3.3V
RESISTORS

Figure 10. HDCP Implementation Using the AD9882

–20– REV. A
 AD9882
GENERAL TIMING DIAGRAMS (DIGITAL INTERFACE)

80% 80% TCIP , R CIP

TCIH , R CIH

20% 20%

DLHT DHLT

TCIL , R CIL

Figure 11. Digital Output Rise and Fall Times

Figure 12. Clock Cycle/High/Low Times

RX0

VDIFF = 0V

RX1

TCSS
VDIFF = 0V

RX2

Figure 13. Channel-to-Channel Skew Timing

TIMING MODE DIAGRAMS (DIGITAL INTERFACE)

INTERNAL
ODCLK
TST

DATACK

DE

FIRST PIXEL SECOND PIXEL THIRD PIXEL FOURTH PIXEL

DATAOUT

Figure 14. DVI CLK Invert = 1 (Register 14, Bit 4)

INTERNAL
ODCLK
TST
DATACK

DE

FIRST PIXEL SECOND PIXEL THIRD PIXEL FOURTH PIXEL

DATAOUT

Figure 15. DVI CLK Invert = 0 (Register 14, Bit 4)

REV. A –21–
AD9882
2-WIRE SERIAL REGISTER MAP
The AD9882 is initialized and controlled by a set of registers that determines the operating modes. An external controller is employed
to write and read the Control Registers through the 2-wire serial interface port.

Table IX. Control Register Map

Hex Read and Write Default

Address or Read Only Bit Value Register Name Function
00 RO 7–0 Chip Revisions An 8-bit register that represents the silicon
level. Revision 0 = 0000 0000
01 R/W 7–0 0110 1001 PLL Div MSB This register is for Bits [11:4] of the PLL
divider. Larger values mean the PLL operates
at a faster rate. This register should be loaded
first whenever a change is needed. (This will
give the PLL more time to lock.)1
02 R/W 7–4 1101 **** PLL Div LSB Bits [3:0] LSBs of the PLL divider word. Links
to PLL MSB to make a 12-bit register.1
03 R/W 7–6 01** **** VCO Range Selects VCO frequency range.
5–3 **00 1*** Charge Pump Varies the current that drives the PLL loop filter.
04 R/W 7–3 1000 0*** Phase Adjust ADC clock phase adjustment. Larger values
mean more delay (1 LSB = T/32).
05 R/W 7–0 0000 1000 Clamp Placement Places the clamp signal an integer number of
clock periods after the trailing edge of Hsync.
06 R/W 7–0 0001 0100 Clamp Duration Number of clock periods that the clamp signal
is actively clamping.
07 R/W 7–0 0010 0000 Hsync Output Pulsewidth Sets the number of pixel clocks that HSOUT
will remain active.
08 R/W 7–0 1000 0000 Red Gain Controls the ADC input range (contrast) of the
red channel. Larger values give less contrast.
09 R/W 7–0 1000 0000 Green Gain Controls the ADC input range (contrast) of the
green channel. Larger values give less contrast.
0A R/W 7–0 1000 0000 Blue Gain Controls the ADC input range (contrast) of the
blue channel. Larger values give less contrast.
0B R/W 7–1 1000 000* Red Offset Controls the dc offset (brightness) of the red
channel. Larger values decrease brightness.
0C R/W 7–1 1000 000* Green Offset Controls the dc offset (brightness) of the green
channel. Larger values decrease brightness.
0D R/W 7–1 1000 000* Blue Offset Controls the dc offset (brightness) of the blue
channel. Larger values decrease brightness.
0E R/W 7–0 0010 0000 Sync Separator Threshold Sets how many pixel clocks to count before
toggling high or low. This should be set to
some number greater than the maximum
Hsync or equalization pulsewidth.
0F R/W 7–3 0111 1*** Sync-On-Green Threshold Sets the voltage level of the Sync-on-Green
slicer’s comparator.
2 **** *0** Active Interface Override 0 = No override
1 = User overrides, interface set by 0FH, Bit 1
1 **** **0* Active Interface Select 0 = Analog interface active
1 = Digital interface active
This interface is selected only if Register 0FH,
Bit 2 is set to 1, or if both interfaces are active.
NOTE
1
The AD9882 only updates the PLL divide ratio when the LSBs are written to Register 02H.

–22– REV. A
 AD9882
Table IX. Control Register Map (continued)

Hex Read and Write Default

Address or Read Only Bit Value Register Name Function
10 R/W 7 0*** **** Hsync Polarity Override 0 = Polarity determined by chip
1 = Polarity set by 10H, Bit 6
6 *1** **** Input Hsync Polarity 0 = Active low polarity
1 = Active high polarity
5 **0* **** Output Hsync Polarity 0 = Active high sync signal
1 = Active low sync signal
4 ***0 **** Active Hsync Override 0 = No override
1 = User overrides, analog Hsync set by 10H, Bit 3
3 **** 0*** Active Hsync Select 0 = Analog Hsync from the Hsync input pin
1 = Analog Hsync from SOG
This bit is used if Register 10H, Bit 4 is set to
1 or if both syncs are active.
2 **** *0** Output Vsync Polarity 0 = Invert
1 = Not inverted
1 **** **0* Active Vsync Override 0 = No override
1 = User overrides, analog Vsync set by 10H, Bit 0
0 **** ***0 Active Vsync Select 0 = Analog Vsync from the Vsync input pin
1 = Analog Vsync from sync separator
11 R/W 7 0*** **** Clamp Function 0 = Clamping with internal clamp
1 = Clamping disabled
6 *0** **** Red Clamp Select 0 = Clamp to ground
1 = Clamp to midscale for red channel
5 **0* **** Green Clamp Select 0 = Clamp to ground
1 = Clamp to midscale for green channel
4 ***0 **** Blue Clamp Select 0 = Clamp to ground
1 = Clamp to midscale for blue channel
3 **** 1*** Coast Select 0 = Disabled coast
1 = Coasting with internally generated coast signal
2 **** *0** Coast Polarity Override 0 = Coast polarity determined by the chip
1 = Coast polarity set by 11H, Bit 1
This bit must be set to 1 to disable coast.
1 **** **1* Input Coast Polarity 0 = Active low coast signal
1 = Active high coast signal
This bit must be set to 1 to disable coast.
12 R/W 7–0 0000 0000 Pre-Coast Number of Hsync periods that coast goes active
prior to Vsync.
13 R/W 7–0 0000 0000 Post-Coast Number of Hsync periods before coast goes inactive
following Vsync.
14 R/W 7–6 11** **** Output Drive Select Selects among high, medium, and low output
drive strength.
5 **1* **** Programmable Bandwidth 0 = Low bandwidth of 10 MHz
1 = High bandwidth of 300 MHz
4 ***0 **** DVI Clock Invert 0 = DVI data clock output not inverted
1 = DVI data clock output inverted
For digital interface only.
3 **** 0*** DVI PDO Three-State 0 = Normal outputs
1 = High impedance outputs
2 **** *0** HDCP Address Address Bit 0 = 0 for HDCP Slave Port
Address Bit 1 = 1 for HDCP Slave Port
1 **** **1* Power-Down 0 = Full chip power-down

REV. A –23–
AD9882
Table IX. Control Register Map (continued)

Hex Read and Write Default

Address or Read Only Bit Value Register Name Function
14 R/W 0 **** ***0 Enable 4:2:2 0 = 4:4:4 mode
1 = 4:2:2 mode
15 RO 7 Analog Hsync Active 0 = Hsync not detected
1 = Hsync detected
6 Analog SOG Active 0 = Sync signal not detected on green channel
1 = Sync signal detected on green channel
5 Analog Vsync Active 0 = Vsync not detected
1 = Vsync detected
4 DVI Active 0 = Digital interface clock not detected
1 = Digital interface clock detected
3 Active Interface 0 = Analog interface active
1 = DVI interface active
16 RO 7 Active Hsync 0 = Hsync from the Hsync input pin
1 = Hsync from the SOG input
6 Hsync Polarity Detected 0 = Active low polarity detected
1 = Active high polarity detected
5 Active Vsync 0 = Vsync from the Vsync input pin
1 = Vsync from SOG
4 Vsync Polarity Detected 0 = Active high polarity detected
1 = Active low polarity detected
3 Coast Polarity Detected 0 = Active low polarity detected
1 = Active high polarity detected
This function works only with internal coast.
2 HDCP Keys Detected 0 = Not detected
1 = Detected
17 R/W 7–0 0000 0000 Test Register Must be set to 1000 0000 for proper operation.
18 R/W 7–0 0000 000X Test Register Must be set to 1100 000x for proper operation.
19 R/W 7–0 0000 010X Test Register Must be set to 0111 110x for proper operation.
1A R/W 7–0 0011 1111 Test Register Must be set to default for proper operation.
1B R/W 7 1*** **** MDA and MCL 0 = MDA and MCL three-stated
1 = MDA and MCL not three-stated
6–0 *111 0000 Test Register Must be set to *110 0111 for proper operation.
1C R/W 7–0 0000 1111 Test Register Must be set to default for proper operation.
1D RO 7–0 Test Register Reserved for future use.
1E RO 7–0 Test Register Reserved for future use.

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 AD9882
2-WIRE SERIAL CONTROL REGISTER DETAIL Table X. VCO Ranges
CHIP IDENTIFICATION
00 7–0 Chip Revision VCORNGE Pixel Rate Range
An 8-bit register that represents the silicon revision. Revision 0 00 12–41
= 0000 0000. 01 41–82
10 82–140
PLL DIVIDER CONTROL
The power-up default value is VCORNGE = 01.
01 7–0 PLL Divide Ratio MSBs
The eight most significant bits of the 12-bit PLL divide ratio
03 5–3 CURRENT Charge Pump Current
PLLDIV. (The operational divide ratio is PLLDIV + 1.)
Three bits that establish the current driving the loop filter in the
The PLL derives a pixel clock from the incoming Hsync signal. clock generator.
The pixel clock frequency is then divided by an integer value,
such that the output is phase-locked to Hsync. This PLLDIV Table XI. Charge Pump Currents
value determines the number of pixel times (pixels plus horizontal
blanking overhead) per line. This is typically 20% to 30% more Charge Pump Current (mA)
than the number of active pixels in the display. 000 50
The 12-bit value of the PLL divider supports divide ratios from 001 100
221 to 4095. The higher the value loaded in this register, the 010 150
higher the resulting clock frequency with respect to a fixed Hsync 011 250
frequency. 100 350
VESA has established some standard timing specifications that will 101 500
assist in determining the value for PLLDIV as a function of the 110 750
horizontal and vertical display resolution and frame rate 111 1500
(Table VII). However, many computer systems do not conform
precisely to the recommendations, and these numbers should be CHARGE PUMP must be set to correspond with the desired
used only as a guide. The display system manufacturer should operating frequency (incoming pixel rate). See Table XI for the
provide automatic or manual means for optimizing PLLDIV. charge pump current for each register setting.
An incorrectly set PLLDIV will usually produce one or more The power-up default value is CURRENT = 001.
vertical noise bars on the display. The greater the error, the
04 7–3 Phase Adjust
greater the number of bars produced.
A 5-bit value that adjusts the sampling phase in 32 steps
The power-up default value of PLLDIV is 1693 (PLLDIVM = across one pixel time. Each step represents an 11.25∞ shift in
69H, PLLDIVL = DxH). sampling phase.
The AD9882 updates the full divide ratio only when the LSBs are The power-up default Phase adjust value is 10H.
changed. Writing to this register by itself will not trigger an update.
02 7–4 PLL Divide Ratio LSBs CLAMP TIMING
The four least significant bits of the 12-bit PLL divide ratio 05 7–0 Clamp Placement
PLLDIV. The operational divide ratio is PLLDIV + 1. An 8-bit register that sets the position of the internally gener-
ated clamp.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69H, PLLDIVL = DxH). When CLAMP FUNCTION (Register 11H, Bit 7) = 0, a clamp
signal is generated internally at a position established by the
The AD9882 updates the full divide ratio only when this register clamp placement and for a duration set by the clamp duration.
is written. Clamping is started (Clamp Placement) an integral number of
03 7–6 VCO Range Select pixel periods after the trailing edge of Hsync. The clamp place-
Two bits that establish the operating range of the clock generator. ment may be programmed to any value between 1 and 255.
VCORNGE must be set to correspond with the desired operating The clamp should be placed during a time that the input signal
frequency (incoming pixel rate). presents a stable black-level reference, usually the back porch
The PLL VCO gives the best jitter performance while operating period between Hsync and the image.
at high frequencies. For this reason, in order to output low pixel When CLAMP FUNCTION = 1, this register is ignored.
rates and still get good jitter performance, the PLL VCO actually 06 7–0 Clamp Duration
operates at a higher frequency but then divides down the clock An 8-bit register that sets the duration of the internally gener-
rate afterward. Table X shows the pixel rates for each VCO range ated clamp.
setting. The PLL output divisor is automatically selected with
the VCO range setting. For the best results, the clamp duration should be set to include
the majority of the black reference signal time that follows the
Hsync signal trailing edge. Insufficient clamping time can produce
brightness changes at the top of the screen and a slow recovery from
large changes in the Average Picture Level (APL) or brightness.
When CLAMP FUNCTION = 1, this register is ignored.

REV. A –25–
AD9882
HSYNC OUTPUT PULSEWIDTH 0F 7–3 Sync-on-Green Slicer Threshold
07 7–0 Hsync Output Pulsewidth This register allows the comparator threshold of the Sync-on-Green
An 8-bit register that sets the duration of the Hsync output pulse. slicer to be adjusted. This register adjusts it in steps of 10 mV,
The leading edge of the Hsync output is triggered by the internally with the minimum setting equaling 10 mV and the maximum
generated, phase adjusted PLL feedback clock. The AD9882 setting equaling 330 mV.
then counts a number of pixel clocks equal to the value in this The default setting is 15 decimal and corresponds to a threshold
register minus one. This triggers the trailing edge of the Hsync value of 170 mV.
output, which is also phase adjusted. 0F 2 AIO Active Interface Override
This bit is used to override the automatic interface selection
INPUT GAIN (Bit 3 in Register 15H). To override, set this bit to logic 1. When
08 7–0 REDGAIN RED Gain overriding, the active interface is set via Bit 1 in this register.
An 8-bit word that sets the gain of the RED channel. The AD9882
can accommodate input signals with a full-scale range of between Table XII. Active Interface Override Settings
0.5 V and 1.0 V p-p. Setting REDGAIN to 255 corresponds to
an input range of 1.0 V. A REDGAIN of 0 establishes an input AIO Result
range of 0.5 V. Note that INCREASING REDGAIN results in
0 Autodetermine the active interface.
the picture having LESS CONTRAST (the input signal uses
1 Override, Bit 1 determines the active interface.
fewer of the available converter codes). See Figure 2.
The default for this register is 0.
09 7–0 GREENGAIN GREEN Gain
An 8-bit word that sets the gain of the GREEN channel. See
0F 1 AIS Active Interface Select
REDGAIN (08).
This bit is used under two conditions. It is used to select the active
0A 7–0 BLUEGAIN BLUE Gain interface when the override bit is set (Register 0FH, Bit 2).
An 8-bit word that sets the gain of the BLUE channel. See Alternatively, it is used to determine the active interface when
REDGAIN (08). not overriding but both interfaces are detected.

INPUT OFFSET Table XIII. Active Interface Select Settings

0B 7–1 RED Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the RED AIS Result
channel. One LSB of offset adjustment equals approximately one 0 Analog interface
LSB change in the ADC offset. Therefore, the absolute magni- 1 Digital interface
tude of the offset adjustment scales as the gain of the channel is
changed. A nominal setting of 64 results in the channel nominally The default for this register is 0.
clamping the back porch (during the clamping interval) to code 00.
An offset setting of 127 results in the channel clamping to code 10 7 Hsync Input Polarity Override
63 of the ADC. An offset setting of 0 clamps to code –64 (off the This register is used to override the internal circuitry that determines
bottom of the range). Increasing the value of RED offset the polarity of the Hsync signal going into the PLL.
DECREASES the brightness of the channel.
Table XIV. Hsync Input Polarity Override Settings
0C 7–1 GREEN Channel Offset Adjust
A 7-bit offset binary word that sets the dc offset of the GREEN Override Bit Result
channel. See REDOFST (0B). 0 Hsync polarity determined by chip.
0D 7–1 BLUE Channel Offset Adjust 1 Hsync polarity determined by Register 10H,
A 7-bit offset binary word that sets the dc offset of the BLUE Bit 6.
channel. See REDOFST (0B). The default for Hsync polarity override is 0. (Polarity determined by chip.)
0E 7–0 Sync Separator Threshold
This register is used to set the responsiveness of the sync separator. 10 6 HSPOL Hsync Input Polarity
It sets how many internal 5 MHz clock periods the sync separa- A bit that must be set to indicate the polarity of the Hsync signal
tor must count to before toggling high or low. It works like a that is applied to the PLL Hsync input.
low-pass filter to ignore Hsync pulses in order to extract the
Vsync signal. This register should be set to some number greater Table XV. Hsync Input Polarity Settings
than the maximum Hsync pulsewidth. Note: the sync separator
threshold uses an internal dedicated clock with a frequency of HSPOL Function
approximately 5 MHz. 0 Active LOW
The default for this register is 20H. 1 Active HIGH

Active LOW means the leading edge of the Hsync pulse is negative-
going. All timing is based on the leading edge of Hsync, which
is the FALLING edge. The rising edge has no effect.

–26– REV. A
 AD9882
Active HIGH means the leading edge of the Hsync pulse is 10 1 Active Vsync Override
positive-going. This means that timing will be based on the This bit is used to override the automatic Vsync selection. To
leading edge of Hsync, which is now the RISING edge. override, set this bit to logic 1. When overriding, the active
The device will operate if this bit is set incorrectly, but the inter- interface is set via Bit 0 in this register.
nally generated clamp position, as established by Clamp Placement
(Register 05H), will not be placed as expected, which may Table XX. Active Vsync Override Settings
generate clamping errors. Override Result
The power-up default value is HSPOL = 1.
0 Autodetermine the active Vsync
10 5 Hsync Output Polarity 1 Override. Bit 0 determines the active Vsync.
One bit that determines the polarity of the Hsync output and the
The default for this register is 0.
SOG output. Table XVI shows the effect of this option. SYNC
indicates the logic state of the sync pulse. 10 0 Active Vsync Select
This bit is used to select the active Vsync when the override bit
Table XVI. Hsync Output Polarity Settings is set (Bit 1).
Setting SYNC
Table XXI. Active Vsync Select Settings
0 Logic 1 (positive polarity)
1 Logic 0 (negative polarity) Select Result
The default setting for this register is 0. 0 Vsync input
1 Sync separator output
10 4 Active Hsync Override
The default for this register is 0.
This bit is used to override the automatic Hsync selection. To
override, set this bit to logic 1. When overriding, the active 11 7 Clamp Function
Hsync is set via Bit 3 in this register. A bit that enables/disables clamping.
Table XVII. Active Hsync Override Settings Table XXII. Clamp Input Signal Source Settings
Override Result Clamp Function Function
0 Autodetermine the active Hsync. 0 Internally generated clamp enabled
1 Override. Bit 3 determines the active Hsync. 1 Clamping disabled
The default for this register is 0.
A 0 enables the clamp timing circuitry controlled by clamp
10 3 Active Hsync Select placement and clamp duration. The clamp position and duration
This bit is used under two conditions. It is used to select the active is counted from the trailing edge of Hsync.
Hsync when the override bit is set (Bit 4). Alternately, it is used A 1 disables clamping. The three channels are clamped when
to determine the active Hsync when not overriding, but both the CLAMP signal is active.
Hsyncs are detected.
Power-up default value is CLAMP FUNCTION = 0.
Table XVIII. Active Hsync Select Settings
11 6 RED Clamp Select
Select Result A bit that determines whether the RED channel is clamped to
ground or to midscale. For RGB video, all three channels are
0 Hsync input
referenced to ground. For YPbPr, the Y channel is referenced
1 Sync-on-Green input
to ground, but the PbPr channels are referenced to midscale.
The default for this register is 0. Clamping to midscale actually clamps to Pin 74.

10 2 Vsync Output Polarity Table XXIII. RED Clamp Select Settings

One bit that determines the polarity of the Vsync output.
Table XIX shows the effect of this option. SYNC indicates the Clamp Function
logic state of the sync pulse. 0 Clamp to ground
1 Clamp to midscale (Pin 74)
Table XIX. Vsync Output Polarity Settings
The default setting for this register is 0.
Setting SYNC
1 Not invert
0 Invert
The default setting for this register is 0.

REV. A –27–
AD9882
11 5 GREEN Clamp Select 12 7–0 Pre-Coast
A bit that determines whether the GREEN channel is clamped This register allows the coast signal to be applied prior to the
to ground or to midscale. Vsync signal. This is necessary in cases where pre-equalization
pulses are present. This register defines the number of edges
Table XXIV. GREEN Clamp Select Settings that will be filtered before Vsync on a composite sync.
Clamp Function The default is 0.
0 Clamp to ground 13 7–0 Post-Coast
1 Clamp to midscale (Pin 74) This register allows the coast signal to be applied following the
Vsync signal. This is necessary in cases where post-equalization
The default setting for this register is 0.
pulses are present. The step size for this control is one Hsync
11 4 BLUE Clamp Select period. This register defines the number of edges that will be
A bit that determines whether the BLUE channel is clamped to filtered after Vsync on a composite sync.
ground or to midscale. The default is 0.
Table XXV. BLUE Clamp Select Settings 14 7–6 Output Drive
The two bits select the drive strength for the high speed digital
Clamp Function outputs (all data output and clock output pins). Higher drive
0 Clamp to ground strength results in faster rise/fall times, and in general makes it
1 Clamp to midscale (Pin 74) easier to capture data. Lower drive strength results in slower
rise/fall times and helps reduce EMI and digitally generated
The default setting for this register is 0. power supply noise.
11 3 Coast Select
Table XXIX. Output Drive Strength Settings
This bit is used to enable or disable the coast signal. If coast is
enabled, the additional decision of using the Vsync input pin or Bit 7 Bit 6 Result
the output from the sync separator needs to be made (Register
10H, Bits 1, 0). To disable coast, the user must set Register 11H, 1 X High drive strength
Bit 2 to 1 and 11H, Bit 1 to 1. 0 1 Medium drive strength
0 0 Low drive strength
Table XXVI. Coast Enable Settings The default for this register is 11, high drive strength. (This option works on
both the analog and digital interfaces.)
Select Result
0 Coast disabled 14 5 Programmable Analog Bandwidth
1 Internally generated coast signal Bits that select the analog bandwidth.
The default for this register is 1.
Table XXX. Analog Bandwidth Control
11 2 Coast Input Polarity Override
Bit 5 Analog Bandwidth
This register is used to override the internal circuitry that deter-
mines the polarity of the coast signal going into the PLL. When 0 10 MHz
disabling coast, Register 11, Bit 2 must be set to 1 and Register 1 300 MHz
11H, Bit 1 must be set to 1. This register only works when Coast
is disabled. It does not work with internal Coast.
14 4 Clk Inv Data Output Clock Invert
Table XXVII. Coast Input Polarity Override Settings A control bit for the inversion of the output data clock (Pin 85).
This function works only for the digital interface. When not
Override Bit Result inverted, data is output on the falling edge of the data clock.
0 Coast polarity determined by chip See the timing diagrams, Figures 14 and 15, to see how this
1 Coast polarity determined by user affects timing.

The default for coast polarity override is 0. Table XXXI. Clock Output Invert Settings
11 1 Coast Input Polarity Clk Inv Function
A bit to indicate the polarity of the coast signal that is applied to
the PLL coast input. 0 Not inverted
1 Inverted
This register can only be used when coast is disabled and
Register 11H, Bit 2 is set to 1. The default for this register is 0 (not inverted).

Table XXVIII. Coast Input Polarity Settings

CSTPOL Function
0 Active LOW
1 Active HIGH
The power-up default value is CSTPOL = 1.
–28– REV. A
 AD9882
14 3 PDO Power-Down Outputs 15 7 Hsync Detect
A bit that can put the outputs in a high impedance mode. This This bit is used to indicate when activity is detected on the
applies to the 24 data output pins, HSOUT, VSOUT, and DE Pins. Hsync input pin (Pin 79). If Hsync is held high or low, activity
will not be detected.
Table XXXII. Power-Down Output Settings
Table XXXVII. Hsync Detection Results
PDO Function
Detect Function
0 Normal operation
1 Three-state 0 No activity detected
The default for this register is 0. (This option works on both the analog and
1 Activity detected
digital interfaces.) The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
14 2 HDCP Address
This bit is used to set the HDCP Slave Port address. 15 6 Sync-on-Green Detect
This bit is used to indicate when sync activity is detected on the
Table XXXIII. HDCP Address Settings Sync-on-Green input pin (Pin 64).
Address Bit Result Table XXXVIII. Sync-on-Green Detection Results
0 0 for HDCP Slave Port
Detect Function
1 1 for HDCP Slave Port
The default for this register is 0.
0 No activity detected
1 Activity detected
14 1 PWRDN
The Sync Processing Block Diagram, Figure 18, shows where this function is
This bit is used to control chip power-down. See the section on implemented.
power management for details about which blocks are actually Note: If no Sync signal is presented on the GREEN video input,
powered down. normal video may still trigger activity.

Table XXXIV. Power-Down Settings 15 5 Vsync Detect

This bit is used to indicate when activity is detected on the
Select Result Vsync input pin (Pin 80). If Vsync is held high or low, activity
0 Power-down will not be detected.
1 Normal operation
Table XXXIX. Vsync Detection Results
The default for this register is 1.
Detect Function
14 0 4:2:2 Output Mode Select
A bit that configures the output data in 4:2:2 mode. This mode 0 No activity detected
can be used to reduce the number of data lines used from 24 1 Activity detected
to 16 for applications using YPbPr graphics signals. A timing The Sync Processing Block Diagram, Figure 18, shows where this function is
diagram for this mode is shown in Figure 9. Recommended implemented.
input and output configurations are shown in Table XXXVI.
In 4:2:2 mode, the RED and BLUE channels can be interchanged 15 4 Digital Interface Clock Detect
to help satisfy board layout or timing requirements, but the This bit is used to indicate when activity is detected on the
GREEN channel must be configured for Y. digital interface clock input.

Table XXXV. 4:2:2 Output Mode Select Table XL. Digital Interface Clock Detection Results

Select Output Mode Detect Function

0 4:4:4 0 No activity detected

1 4:2:2 1 Activity detected
The Sync Processing Block Diagram, Figure 18, shows where this function is
implemented.
Table XXXVI. 4:2:2 Input/Output Configuration

Channel Input Connection Output Format

RED Pr Pb/Pr
GREEN Y Y
BLUE Pr High impedance

REV. A –29–
AD9882
15 3 Active Interface 16 5 AVS Active Vsync
This bit is used to indicate which interface should be active, analog This bit indicates which Vsync source is being used for the analog
or digital. It checks for activity on the analog interface and for interface: the Vsync input or output from the sync separator.
activity on the digital interface, then determines which should be If the override bit (10H, Bit 1) is set to logic 1, then this bit will be
active according to Table XLI. Specifically, analog interface detec- forced to the same state as Bit 0 in Register 10H.
tion is determined by OR-ing Bits 7, 6, and 5 in this register. Digital
interface detection is determined by Bit 4 in this register. If both Table XLIV. Active Vsync Results
interfaces are detected, the user can determine which has priority
via Bit 1 in Register 0FH. The user can override this function Vsync Detect Override
via Bit 2 in Register 0FH. If the override bit is set to logic 1, then Register 16H Register 10H
this bit will be forced to the same state as Bit 1 in Register 0FH. Bit 5 Bit 1 AVS
0 0 0
Table XLI. Active Interface Results 1 0 1
Bits 7, 6, or 5 Bit 4 X 1 Bit 0 in 10H
(Analog (Digital AVS = 0 means Vsync input
Detection) Detection) Override AI AVS = 1 means Sync separator
The override bit is in Register 10H, Bit 1.
0 0 0 Soft
16 4 Detected Vsync Output Polarity Status
Power-Down
(Seek Mode) This bit reports the status of the Vsync output polarity detection
0 1 0 1 circuit. It can be used to determine the polarity of the Vsync
1 0 0 0 output. The detection circuit’s location is shown in the Sync
1 1 0 Bit 1 in 0FH Processing Block Diagram, Figure 18.
X X 1 Bit 1 in 0FH
Table XLV. Detected Vsync Input Polarity Status
AI = 0 means analog interface
AI = 1 means digital interface Vsync Polarity Status Result
The override bit is in Register 0FH, Bit 2.
0 Vsync polarity is active high.
16 7 AHS Active Hsync 1 Vsync polarity is active low.
This bit indicates which Hsync input source is being used by the
PLL (Hsync input or Sync-on-Green). Bits 6 and 7 in Register 16 3 Detected Coast Polarity Status
15H determine which source is used. If both Hsync and SOG This bit reports the status of the coast input polarity detection
are detected, the user can determine which has priority via Bit 3 circuit. The detection circuit’s location is shown in the Sync
in Register 10H. The user can override this function via Bit 4 Processing Block Diagram, Figure 18. This bit only applies to
in Register 10H. If the override bit is set to logic 1, then this the internal Coast and does not apply when Coast is disabled.
bit will be forced to the same state as Bit 3 in Register 10H.
Table XLVI. Detected Coast Input Polarity Status
Table XLII. Active Hsync Results
Hsync Polarity
Hsync Detect SOG Detect Override AHS Status Result
Register 15H Register 15H Register 10H Register 16H
Bit 7 Bit 6 Bit 4 Bit 7 0 Coast polarity is negative/active low.
1 Coast polarity is positive/active high.
0 0 0 Bit 3 in 10H
0 1 0 1 16 2 Key Read Verification
1 0 0 0 This bit reports wherever HDCP keys are detected.
1 1 0 Bit 3 in 10H
X X 1 Bit 3 in 10H Table XLVII. Key Read Verification
AHS = 0 means use the Hsync pin input for Hsync
AHS = 1 means use the SOG pin input for Hsync Detect Function
The override bit is in Register 10H, Bit 4.
0 Not detected
16 6 Detected Hsync Input Polarity Status 1 Detected
This bit reports the status of the Hsync input polarity detection
circuit. It can be used to determine the polarity of the Hsync 1B 7 MDA and MCL Three-State
input. The detection circuit’s location is shown in the Sync The MDA and MCL three-state feature allows the EEPROM to
Processing Block Diagram, Figure 18. be programmed in-circuit. The MDA/MCL port must be three-
stated before attempting to program the EEPROM using an
Table XLIII. Detected Hsync Input Polarity Status external master. The keys will be stored in an I2C compatible
3.3 V serial EEPROM of at least 512 bytes. The EEPROM
Hsync Polarity
should have a device address of A0H.
Status Result
0 Hsync polarity is negative/active low.
1 Hsync polarity is positive/active high.
–30– REV. A
 AD9882
2-WIRE SERIAL CONTROL PORT Data Transfer via Serial Interface
A 2-wire serial control interface is provided. Two AD9882 For each byte of data read or written, the MSB is the first bit of
devices may be connected to the 2-wire serial interface, with each the sequence.
device having a unique address. If the AD9882 does not acknowledge the master device during a
The 2-wire serial interface comprises a clock (SCL) and a write sequence, the SDA remains HIGH so the master can gener-
bidirectional data (SDA) pin. The analog flat panel interface ate a stop signal. If the master device does not acknowledge the
acts as a slave for receiving and transmitting data over the serial AD9882 during a read sequence, the AD9882 interprets this
interface. When the serial interface is not active, the logic levels as “end of data.” The SDA remains HIGH so the master can
on SCL and SDA are pulled HIGH by external pull-up resistors. generate a stop signal.
Data received or transmitted on the SDA line must be stable for Writing data to specific control registers of the AD9882 requires
the duration of the positive-going SCL pulse. Data on SDA must that the 8-bit address of the control register of interest be written
change only when SCL is LOW. If SDA changes state while SCL after the slave address has been established. This control regis-
is HIGH, the serial interface interprets that action as a start or ter address is the base address for subsequent write operations.
stop sequence. The base address autoincrements by one for each byte of data
There are five components to serial bus operation: written after the data byte intended for the base address. If there
are more bytes transferred than there are available addresses, the
∑ Start signal address will not increment and will remain at its maximum value
∑ Slave address byte of 1Eh. Any base address higher than 1Eh will not produce an
∑ Base register address byte acknowledge signal.
∑ Data byte to read or write
∑ Stop signal Data are read from the control registers of the AD9882 in a
similar manner. Reading requires two data transfer operations:
When the serial interface is inactive (SCL and SDA are HIGH),
communications are initiated by sending a start signal. The start The base address must be written with the R/W bit of the slave
signal is a HIGH-to-LOW transition on SDA while SCL is HIGH. address byte LOW to set up a sequential read operation.
This signal alerts all slaved devices that a data transfer sequence Reading (the R/W bit of the slave address byte HIGH) begins at
is coming. the previously established base address. The address of the read
The first eight bits of data transferred after a start signal com- register autoincrements after each byte is transferred.
prise a 7-bit slave address (the first seven bits) and a single To terminate a read/write sequence to the AD9882, a stop signal
R/W bit (the eighth bit). The R/W bit indicates the direction of must be sent. A stop signal comprises a LOW-to-HIGH transition
data transfer: read from (1) or write to (0) the slave device. If the of SDA while SCL is HIGH. The timing for the read/write is
transmitted slave address matches the address of the device (set shown in Figure 16, and a typical byte transfer is shown in
by the state of the SA input pin in Table XLVIII), the AD9882 Figure 17.
acknowledges by bringing SDA LOW on the ninth SCL pulse. A repeated start signal occurs when the master device driving the
If the addresses do not match, the AD9882 does not acknowledge. serial interface generates a start signal without first generating a
stop signal to terminate the current communication. This is used
Table XLVIII. Serial Port Addresses to change the mode of communication (read, write) between the
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 slave and master without releasing the serial interface lines.

A6 A5 A4 A3 A2 A1 A0
(MSB) (LSB)
1 0 0 1 1 0 0
1 0 0 1 1 0 1

SDA

tBUFF tDHO tDSU

tSTASU tSTOSU
tSTAH
tDAL
SCL

tDAH

Figure 16. Serial Port Read/Write Timing

REV. A –31–
AD9882
Serial Interface Read/Write Examples Read from one control register
Write to one control register ∑ Start signal
∑ Start signal ∑ Slave address byte (R/W bit = LOW)
∑ Slave address byte (R/W bit = LOW) ∑ Base address byte
∑ Base address byte ∑ Start signal
∑ Data byte to base address ∑ Slave address byte (R/W bit = HIGH)
∑ Stop signal ∑ Data byte from base address
Write to four consecutive control registers ∑ Stop signal
∑ Start signal Read from four consecutive control registers
∑ Slave address byte (R/W bit = LOW) ∑ Start signal
∑ Base address byte ∑ Slave address byte (R/W bit = LOW)
∑ Data byte to base address ∑ Base address byte
∑ Data byte to (base address + 1) ∑ Start signal
∑ Data byte to (base address + 2) ∑ Slave address byte (R/W bit = HIGH)
∑ Data byte to (base address + 3) ∑ Data byte from base address
∑ Stop signal ∑ Data byte from (base address + 1)
∑ Data byte from (base address + 2)
∑ Data byte from (base address + 3)
∑ Stop signal

SDA BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 ACK

SCL

Figure 17. Serial Interface, Typical Byte Transfer

–32– REV. A
 AD9882

ACTIVITY
SYNC STRIPPER DETECT

NEGATIVE SYNC SEPARATOR

PEAK COMP
CLAMP SYNC INTEGRATOR
SOG 1/S VSYNC

MUX 1
HSYNC IN
SOG
OUT

PLL
ACTIVITY MUX 4
POLARITY
DETECT DETECT

HSYNC HSYNC OUT

MUX 2 CLOCK
GENERATOR PIXEL CLOCK
COAST HSYNC
OUT

POLARITY MUX 5
DETECT

VSYNC IN
VSYNC
OUT

MUX 3
ACTIVITY MUX 6
DETECT HSYNC

DVI VSYNC
DE DE

Figure 18. Sync Processing Block Diagram

Table XLIX. Control of the Sync Block Muxes via the Serial Register

Mux Number(s) Serial Bus Control Bit Control Bit State Result
1 and 2 10H: Bit 3 0 Pass Hsync
1 Pass Sync-on-Green
3 10H: Bit 0 0 Pass Vsync
1 Pass Sync Separator Signal
4, 5, and 6 0FH: Bit 1 0 Pass Analog Interface Signals
1 Pass Digital Interface Signals

REV. A –33–
AD9882
THEORY OF OPERATION Place the 75 W termination resistors (see Figure 1) as close to the
Sync Stripper AD9882 chip as possible. Any additional trace length between the
This section is devoted to the basic operation of the sync pro- termination resistors and the input of the AD9882 increases the
cessing engine. (Refer to Figure 18.) magnitude of reflections, which will corrupt the graphics signal.
The purpose of the sync stripper is to extract the sync signal from Use 75 W matched impedance traces. Trace impedances other
the green graphics channel. A sync signal is not present on all than 75 W will also increase the chance of reflections.
graphics systems; only those with Sync-on-Green. The sync signal The AD9882 has a very high input bandwidth (300 MHz). While
is extracted from the GREEN channel in a two-step process. this is desirable for acquiring a high resolution PC graphics signal
First, the SOG input is clamped to its negative peak (typically with fast edges, it means that it will also capture any high frequency
0.3 V below the black level). Next, the signal goes to a comparator noise present. Therefore, it is important to reduce the amount
with a variable trigger level, nominally 0.15 V above the clamped of noise that gets coupled to the inputs. Avoid running any
level. The output signal is typically a composite sync signal digital traces near the analog inputs.
containing both Hsync and Vsync.
Due to the high bandwidth of the AD9882, sometimes low-pass
Sync Separator filtering the analog inputs can help to reduce noise. (For many
A sync separator extracts the Vsync signal from a composite sync applications, filtering is unnecessary.) Experiments have shown
signal. It does this through a low-pass filter-like or integrator- that placing a series ferrite bead prior to the 75 W termination
like operation. It works on the idea that the Vsync signal stays resistor is helpful in filtering out excess noise. Specifically, the
active for a much longer time than the Hsync signal. So, it rejects part used was the #2508051217Z0 from Fair-Rite, but different
any signal shorter than a threshold value, which is somewhere applications may work best with different bead values. Alternatively,
between an Hsync pulsewidth and a Vsync pulsewidth. placing a 100 W to 120 W resistor between the 75 W termination
The sync separator on the AD9882 is simply an 8-bit digital resistor and the input coupling capacitor can also be beneficial.
counter with a 5 MHz clock. It works independently of the polarity Digital Interface Inputs
of the composite sync signal. (Polarities are determined elsewhere Many of the same techniques that are recommended for the analog
on the chip.) The basic idea is that the counter counts up when interface inputs should also be used for the digital interface inputs.
Hsync pulses are present. But since Hsync pulses are relatively It is important to minimize trace lengths, then make the input
short in width, the counter only reaches a value of N before the trace impedances match the input termination (typically 50 W).
pulse ends. It then starts counting down, eventually reaching Each differential input pair (RX0+, RX0–, RXC+, RXC–, and so on)
0 before the next Hsync pulse arrives. The specific value of N will should be routed together using 50 W strip line routing techniques
vary for different video modes, but will always be less than 255. and should be kept as short as possible. No other components,
For example, with a 1 ms width Hsync, the counter will only reach e.g., no clamping diodes, should be placed on these inputs. Every
5 (1 ms/200 ns = 5). Now, when Vsync is present on the composite effort should be made to route these signals on a single layer
sync the counter will also count up. However, since the Vsync (component layer) with no vias.
signal is much longer, it will count to a higher number M. For
most video modes, M will be at least 255. So, Vsync can be detected Power Supply Bypassing
on the composite sync signal by detecting when the counter Bypassing each power supply pin with a 0.1 mF capacitor is
counts to higher than N. The specific count that triggers detection recommended. The exception is the case in which two or more
(T) can be programmed through the serial register (0EH). supply pins are adjacent to each other. For these groupings of
powers/grounds, it is necessary to have one bypass capacitor.
Once Vsync has been detected, a similar process detects when The fundamental idea is to have a bypass capacitor within about
it goes inactive. At detection, the counter first resets to 0, then 0.5 cm of each power pin. Also, avoid placing the capacitor on
starts counting up when Vsync goes away. In a way similar to the side of the PC board opposite the AD9882, as that interposes
the previous case, it will detect the absence of Vsync when the resistive vias in the path.
counter reaches the threshold count (T). In this way, it will
reject noise and/or serration pulses. Once Vsync is determined The bypass capacitors should be physically located between the
to be absent, the counter resets to 0 and begins the cycle again. power plane and the power pin. Current should flow from the
power plane Æ capacitor Æ power pin. Do not make the power
PCB LAYOUT RECOMMENDATIONS connection between the capacitor and the power pin. Placing a
The AD9882 is a high precision, high speed analog device. In via underneath the capacitor pads, down to the power plane, is
order to derive the maximum performance out of the part, it is generally the best approach.
important to have a well laid out board. The following is a guide It is particularly important to maintain low noise and good
for designing a board using the AD9882. stability of PVD (the clock generator supply). Abrupt changes
Analog Interface Inputs in PVD can result in similarly abrupt changes in sampling clock
Using the following layout techniques on the graphics inputs is phase and frequency. This can be avoided by careful attention to
extremely important. regulation, filtering, and bypassing. It is highly desirable to pro-
vide separate regulated supplies for each of the analog circuitry
Minimize the trace length running into the graphics inputs. This groups (VD and PVD).
is accomplished by placing the AD9882 as close as possible to the
graphics VGA connector. Long input trace lengths are undesirable
because they will pick up more noise from the board and other
external sources.

–34– REV. A
 AD9882
Some graphic controllers use levels of power when active (during Outputs (Data and Clocks)
active picture time) that are substantially different from those used Try to minimize the trace length that the digital outputs have to
when they are idle (during horizontal and vertical sync periods). drive. Longer traces have higher capacitance and require more
This can result in a measurable change in the voltage supplied to current, which causes more internal digital noise.
the analog supply regulator, which can in turn produce changes Shorter traces reduce the possibility of reflections.
in the regulated analog supply voltage. This can be mitigated by
regulating the analog supply, or at least PVD, from a different, Adding a series resistor with a value of 22 W to 100 W can suppress
cleaner, power source (for example, from a 12 V supply). reflections, reduce EMI, and reduce the current spikes inside of
the AD9882. However, if 50 W traces are used on the PCB, the
Using a single ground plane for the entire board is also rec- data output should not need these resistors.
ommended. Experience has repeatedly shown that the noise
performance is the same or better with a single ground plane. A 22 W resistor on the DATACK output should provide good
Using multiple ground planes can be detrimental because each impedance matching that will reduce reflections. If EMI or
separate ground plane is smaller than one common ground current spiking is a concern, use a lower drive strength setting
plane, and long ground loops can result. by adjusting register 14H. If series resistors are used, place them as
close to the AD9882 pins as possible (but avoid adding vias or
In some cases, using separate ground planes is unavoidable. For extra length to the output trace in order to get the resistors closer).
those cases where they must be used, it is recommended that at
least a single ground plane be placed under the AD9882. The loca- If possible, limit the capacitance that each of the digital outputs
tion of the split should be at the receiver of the digital outputs. For drives to less than 10 pF. This can be accomplished easily by
this case, it is even more important to place components wisely keeping traces short and by connecting the outputs to only one
because the current loops will be much longer (current takes the device. Loading the outputs with excessive capacitance will
path of least resistance). The following is an example of a current increase the current transients inside the AD9882, creating
loop: power plane Æ AD9882 Æ digital output trace Æ digital more digital noise on its power supplies.
data receiver Æ digital ground plane Æ analog ground plane. Digital Inputs
PLL The digital inputs on the AD9882 were designed to work
Place the PLL loop filter components as close to the FILT pin with 3.3 V signals, but are tolerant of 5.0 V signals. No extra
as possible. components need to be added if 5.0 V logic is used.
Do not place any digital or other high frequency traces near Any noise that gets onto the Hsync input trace will add jitter to
these components. the system. Therefore, minimize the trace length and do not
run any digital or other high frequency traces near it.
Use the values suggested in the data sheet with 10% or smaller
tolerances. Voltage Reference
Bypass with a 0.1 mF capacitor. Place as close to the AD9882
pin as possible. Make the ground connection as short as possible.

REV. A –35–
AD9882
OUTLINE DIMENSIONS

100-Lead Quad Flatpack [LQFP]

(ST-100)
Dimensions shown in millimeters

C02889–0–1/03(A)
16.00 BSC SQ
1.60 MAX
14.00 BSC SQ

0.75 12ⴗ 100 76

0.60 1 75
TYP
0.45
SEATING
PLANE

12.00
TOP VIEW
(PINS DOWN) REF
0.20
0.15 0.09
0.05 7ⴗ
3.5ⴗ VIEW A
0.08 0ⴗ
MAX LEAD SEATING 25 51
COPLANARITY PLANE 26 50

0.27
VIEW A 0.50 BSC
0.22
ROTATED 90ⴗ CCW
0.17

COMPLIANT TO JEDEC STANDARDS MS-026BED

THE ACTUAL POSITION OF EACH LEAD IS WITHIN 0.08 OF ITS IDEAL
POSITION WHEN MEASURED IN THE LATERAL DIRECTION

Revision History
Location Page
1/03—Data Sheet changed from REV. 0 to REV. A.
Edits to PIN CONFIGURATION headings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Edits to Table IX . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

PRINTED IN U.S.A.

–36– REV. A