COMPUTER ORGANIZATION AND ARCHITECTURE

UNIT-II / PART-2
CENTRAL PROCESSING UNIT
I. GENERAL REGISTER ORGANIZATION
II. INSTRUCTION FORMATS
III. ADDRESSING MODES
IV. DATA TRANSFER AND MANIPULATIONS
V. PROGRAM CONTROL

Introduction:

All the data processing operations are done at central processing unit also called as CPU. The
CPU consists of 3 blocks as shown in fig.1.
1. Control Unit: Initiates the transfer of information among registers and instructs the
ALU as to which operation to perform.
2. Register Set: stores the intermediate data used during the execution of the instruction.
3. ALU: performs the required microoperations as per the instruction.

Fig 1: Block Diagram of CPU

I. GENERAL REGISTER ORGANIZATION:

Memory access is the most time consuming in the computer. Instead of storing the
intermediate values arose due to microoperations like multiplication, its convenient to store
these values in processor register.

Common bus is used to connect when the computer employs large number of registers. These
registers communicate with each other to share the information during data transfer or during
some microoperations. We need to design a common unit that performs arithmetic, logic and
shift operations by the processor.

The fig.2 shows the common unit that performs arithmetic, logic and shift operations. Also the
results are loaded onto the registers.

G. SRUJAN REDDY 1
 COMPUTER ORGANIZATION AND ARCHITECTURE

Fig. 2: Block Diagram to understand the data flow between registers

The block:
a. Consists of 7 registers R1 through R7. All the registers are connected with a common
clock. Considering the data is transmitted in-out of the registers at the rising edge of the
clock, one of seven registers is selected by the 3x8 decoder with 3-bit inputs SelD (SelD2,
SelD1, SelD0) and 8 output lines is shown below along with selection of registers
SelD2 SelD1 SelD0 Register Selected
0 0 0 -
0 0 1 R1
0 1 0 R2
0 1 1 R3
1 0 0 R4
1 0 1 R5
1 1 0 R6
1 1 1 R7

G. SRUJAN REDDY 2
 COMPUTER ORGANIZATION AND ARCHITECTURE

b. The output of the registers is connected to two 8x1 multiplexer MUX-A and MUX-B.
selection lines SelA and SelB are the control signals used for selecting one of the register.
The registers connected are as follows.

SelA2 SelA1 SelA0 Output on Bus-A

0 0 0 Data coming from Input terminal
0 0 1 Data coming from R1 register
0 1 0 Data coming from R2 register
0 1 1 Data coming from R3 register
1 0 0 Data coming from R4 register
1 0 1 Data coming from R5 register
1 1 0 Data coming from R6 register
1 1 1 Data coming from R7 register

SelB2 SelB1 SelB0 Output on Bus-B

0 0 0 Data coming from Input terminal
0 0 1 Data coming from R1 register
0 1 0 Data coming from R2 register
0 1 1 Data coming from R3 register
1 0 0 Data coming from R4 register
1 0 1 Data coming from R5 register
1 1 0 Data coming from R6 register
1 1 1 Data coming from R7 register

c. The output of each multiplexer is sent on Bus-A and Bus-B as an input to ALU. The
control lines OPR will decide the operation being performed in the ALU. The output of
ALU is readily available on the output common-bus and will be either sent to a register or
to an output device. The encoding of OPR control lines are as shown in table.

OPR Operation
00000 Transfer A
00001 Transfer B
00010 A+B
00011 A-B
00100 Decrement A
00101 Decrement B
00110 Increment A
00111 Increment B
01000 A and B
01001 A or B

d. To store the output of ALU into a register, a 3x8 decoder is used to connect the output line
of ALU to one of the register. For a particular input value of the decoder, the output

G. SRUJAN REDDY 3
 COMPUTER ORGANIZATION AND ARCHITECTURE

corresponding to the selected register will active LD(load) pin of the register and the result
is stored in the selected register.

Let’s understand the operation

R1R2+R3
Let the data present in R2 register be moved to MUX-A, for this the select lines SelA
should be 010. Let the data present in R3 be moved to MUX-B, for this the select lines
SelB2 should be 011. With this the ALU has two input values coming from Bus-A and
Bus-B. To add R2 and R3, the OPR is 00010. The output of ALU is to be stored in R1
register, for this SelD=010

The control signals are as follows:

SelA = 010
SelB = 011
SelD = 010
OPR = 00010
We know that the control signals grouped together to form a control word. The control
word for the above example is

Sel SelB Sel OPR

A D
010 011 010 00010

Similarly, we can generate many control words for other operations like SUB, INC, CMP,
AND, OR, etc.

All these control words are stored in the memory unit, and the memory unit that stores
these control words is referred as CONTROL MEMORY. By reading the control word from
the memory, we can initiate a desired sequence of operations. This type of control is
referred as the MICROPROGRAMMED CONTROL.

G. SRUJAN REDDY 4
 COMPUTER ORGANIZATION AND ARCHITECTURE

II. INSTRUCTION FORMATS

A computer have a variety of instruction format. It is the responsibility of the control unit in
the CPU to interpret each instruction code and provide necessary control functions to process
the instruction.
The instruction format is represented as a rectangular box is divided into fields and each field
will depict a particular information as shown below
i. Opcode field that species operation to be performed.
ii. Mode field that specifies the effective address
iii. Address field that specified a memory address or a processor address.
Operations specified by the computer instruction is executed on the data stored either stored in
memory or in the processor.
Operand residing in memory are specified by memory address and
Operands residing in the registers are specified by register address.
Note: the register address for a 2k number of registers is k-bits.
Computers can have variety of instructions with varying lengths containing varying number of
addresses. Most computer falls into 3 types of computer organizations.
i. Single Accumulator Organization: All operations are performed with an implied
accumulator register. The instruction format in this type of organization used only one address
filed.
Ex: ADD X  it adds the operand present in memory address X with the operand present in
AC and result are stored in AC, represented as
AC  AC + M[X]

ii. General Register Organization: This type of register organization employs three addresses,
two addresses, one address fields. Let us understand these with an example.

Consider the mathematical expression X=(A+B)*(C+D), where A,B,C,D,X are the memory
locations.

a. Three Address Instructions: In this type, the instruction use 3 address fields. Also, the
address fields can be a register address and memory address
Instructions for X=(A+B)*(C+D) is:

ADD R1, A, B R1 M[A]+M[B]

ADD R2, C, D R2 M[C]+M[D]
MUL X, R1, R2 M[X]R1*R2
Here, we used 2 processor registers R1 and R2. Advantage of three address
instruction is that the instructions are short. Disadvantage is that the binary coded
instruction required too many bits.

b. Two Address Instructions: In this type, the instructions use 2 address fields. Also, the
address fields can be a register address and memory address
Instructions for X=(A+B)*(C+D) is:
G. SRUJAN REDDY 5
 COMPUTER ORGANIZATION AND ARCHITECTURE

MOV R1, A R1 M[A]

ADD R1, B R1 R1+M[B]
MOV R2, C R2M[C]
ADD R2, D R2R2+M[D]
MUL R1,R2 R1R1*R2
MOV X, R1 M[X]R1
We used MOV instruction to move the data to/from memory and register.

c. One address Instructions: here, it uses one address field, but the AC is used as implied
address for all data manipulation operations.
Instructions for X=(A+B)*(C+D) is:

LOAD A ACM[A]
ADD B ACM[A] +B
STORE T M[T]AC
LOAD C ACM[C]
ADD D ACM[D] + D
MUL T ACM[T] * AC
STORE X M[X]AC

iii. Stack Organization: A stack is a storage device that stored information in such a manner
that the items stored last is the first item retrieved. In simple words, stack is a last-in first-out
(LIFO). Here 2 instructions PUSH and POP are used where PUSH is used to sent the data into
the stack memory and POP is used to sent the data out from the stack memory. However, the
PUSH and POP are one address instructions and all other instructions used are zero address
instructions. Instructions for X=(A+B)*(C+D) is:

PUSH A TOSA
PUSH B TOSB
ADD TOS A+B
PUSH C TOS C
PUSH D TOS D
ADD TOS C+D
MUL TOS(C+D)*(A+B)
POP X M[X] TOS

iv. Reduced Instruction Set Computer (RISC): In the RISC architecture, the LOAD and
STORE instructions are restricted to data transfer between memory and processor registers
only. And all the other instructions should only use the processor register (memory is not
involved). There is no restriction on the use of address fields.
Instructions for X=(A+B)*(C+D) is:

LOAD R1, A R1M[A]

LOAD R2, B R2M[B]
LOAD R3, C R3M[C]
LOAD R4, D R4M[D]
G. SRUJAN REDDY 6
 COMPUTER ORGANIZATION AND ARCHITECTURE

ADD R1, R1, R2 R1 R1 + R2

ADD R3, R3, R4 R3 R3 + R4
MUL R1, R1, R3 R1 R1*R2
STORE X, R1 M[X]R1

Note: LOAD and STORE instructions uses memory and processor register addresses.
ADD, MUL instructions uses register address field only (memory address is not used)

G. SRUJAN REDDY 7
 COMPUTER ORGANIZATION AND ARCHITECTURE

III. ADDRESSING MODES

The operation field of an instruction specifies the operation to be performed. This operation
must be executed on some data stored in computer registers or memory words. The way the
operands are chosen during program execution is dependent on the addressing mode of the
instruction.

The addressing mode specifies a rule for interpreting or modifying the address field of the
instruction before the operand is actually referenced

Different addressing modes are as follows:

i. Implied Addressing Mode
ii. Immediate Addressing Mode
iii. Register Addressing Mode
iv. Register Indirect Addressing Mode
v. Autoincrement and Autodecrement Addressing Mode
vi. Direct Addressing Mode
vii. Indirect Addressing Mode
viii. Relative Addressing Mode
ix. Indexed Addressing Mode
x. Base Register Addressing Mode

i. Implied Addressing Mode:

In this mode the operands are specified implicitly in the definition of the instruction. For
example, the instruction "complement accumulator” is an implied-mode instruction because the
operand in the accumulator register is implied in the definition of the instruction

Ex: ADD, MUL from previous example is a implied mode (here the operand is present in AC)

ii. IMMEDIATE ADDRESSING MODE:

In this mode, the operand is mentioned in the instruction as a immediate value. This immediate
operand takes the place of the address in the instruction format. i.e., in immediate addressing
mode instruction has a operand field rather than a address field. This addressing mode do not
have an effective address

Ex: ADD R1,55h  the immediate value 55h is added to the processor register R1
MOV R2,4Ah the immediate value 4Ah is moved to the processor register R2

iii. REGISTER ADDRESSING MODE:

In this addressing mode, the operands reside in the registers of a CPU. A k-bit address is used
to specify a CPU with 2k registers.

Ex: ADD R1, R3  the operands are present in processor registers R1 and R3
MOV R2, AC  the operands are present in R1 and Accumulator registers

iv. REGISTER INDIRECT ADDRESSING MODE:

In this addressing mode, the content present in the register gives the address of the operand
i.e., the register holds the effective address, not the operand. Before using the register indirect
G. SRUJAN REDDY 8
 COMPUTER ORGANIZATION AND ARCHITECTURE

addressing mode, the programmer needs to load the effective address into the processor
register in the previous instruction.

Ex: consider the operand is at memory address A6h, we need to first move this address into a
processor register and then use register indirect addressing mode to get the operand. This is as
shown below

MOV R1, A6h R1  A6

ADD R2, R1 R2  R2 + [A6]

v. AUTOINCREMENT AND AUTODECREMENT ADDRESSING MODE

This is similar to the Registe Indirect addressing mode, except that the register is incremented
or decremented after its value is used to access memory. When the address stored in the
register refers to ta table of data in memory, then it is needed to increment or decrement the
register after each access to the table.
Ex: Consider an example where we need to add the content of a table present in memory as
shown below

Memory Address Operand

00AAh 55h
00ABh 42h
00ACh 21h
00ADh 77h
00AEh 63h

If the addressing mode is autoincrement then,

MOV R1, AAh R1  AA
ADD R2, R1 R2  R2 + [AA] ie., R2  R2+55h
ADD R2, R1 R2  R2 + [AB] ie., R2  R2+42h
ADD R2, R1 R2  R2 + [AC] ie., R2  R2+21h
ADD R2, R1 R2  R2 + [AD] ie., R2  R2+77h
ADD R2, R1 R2  R2 + [AE] ie., R2  R2+63h

vi. DIRECT ADDRESSING MODE

In this addressing mode, the effective address is the address filed of the instruction. The
operand resides in the memory and the effective address is given in the instruction.
Ex: ADD 385h AC  AC + [385h]

G. SRUJAN REDDY 9
 COMPUTER ORGANIZATION AND ARCHITECTURE

AC

vii. INDIRECT ADDRESSING MODE:

In this addressing mode,

effective address = data present in the address mentioned in instruction
the register used in the computation can be a program counter, indexed register or a base
register

Ex: ADD 385h AC  AC + [1238]

AC

viii. RELATIVE ADDRESSING MODE:

In this addressing mode, the effective address is the sum of content of program counter and the
address part of the instruction
effective address = content of program counter + address part of instruction
this addressing mode is best understood by the below example. Let program counter contains
the number 825 and the address part of the instruction contains the number 24. The instruction
at location 825 is read from memory during the fetch phase and the program counter is then
incremented by one to 826. The effective address computation for the relative address mode is
826 + 24 = 850.

G. SRUJAN REDDY 10
 COMPUTER ORGANIZATION AND ARCHITECTURE

ix. INDEXED ADDRESSING MODE:

In this addressing mode, the

effective address = content of index register + address part of instruction

Index Value is the distance between the beginning address and the address of the operand. This
index value is stored in index register.

x. BASE REGISTER ADDRESSING MODE:

In this addressing mode,

effective address = content of base register + address part of instruction
The base register addressing mode is used in computers to facilitate the relocation of programs
in memory. When programs and data are moved from one segment of memory to another, as
required in multiprogramming systems, the address values of instructions must reflect this change
of position.

Numerical Example to understand the addressing modes.

In the example, the MOD field can be any of the addressing mode. The instruction is a 2-word
instruction and hence it occupies 2 memory locations i.e., 200 and 201. The operation is a load to
G. SRUJAN REDDY 11
 COMPUTER ORGANIZATION AND ARCHITECTURE

accumulator and the operand to be loaded is mentioned by the addressing mode. Initially, the
content are as follows. Index register XR=100, PC=200, R1=400.

Listed is the effective address the data loaded into AC for different addressing modes

Addressing Mode Effective Address Data Loaded to AC

Immediate Mode 201 500
Register Mode No effective address for this mode 400
Register Indirect 400 700
Direct Memory 500 800
Indirect Memory 800 300
Autoincrement 401 Xyz
Autodecrement 399 450
Relative 202+500 = 702 325
Indexed Mode 100+500 = 600 900

G. SRUJAN REDDY 12
 COMPUTER ORGANIZATION AND ARCHITECTURE

VI. DATA TRANSFER / DATA MANIPULATION

The computer instructions are classified as

i. Data Manipulation Instructions
ii. Data Transfer Instructions
iii. Program Control Instructions
Data Transfer Instructions cause transfer of data from one location to the other without changing
the data bits.
Data Manipulation Instructions are result of arithmetic, logic and shift operations
Program control instructions are the decision-making instructions where by the flow of execution
is altered.

i. Data Transfer Instructions:

Data transfer instructions move data from one place in the computer to another without changing
the data content. The most common transfers are between memory and processor registers,
between processor registers and input or output, and between the processor registers themselves.
The table below shows the list of 8 data transfer instructions.

Name Mnemonic Comment

Load LD Load the AC with data from memory
Store ST Store the memory with data from AC
Move MOV Moves the data to/from memory/register
Exchange XCH Exchanges content of
Input IN Inputs the data from input device
Output OUT Outputs the data to output device
Push PUSH Inserts data into the stack
Pop POP Delete the data from the stack.

ii. Data Manipulation Instructions:

Data manipulation instructions perform operations on data and provide the computational
capabilities for the computer. Data manipulation instructions are divided into 3 categories.
a. Arithmetic Instructions
b. Logical Instructions
c. Shift Instructions
a. Arithmetic Instructions:
Addition, subtraction, multiplication and division are few of basic arithmetic operations.
Apart from these, the processor also has few operations where the carry bit also is to be
included in addition operation. Similar is the case with subtraction. List of arithmetic
instructions are

G. SRUJAN REDDY 13
 COMPUTER ORGANIZATION AND ARCHITECTURE

Name Mnemonic
Increment INC
Decrement DEC
Addition ADD
Subtraction SUB
Multiplication MUL
Division DIV
Addition with carry ADDC
Subtraction with borrow SUBB
2’s complement / Negate NEG

b. Logical and Bit Manipulation Instructions

Logical instructions perform binary operations on strings of bits stored in registers. They are
useful for manipulating individual bits or a group of bits that represent binary-coded
information. The logical instructions consider each bit of the operand separately and treat it as
a Boolean variable.

Name Mnemonic Comment

Clear CLR Clear the content of register
Complement COM Complement the register
AND AND ANDing
OR OR ORing
Exclusive-OR XOR XORing
Clear Carry CLRC Clears the carry bit i.e., C=0
Set Carry SETC Sets the carry bit i.e., C=1
Complement Carry COMC Carry bit is complemented
Enable Interrupt EI Enables the interrupt flag
Disable Interrupt DI Disables the interrupt flag

c. Shift Instructions:
Shift instructions are used to shift the data either to the left or to the right by the number of bits
mentioned in the instructions. By default, the number of shifts is 1. If the number of shifts are
more than 1, the same has to be mentioned in the instruction.

Listed are the shift instructions

Name Mnemonic Comment

Logical Shift Left SHL
Logical Shift Right SHR
Arithmetic shift right SHRA
Arithmetic shift left SHLA
rotate shift left ROL
rotate shift right ROR
rotate right through carry RORC LSB moves to Carry bit and
the carry bit moves to MSB
rotate left through carry ROLC MSB moves to carry bit and
the carry bit moves to LSB.
G. SRUJAN REDDY 14
 COMPUTER ORGANIZATION AND ARCHITECTURE

VII. PROGRAM CONTROL INSTRUCTIONS:

We know that that instructions are stored in the memory in the successive memory
locations. These instructions are fetched and executed. Each time an instruction is
executed, the program counter is loaded with address of the next instruction to be
executed.

The data transfer and data manipulation instructions are executed in a sequential order.
When a program control instruction is encountered, causes changes in the value of
program counter and the order of execution is altered. This results in transfer of control to
another segment.

Few of the program control instructions are mentioned in the table below.

Name Mnemonic Comment

Branch BR Branche to the address specifies in the
instruction
Jump JMP Jumps to the address specified in the
instruction
Skip SKIP Skip the next instruction and executed the
immediate instruction after SKIP
Call CALL Calls the subroutine
Return RET Return to the main program from the
subroutine
Compare CMP Compares two values using subtraction
operation
Test TST Performs ANDing

The branch and jump instructions are used interchangeably except that they are used
during different addressing nodes. The Branch instruction is a one address instruction. The
format for branch instruction is

BR ADR

where ADR is the address of the next instruction to be executed. i.e., the PC will be loaded
with ADR.

The skip instruction is a zero-address field, a conditional skip instruction will skip the next
instruction if condition is met and if the condition is nor met then the next instruction is
executed.

The call and return instruction are used in subroutines. A call instruction in the main
program will transfer the control to the starting address of the subroutine and the
instructions in the subroutine are executed, the last instruction in the subroutine is Return
which transfers the control to the main memory and executed the next instruction after call
instruction.

G. SRUJAN REDDY 15
 COMPUTER ORGANIZATION AND ARCHITECTURE

Note: Main Program and Subroutine are separate set of instructions.

Compare instruction is used to compare 2 numbers. During comparison, subtraction is

performed on the numbers and the outcome are equal, greater or lesser. During the
comparison operation, certain status bits are altered. Few examples of status bits are
SIGN(S), ZERO(Z), CARRY(C), OVERFLOW(V). Let us now discuss about the status bits
Status Bits:
Status bits are also called as Condition-codes or flag bits. The outcome of the operations in
the ALU are connected to the status bits as shown below with a 4-bit status register. The
status bits are SIGN(S), ZERO(Z), CARRY(C), OVERFLOW(V):

Consider 2 inputs A (A7 – A0) and B (B7 – B0), each of 8-bit in length is connected to the
ALU. Let F (F7 – F0) be the output of ALU. Let the carry bits generated during ALU
operation be C0-C7 and let C8 be the final carry generated due to bits A7 and B7.

CARRY (C): Bit C is set to 1 if the carry bit C8 is 1

Bit C is reset/cleared to 0 if the carry bit C8 is 0.

SIGN(S): Bit S is set to 1 if the bit F7 is 1

Bit S is reset/clared to 0 if the bit F7 is 0
ZERO(Z): if all bits of result is 0 then bit Z is set to 1, else it is reset/cleared to 0

OVERFLOW(V): overflow is the condition when negative numbers are in 2’s complement
representation.
If XOR of bits C7 and C8 results in 1, bit V is set to 1 and
if the XOR results in a 0, bit V is cleared/reset to 0

Example:

Carry bits= 1 1 1 1 1 1 1 1 0 carry bits C7 and C8 are 1

A= 10100111
G. SRUJAN REDDY 16
 COMPUTER ORGANIZATION AND ARCHITECTURE

+ B= 01111011
---------------------------
F= 100100010 F7 = 0

Thus, C = 1, V =0, Z=0, S= 0

Conditional Branch Instructions:

Listed are few of the conditional branch instructions

Each branch instruction starts with B. When a opposite condition is to be checked then we
insert letter N making the branch instruction as BN. Thus, BZ is branch on Zero, BNZ is
Branch on No Zero.

Thus, Branch on Zero checks for Z=1

Branch on not zero checks for Z=0
Branch on Carry checks for C=1
Branch on No Carry checks for C=0
Branch on Plus checks for S=0
Branch on minus checks for S=1

The above instructions are applicable only for the unsigned comparison. Where the results
after comparison are Higher, Equal and Lower

* Please elaborate at least 2 instructions

G. SRUJAN REDDY 17
 COMPUTER ORGANIZATION AND ARCHITECTURE

The above instructions are applicable for signed comparison, where the results are
Greater, Equal, Lesser

* Please elaborate at least 2 instructions

VIII. SUBROUTINE CALL and RETURN

A subroutine is a self-contained sequence of instructions that performs a given

computational task.

During the execution of a program, a subroutine may be called to perform its function
many times at various points in the main program. Each time a subroutine is called, a branch is
executed to the beginning of the subroutine to start executing its set of instructions. After the
subroutine has been executed, a branch is made back to the main program

The instruction that transfers program control to a subroutine is known as

i. call subroutine,
ii. jump to subroutine,
iii. branch to subroutine
iv. branch and save address
A call subroutine instruction consists of an operation code together with an address that specifies
the beginning of the subroutine. The instruction is executed by performing two operations: (1) the
address of the next instruction available in the program counter (the return address) is stored in a
temporary location so the subroutine knows where to return, and (2) control is transferred to the
beginning of the subroutine. The last instruction of every subroutine, commonly called return
from subroutine transfers the return address from the temporary location into the program counter.
This results in a transfer of program control to the instruction whose address was originally stored
in the temporary location.
Different computers use a different temporary location for storing the return address. The most
efficient way is to store the return address in a memory stack. The advantage of using a stack for
the return address is that when a succession of subroutines is called, the sequential return
addresses can be pushed into the stack. The return from subroutine instruction causes the stack to

G. SRUJAN REDDY 18
 COMPUTER ORGANIZATION AND ARCHITECTURE

pop and the contents of the top of the stack are transferred to the program counter. In this way, the
return is always to the program that last called a subroutine. A subroutine call is implemented with
the following microoperations.
SP SP – 1 Decrement Stack Pointer
M[PC] PC Push content of PC onto the stack
PC Effective address Transfer Control to the subroutine
If another subroutine is called by the current subroutine, the new return address is pushed to the
stack. The instructions that returns from the last subroutine is implemented by the following
microoperation.
PC M[SP] POP stack and transfer to PC
SP SP+1 Increment Stack Pointer
By using a subroutine stack, all return addresses are automatically stored by the hardware in one
unit. The programmer does not have to be concerned or remember where the return address was
stored.
IX. INTERRUPTS:
Program interrupt refers to the transfer of program control from a currently running program to
another service program as a result of an external or internal generated request. Control returns to
the original program after the service program is executed.
The interrupt procedure is, in principle, quite similar to a subroutine call except for three
variations:
(1) The interrupt is usually initiated by an internal or external signal rather than from the
execution of an instruction (except for software interrupt as explained later)
(2) the address of the interrupt service program is determined by the hardware rather than from
the address field of an instruction; and
(3) an interrupt procedure usually stores all the information necessary to define the state of the
CPU rather than storing only the program counter
After a program has been interrupted and the service routine been executed, the CPU must return
to exactly the same state that it was when the interrupt occurred.
The state of the CPU at the end of the execute cycle (when the interrupt is recognized) is
determined from:
1. The content of the program counter
2. The content of all processor registers
3. The content of certain status conditions

G. SRUJAN REDDY 19
 COMPUTER ORGANIZATION AND ARCHITECTURE

The collection of all status bit conditions in the CPU is sometimes called program status word or
PSW. The PSW is stored in a separate hardware register and contains the status information that
characterizes the state of the CPU.
Typically, it includes the status bits from the last ALU operation and it specifies the interrupts that
are allowed to occur and whether the CPU is operating in a supervisor or user mode. Many
computers have a resident operating system that controls and supervises all other programs in the
computer. When the CPU is executing a program that is part of the operating system, it is said to
supervisor mode be in the supervisor or system mode. certain instructions are privileged and can
be executed in this mode only. The CPU is normally in the user mode when executing user
programs. The mode that the CPU is operating at any given time is determined from special status
bits in the PSW.
Types of Interrupts
There are three major types of interrupts that cause' a break in the normal
execution of a program. They can be classified as:
1. External interrupts
2. Internal interrupts
3. Software interrupts
External interrupts come from input-output (I/O) devices, from a timing device, from a circuit
monitoring the power supply, or from any other external source. Examples that cause external
interrupts are I/O device requesting transfer of data, I/O' device finished transfer of data, elapsed
time of an event, or power failure
Internal interrupts arise from illegal or erroneous use of an instruction or data. Internal
interrupts are also called traps. Examples of interrupts caused by internal error conditions are
register overflow, attempt to divide by zero, an invalid operation code, stack overflow, and
protection violation. These error conditions usually occur as a result of a premature termination of
the instruction execution
External and internal interrupts are initiated from Signals that occur in the hardware of the CPU.
Software interrupt is initiated by executing an instruction. Software interrupt is a special call
instruction that behaves like an interrupt rather than a subroutine call. It can be used by the
programmer to initiate an interrupt procedure at any desired point in the program.

G. SRUJAN REDDY 20