Basic Computer Organization and

Design
 CPU Organization
Block diagram of a complete processor:
 CPU Organization
Block diagram of a complete processor- Description:

Instruction Unit: Role of this unit is to fetch the instructions from the instruction cache. In
case the required instruction is not available in instruction cache, the instruction unit fetches it
from the main memory.

Instruction Cache: A processor provides instruction cache and data cache for storing
instructions and data, respectively.

Processing Units: There are two processing units provided by the processor: integer unit to
process the integer data and floating point unit to process floating-point data. Both the
processing units receive the respective data from the data cache.

Bus Interface Unit: It is responsible for controlling the interface of processor to system bus,
main memory module and I/O module.
 CPU Organization
The design of an instruction set for a computer depends on the way in which the CPU Iis
organized. There are three different CPU organization with certain specific instructions:
1. Single accumulator organization
2. General register organization.
3. Stack organization

1. Single Accumulator Based:


It is a simple CPU in which accumulation register is used implicitly for processing all
instructions of a program and intermediate results are stored into this register.

One address field used for instruction.

Example: MULT X; where X is address of the operand. The instruction performs operations
like- AC <- AC * M[X]
General Register Based CPU Organization

Multiple general purpose registers are used.

Uses two or three address fields in instruction format.

e.g. MULT R1, R2, R3 {R1 <- R2 * R3}

MULT R1, R2 {R1 <- R1 * R2}
 
Stack Based CPU Organization
Stack based computer operates instructions based on a data structure called stack. A stack
is list of data words with LIFO access method that is included in the CPU of most
computers. A portion of memory unit used to store operands in successive locations can be
considered as a stack in computers. A portion of memory unit used to store operands in
successive locations can be considered as a stack in computers. The register that holds the
address for the top most operand in the stack is called a stack pointer (SP). The two
operations performed on the operands stored in a stack are the PUSH and POP. PUSH –
write data, POP – Read data.
Call -> PUSH @RET

RET -> POP @RET

PUSH:

SP <- SP + 1
M[SP] <- DR
If (SP = 0 )
Then (FULL <- 1)
EMPTY <- 0

POP:

DR <- M[SP]
SP <- SP – 1
If (SP = 0 )
then (EMPTY <- 1)
FULL <- 0
Infix expression: (4*5)+(5*6) = Postfix expression 4 5 * 5 6* +

6
5 30
5 5
4 20 20 20 50
4 20
 Bus Interconnection Structure


Internal data paths - are needed for moving the
data from one register to another or between the
ALU and CPU.

External data paths - for transferring the data
from register to memory or I/O devices.
 Bus Interconnection Structure

A system bus comprises of 50 to hundreds of separate lines with each line having
a specific function and can be categorized into three groups: (see next slides)

Data Lines: These lines are used for transferring data between
different system modules and are collectively known as data bus. It
may consist 32 to hundreds of separate data lines. Number of lines
present in a data bus is the width of the data bus.

Address Lines: These lines are used to carry the address of the
source or destination of data on the data bus. The set of these lines
are called address bus. The width of address bus specifies the
maximum possible memory supported by a system
16

e.g. 16-bit address bus supports 2 = 65536 bytes of memory size

Control Lines - These lines are used control the access and use of
data and address bus and set of these lines is called control bus.
They are used to transmit command and timing signals between
system modules. Some typical control lines.
Bus request: It indicates that some module wants to gain control
Bus grant: It indicates that the bus request from the requesting
module has beengranted.
I/O read: It indicates to transfer the data from the addressed I/O
port to the data bus.
I/O write: It indicates to transfer the data present on the data bus
to the address I/O port.
Transfer ACK: It indicates that the data has been taken from or
placed on the data bus.


Interrupt request: It indicates a pending interrupt.

Interrupt acknowledgement: It indicates an acknowledgement to
the pending interrupt.
Memory read: It indicates to place the data from the memory
location whose address is specified on the address bus onto the
data bus.
Memory write: It indicates to store the data placed on data bus
into the memory location whose address is specified bus.
 Single Bus Structure

Advantages:
1. Cost effective as it employes common data signalling paths for multiple devices.
2. Since all the modules are connected to a shared transmission medium, each
module can receive signals transmitted by any other module connected the bus.
3. It is flexible as new modules can be attached very easily.
Disadvantages:
1. All data transfers are managed via common bus so it has slow speed.
2. The control over the bus may become complicated when multiple module attempt
to use the single bus.
3. The performance of the single bus structure degrades when a large number of
devices are connected to the bus.
Multiple Bus Structure
 Multiple Bus Structure
Advantages:
1. It speeds up the data transfer process.
2. Increases efficiency and performance of computer system.
3. Flexible because each bus is dedicated to a single type of
device.

Disadvantage:
1. It is costlier.
2. Requires multiple interfaces to control multiple connections of
buses
Basic computer registers
connected to common bus

Registers PC, AR, DR, AC, IR in the diagram are already
discussed.

Input registers(INPR)- It is an 8-bit register that is used to hold
the input character received from an input device.

Output register(OUTR)- It is an 8-bit register that is used to hold
the character for an output device.

Temporary register(TR)- It is a 16-bit register that is used to
hold the data generated during the execution of an operation.
 Types of computer instruction
The basic computer consists of three instruction code formats with each format consisting of
16 bit. In each instruction format, 3 bits are reserved for opcode, 1 bit for mode and the
remaining bits depend on the opcode.

Memory-reference instruction:
15 14 12 11 0

I Opcode Address

Mode Operation code Address

th
Address part specifies a memory address. The 15 bit, I bit, is used to specify the addressing
mode. This bit is set to 1 for indirect address and 0 for direct address. The 3-bit opcode
varies from 000 through 110.
Symbol Description
AND AND memory word to AC
ADD Add memory word to AC
LDA Load memory word to AC
STA Store content of AC in memory
BUN Branch unconditionally
BSA Branch and Save return address
ISZ Increment and Skip if zero
 Register-reference Instruction

In this code 3 bit opcode is 111, and I = 0.

This instruction specifies an operation or a test on AC register.

Since an operand from memory is not required, the remaining 12 bits(0 to 11) are used to
determine the operations or the text that is to be executed.

15 12 11 0
Opc- Register Operation
ode
Symbol Description

CLA Clear AC

CMA Complement AC

CIR Circulate Right AC and E

CIL Circulate Left AC and E

INC Increment AC

HLT Halt computer

 Input/Output Instruction
It also consists 3-bit opcode of an I/O instruction. It is 1111. The rest 12 bits specifiy the type
of operation.
Symbol Description

15 12 11 0 INP Input character to AC

1111 I/O Operation OUT Output character from AC

SKI Skip on input flag

SKO Skip on output flag

ION Interrupt enable on

IOF Interrupt enable off

 Instruction Length
Length of an instruction basically depends on the number of address fields used.
The advantagees and disadvantages of using number of addresses in an instruction are
summarized below:

The fewer the address, the shorter the instruction. Long instructions with multiple addresses
usually require more complex decoding and processing circuits.

Limiting the number of addresses also limits the range of functions each instruction can
perform.

Fewer addresses means more primitive instructions, and longer programs are needed.

Storage requirements of shorter instructions and longer programs tend to balance; larger
program requires longer execution time.
`
Instruction Cycle
 Addressing Mode
The different ways in which the location of an operand is specified in an
instruction are referred to as addressing modes.
Advantage:
1. It gives programming versatility or flexibility to the programmers with
respect to the number of instructions and execution time by providing arious
addressing modes.
2. To reduce length of instructions or the size of programs.

A computer generally has variety of addressing modes.

Class I: Here no address field is used

1. Implied (or Inherent) mode – Operands are indicated implicitly by the

instruction. Accumulator is generally used to hold the operands.
a. RAL;- Rotates content of accumulator left through carry
b. CMA; – Complement content of accumulator.

2. Immediate mode – The operand is mentioned explicitly in the instruction.

a. MVI A, 06; Loads binary value of 06 to the accumulator
b. ADI 05; Adds the binary value of 05 to the AC.

3. Stack addressing mode – Stack-organized computers use this instruction. The instruction
does not have any operand field. Uses top element of stack.
a. SUB;
b. ADD;

CLASS II: Here address field is register address.

4. Register(direct) mode – processor registers hold the operands. So, address field is
register.
ADD R1, R2; Adds contents of registers of R1 and R2 and stores the result in R1.

5. Register indirect mode – instruction specifies an address of CPU register that holds
the address of the operand in memory.
LD R1;
It results in the operation AC <- M[R1].

Op-code R1(register)

Instruction

Memory address
Operand

Register file
Memory
6. Auto-increment or Auto-decrement mode - the address of an operand is contained in a
register. However, with autoincrement mode the contents of the register is incremented each
time the instruction is executed. e.g. Array address
Symbol: (R)+ or -(R)

CLASS III: Here, address field is a memory address.

Effective Address(EA): Sometimes the instructions directly gives the address of the operand
in its format. Sometimes the instruction does not give the operand or its address explicitly,
instead of that it specifies the information from which the memory address of the operand can
be determined. This address is referred to as effective address.

7. Direct or Absolute addressing mode – In this mode the instrution mode contains the
memory address of the operand explicitly. Thus, the address part of the instruction is the
effective address. The operand address is directly available in the instruction.
Example: STA 2500H: stores the content of the accumulator in the memory locatin 2500H.
LDA 2500H: Loads the accumulator with the content of the memory location 2500H.
 Instruction
Op-code Address

Operand

Memory
8. Indirect Addressing Mode :

Instruction
Op-code Address

Address of
Operand1000

Operand 1000
Here, instruction gives a memory address in its
address field which holds the address of the
operand. Memory

Example: MOV R1, (X) : Content of the location whose address is given in X is loaded into
register R1. LDA (X)
Class IV: Address field does not contain an effective address. The effective address is
calculated from the following relation:

Effective Address = address part of instruction + content of a CPU special register.

9. Relative addressing mode or PC-relative addressing mode: the effective address is

obtained by adding the content of program counter(PC) register with address part of the
instruction. The instruction specifies the memory address of operand as the relative position
of the current instruction address.
Instruction
Op-code offset

Operand address = content of PC + offset

Example: JR 20: Branch to a location relative to the value 20 (offset)
 Memory
PC
Address 2002

After instruction fetch

1999
Op-code (JR)
2000
20 (offset) +
2001

PC
2022
2022

Branch address
 10. Indexed addressing mode : In this mode the effective address is
determined by adding the content of index register (XR) with the address
part of the instruction.
Instruction
Op-code offset

Operand address = Address(offset) + content of XR

This mode is useful for operand array.

The address part of instruction gives the starting address of an operand

array in memory.

Eample: Let an operand array starts at memory address 1000 and assume
that the index (XR) contains the value 0002. Suppose the instruction is:
LDA 1000
The effective address of the operand is calculated as:
Effective address = 1000 + content of XR = 1002

11. Base register address mode: This mode is used for relocation of the
programs in the memory.
In this mode, the content of the base register(BR) is added to the address
part of the instruction obtain the effective address.
Instruction
Op-code offset

Operand address = content of base register + offset

Example: MOV DX, [BX+04]

 INTERRUPT

Interrupt : The term interrupt referes to some exceptional event that

causes the CPU to temporarily halt its current program execution to carry
out some specific task.

Interrupt Handler: The program that handles such an event is called an

interrupt handler, also called an interrupt service routine(ISR). It is a
subroutine that gets executed whenever an interrupt is generated.
IEN – Interrupt Enable
FGI – Input Flag
FGO – Output Flag
 INSTRUCTION SET

An instruction set of a processor is a collection that defines all the
instructions.

A complete instruction set is often referred to as the instruction set
archetecture(ISA)

An instruction from the set alone can be used in a program that runs on
the processor.
Characteristics of Instruction Set:

1. Completeness
2. Efficiency
3. Regularity
4. Compatibility
 Complex Instruction Set Computer(CISC)
Major Characteristics:

1. A large number of instruction types used – typically from 100 to 250 instructions.

2. A large number of addressing modes used – typically from 5 to 15 different modes.

3. Some instructions that perform specialized tasks are used infrequently.

4. Variable length instruction formats.

5. Small number of general-purpose registers(GPRs) – typically 8-24 GPRs.

6. Clock per instruction(CPI) lies between 2 and 15.

7. Mostly micro-programmed control units.

8. Most instructions manupulate operands in memory.

 Reduced Instruction Set Computer(RISC)
Major Characteristics:
1. Relatively few number of instruction types – typically less than 100 instructions
2. Relatively few addressing modes – typically less than or equal to 5.
3. Fixed length, easily decoded instruction formats.
4. Large number of general purpose registers (GPRs) typically 32- 192 (GPRs)
5. Mostly split data cache and instruction cache.
6. Clock per instruction (CPI) lies between 1 and 2.
7. Mostly hardwired control units.
8. Memory access limited to load and store instructions.
9. All operations are executed within registers of the CPU.